source: rtems/cpukit/rtems/include/rtems/rtems/cache.h @ 8ef3818

4.104.114.84.95
Last change on this file since 8ef3818 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 19:57:02

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*  cache.h
2 *
3 *  Cache Manager
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *
13 *  The functions in this file define the API to the RTEMS Cache Manager and
14 *  are divided into data cache and instruction cache functions. Data cache
15 *  functions are only declared if a data cache is supported. Instruction
16 *  cache functions are only declared if an instruction cache is supported.
17 *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
18 *  defined, where x E {DATA, INST}. These definitions are found in the CPU
19 *  dependent source files in the supercore, often
20 * 
21 *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
22 * 
23 *  The functions below are implemented with CPU dependent inline routines
24 *  also found in the above file. In the event that a CPU does not support a
25 *  specific function, the CPU dependent routine does nothing (but does exist).
26 * 
27 *  At this point, the Cache Manager makes no considerations, and provides no
28 *  support for BSP specific issues such as a secondary cache. In such a system,
29 *  the CPU dependent routines would have to be modified, or a BSP layer added
30 *  to this Manager.
31 */
32
33#ifndef __CACHE_h
34#define __CACHE_h
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/system.h>
41#include <sys/types.h>
42
43
44/* THESE FUNCTIONS ONLY EXIST IF WE HAVE A DATA CACHE */
45#if defined(_CPU_DATA_CACHE_ALIGNMENT)
46
47/*
48 * This function is called to flush the data cache by performing cache
49 * copybacks. It must determine how many cache lines need to be copied
50 * back and then perform the copybacks.
51 */
52void rtems_flush_multiple_data_cache_lines( const void *, size_t );
53
54/*
55 * This function is responsible for performing a data cache invalidate.
56 * It must determine how many cache lines need to be invalidated and then
57 * perform the invalidations.
58 */
59void rtems_invalidate_multiple_data_cache_lines( const void *, size_t );
60
61/*
62 * This function is responsible for performing a data cache flush.
63 * It flushes the entire cache.
64 */
65void rtems_flush_entire_data_cache( void );
66
67/*
68 * This function is responsible for performing a data cache
69 * invalidate. It invalidates the entire cache.
70 */
71void rtems_invalidate_entire_data_cache( void );
72
73/*
74 * This function returns the data cache granularity.
75 */
76int rtems_get_data_cache_line_size( void );
77
78/*
79 * This function freezes the data cache.
80 */
81void rtems_freeze_data_cache( void );
82
83/*
84 * This function unfreezes the data cache.
85 */
86void rtems_unfreeze_data_cache( void );
87
88/*
89 * These functions enable/disable the data cache.
90 */
91void rtems_enable_data_cache( void );
92void rtems_disable_data_cache( void );
93#endif
94
95
96/* THESE FUNCTIONS ONLY EXIST IF WE HAVE AN INSTRUCTION CACHE */
97#if defined(_CPU_INST_CACHE_ALIGNMENT)
98
99/*
100 * This function is responsible for performing an instruction cache
101 * invalidate. It must determine how many cache lines need to be invalidated
102 * and then perform the invalidations.
103 */
104void rtems_invalidate_multiple_inst_cache_lines( const void *, size_t );
105
106/*
107 * This function is responsible for performing an instruction cache
108 * invalidate. It invalidates the entire cache.
109 */
110void rtems_invalidate_entire_inst_cache( void );
111
112/*
113 * This function returns the instruction cache granularity.
114 */
115int rtems_get_inst_cache_line_size( void );
116
117/*
118 * This function freezes the instruction cache.
119 */
120void rtems_freeze_inst_cache( void );
121
122/*
123 * This function unfreezes the instruction cache.
124 */
125void rtems_unfreeze_inst_cache( void );
126
127/*
128 * These functions enable/disable the instruction cache.
129 */
130void rtems_enable_inst_cache( void );
131void rtems_disable_inst_cache( void );
132#endif
133
134
135#ifdef __cplusplus
136}
137#endif
138
139#endif
140/* end of include file */
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