1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* PCI (Static) Configuration Library |
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4 | * |
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5 | * COPYRIGHT (c) 2010 Cobham Gaisler AB. |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * |
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16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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26 | * POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | /* |
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30 | * The Host Bridge bus must be declared by user. It contains the static |
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31 | * configuration used to setup the devices/functions. |
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32 | */ |
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33 | |
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34 | /* Configure headers */ |
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35 | #define PCI_CFG_STATIC_LIB |
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36 | |
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37 | #include <stdlib.h> |
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38 | #include <pci.h> |
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39 | #include <pci/access.h> |
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40 | #include <pci/cfg.h> |
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41 | |
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42 | #include "pci_internal.h" |
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43 | |
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44 | #define PCI_CFG_R8(dev, args...) pci_cfg_r8(dev, args) |
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45 | #define PCI_CFG_R16(dev, args...) pci_cfg_r16(dev, args) |
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46 | #define PCI_CFG_R32(dev, args...) pci_cfg_r32(dev, args) |
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47 | #define PCI_CFG_W8(dev, args...) pci_cfg_w8(dev, args) |
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48 | #define PCI_CFG_W16(dev, args...) pci_cfg_w16(dev, args) |
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49 | #define PCI_CFG_W32(dev, args...) pci_cfg_w32(dev, args) |
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50 | |
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51 | /* Enumrate one bus if device is a bridge, and all it's subordinate buses */ |
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52 | static int pci_init_dev(struct pci_dev *dev, void *unused) |
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53 | { |
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54 | uint32_t tmp; |
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55 | uint16_t tmp16, cmd; |
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56 | struct pci_bus *bridge; |
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57 | int maxbars, i, romofs; |
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58 | pci_dev_t pcidev = dev->busdevfun; |
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59 | struct pci_res *res; |
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60 | |
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61 | /* Init Device */ |
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62 | |
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63 | /* Set command to reset values, it disables bus |
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64 | * mastering and address responses. |
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65 | */ |
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66 | PCI_CFG_W16(pcidev, PCIR_COMMAND, 0); |
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67 | |
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68 | /* Clear any already set status bits */ |
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69 | PCI_CFG_W16(pcidev, PCIR_STATUS, 0xf900); |
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70 | |
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71 | /* Set latency timer to 64 */ |
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72 | PCI_CFG_W8(pcidev, PCIR_LATTIMER, 64); |
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73 | |
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74 | /* Set System IRQ of PIN */ |
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75 | PCI_CFG_W8(pcidev, PCIR_INTLINE, dev->sysirq); |
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76 | |
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77 | cmd = dev->command; |
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78 | |
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79 | if ((dev->flags & PCI_DEV_BRIDGE) == 0) { |
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80 | /* Disable Cardbus CIS Pointer */ |
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81 | PCI_CFG_W32(pcidev, PCIR_CIS, 0); |
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82 | |
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83 | romofs = PCIR_BIOS; |
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84 | maxbars = 6; |
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85 | } else { |
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86 | /* Init Bridge */ |
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87 | |
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88 | /* Configure bridge (no support for 64-bit) */ |
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89 | PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0); |
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90 | PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0); |
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91 | |
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92 | bridge = (struct pci_bus *)dev; |
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93 | tmp = (64 << 24) | (bridge->sord << 16) | |
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94 | (bridge->num << 8) | bridge->pri; |
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95 | PCI_CFG_W32(pcidev, PCIR_PRIBUS_1, tmp); |
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96 | |
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97 | /*** Setup I/O Bridge Window ***/ |
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98 | res = &dev->resources[BRIDGE_RES_IO]; |
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99 | if (res->size > 0) { |
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100 | tmp16 = ((res->end-1) & 0x0000f000) | |
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101 | ((res->start & 0x0000f000) >> 8); |
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102 | tmp = ((res->end-1) & 0xffff0000) | (res->start >> 16); |
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103 | cmd |= PCIM_CMD_PORTEN; |
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104 | } else { |
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105 | tmp16 = 0x00ff; |
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106 | tmp = 0; |
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107 | } |
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108 | /* I/O Limit and Base */ |
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109 | PCI_CFG_W16(pcidev, PCIR_IOBASEL_1, tmp16); |
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110 | PCI_CFG_W32(pcidev, PCIR_IOBASEH_1, tmp); |
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111 | |
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112 | /*** Setup MEMIO Bridge Window ***/ |
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113 | res = &dev->resources[BRIDGE_RES_MEMIO]; |
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114 | if (res->size > 0) { |
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115 | tmp = ((res->end-1) & 0xffff0000) | |
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116 | (res->start >> 16); |
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117 | cmd |= PCIM_CMD_MEMEN; |
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118 | } else { |
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119 | tmp = 0x0000ffff; |
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120 | } |
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121 | /* MEMIO Limit and Base */ |
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122 | PCI_CFG_W32(pcidev, PCIR_MEMBASE_1, tmp); |
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123 | |
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124 | /*** Setup MEM Bridge Window ***/ |
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125 | res = &dev->resources[BRIDGE_RES_MEM]; |
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126 | if (res->size > 0) { |
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127 | tmp = ((res->end-1) & 0xffff0000) | |
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128 | (res->start >> 16); |
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129 | cmd |= PCIM_CMD_MEMEN; |
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130 | } else { |
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131 | tmp = 0x0000ffff; |
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132 | } |
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133 | /* MEM Limit and Base */ |
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134 | PCI_CFG_W32(pcidev, PCIR_PMBASEL_1, tmp); |
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135 | /* 64-bit space not supported */ |
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136 | PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0); |
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137 | PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0); |
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138 | |
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139 | cmd |= PCIM_CMD_BUSMASTEREN; |
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140 | romofs = PCIR_BIOS_1; |
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141 | maxbars = 2; |
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142 | } |
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143 | |
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144 | /* Init BARs */ |
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145 | for (i = 0; i < maxbars; i++) { |
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146 | res = &dev->resources[i]; |
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147 | if (res->flags & PCI_RES_TYPE_MASK) { |
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148 | PCI_CFG_W32(pcidev, PCIR_BAR(0) + 4*i, |
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149 | res->start); |
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150 | if ((res->flags & PCI_RES_TYPE_MASK) == PCI_RES_IO) |
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151 | cmd |= PCIM_CMD_PORTEN; |
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152 | else |
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153 | cmd |= PCIM_CMD_MEMEN; |
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154 | } |
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155 | } |
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156 | res = &dev->resources[DEV_RES_ROM]; |
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157 | if (res->flags & PCI_RES_TYPE_MASK) { |
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158 | PCI_CFG_W32(pcidev, romofs, res->start|PCIM_BIOS_ENABLE); |
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159 | cmd |= PCIM_CMD_MEMEN; |
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160 | } |
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161 | PCI_CFG_W16(pcidev, PCIR_COMMAND, cmd); |
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162 | |
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163 | return 0; |
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164 | } |
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165 | |
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166 | /* Assume that user has defined static setup array in pci_hb */ |
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167 | int pci_config_static(void) |
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168 | { |
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169 | pci_bus_cnt = pci_hb.sord + 1; |
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170 | pci_system_type = PCI_SYSTEM_HOST; |
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171 | |
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172 | /* Init all PCI devices according to depth-first search algorithm */ |
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173 | return pci_for_each_dev(pci_init_dev, NULL); |
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174 | } |
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