[a31845f7] | 1 | /* Read current PCI configuration that bootloader or BIOS has already setup |
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| 2 | * and initialize the PCI structures. |
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| 3 | * |
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[71e8a5c] | 4 | * COPYRIGHT (c) 2010 Cobham Gaisler AB. |
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[a31845f7] | 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[e53daed] | 8 | * http://www.rtems.org/license/LICENSE. |
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[a31845f7] | 9 | */ |
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| 10 | |
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| 11 | #include <rtems.h> |
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| 12 | #include <stdlib.h> |
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| 13 | #include <rtems/bspIo.h> |
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| 14 | #include <pci/cfg.h> |
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| 15 | #include <pci/access.h> |
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| 16 | |
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[f4bf22c] | 17 | #include "pci_internal.h" |
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| 18 | |
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[a31845f7] | 19 | /* PCI Library |
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| 20 | * (For debugging it might be good to use other functions or the driver's |
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| 21 | * directly) |
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| 22 | */ |
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| 23 | #define PCI_CFG_R8(dev, args...) pci_cfg_r8(dev, args) |
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| 24 | #define PCI_CFG_R16(dev, args...) pci_cfg_r16(dev, args) |
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| 25 | #define PCI_CFG_R32(dev, args...) pci_cfg_r32(dev, args) |
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| 26 | #define PCI_CFG_W8(dev, args...) pci_cfg_w8(dev, args) |
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| 27 | #define PCI_CFG_W16(dev, args...) pci_cfg_w16(dev, args) |
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| 28 | #define PCI_CFG_W32(dev, args...) pci_cfg_w32(dev, args) |
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| 29 | |
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| 30 | #ifdef DEBUG |
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| 31 | #define DBG(args...) printk(args) |
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| 32 | #else |
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| 33 | #define DBG(args...) |
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| 34 | #endif |
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| 35 | |
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| 36 | /* The Host Bridge bus is initialized here */ |
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| 37 | extern struct pci_bus pci_hb; |
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| 38 | |
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| 39 | /* Check if address is accessible from host */ |
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| 40 | static int pci_read_addressable(struct pci_dev *dev, struct pci_res *res) |
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| 41 | { |
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| 42 | struct pci_bus *bus = dev->bus; |
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| 43 | int type = res->flags & PCI_RES_TYPE_MASK; |
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| 44 | struct pci_res *range0, *range1; |
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| 45 | |
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| 46 | if (type == PCI_BUS_IO && (bus->flags & PCI_BUS_IO) == 0) |
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| 47 | return 0; |
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| 48 | |
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| 49 | /* Assume that host bridge can access all */ |
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| 50 | if (bus->pri == 0) |
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| 51 | return 1; |
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| 52 | |
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| 53 | range1 = NULL; |
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| 54 | switch (type) { |
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| 55 | case PCI_RES_IO: |
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| 56 | range0 = &bus->dev.resources[BRIDGE_RES_IO]; |
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| 57 | break; |
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| 58 | case PCI_RES_MEM: |
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| 59 | range1 = &bus->dev.resources[BRIDGE_RES_MEM]; |
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| 60 | default: |
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| 61 | case PCI_RES_MEMIO: |
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| 62 | range0 = &bus->dev.resources[BRIDGE_RES_MEMIO]; |
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| 63 | break; |
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| 64 | } |
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| 65 | if ((res->start >= range0->start) && (res->end <= range0->end)) { |
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| 66 | return pci_read_addressable(&bus->dev, range0); |
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| 67 | } else if (range1 && (res->start >= range1->start) && |
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| 68 | (res->end <= range1->end)) { |
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| 69 | return pci_read_addressable(&bus->dev, range1); |
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| 70 | } |
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| 71 | |
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| 72 | return 0; |
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| 73 | } |
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| 74 | |
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| 75 | static void pci_read_bar(struct pci_dev *dev, int bar) |
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| 76 | { |
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| 77 | uint32_t orig, size, mask; |
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| 78 | struct pci_res *res = &dev->resources[bar]; |
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| 79 | pci_dev_t pcidev = dev->busdevfun; |
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| 80 | int ofs; |
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| 81 | #ifdef DEBUG |
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| 82 | char *str; |
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| 83 | #define DBG_SET_STR(str, val) str = (val) |
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| 84 | #else |
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| 85 | #define DBG_SET_STR(str, val) |
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| 86 | #endif |
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| 87 | |
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| 88 | DBG("Bus: %x, Slot: %x, function: %x, bar%d\n", |
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| 89 | PCI_DEV_EXPAND(pcidev), bar); |
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| 90 | |
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| 91 | res->bar = bar; |
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| 92 | if (bar == DEV_RES_ROM) { |
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| 93 | if (dev->flags & PCI_DEV_BRIDGE) |
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[c1c37a1] | 94 | ofs = PCIR_BIOS_1; |
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[a31845f7] | 95 | else |
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[c1c37a1] | 96 | ofs = PCIR_BIOS; |
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[a31845f7] | 97 | } else { |
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[c1c37a1] | 98 | ofs = PCIR_BAR(0) + (bar << 2); |
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[a31845f7] | 99 | } |
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| 100 | |
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| 101 | PCI_CFG_R32(pcidev, ofs, &orig); |
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| 102 | PCI_CFG_W32(pcidev, ofs, 0xffffffff); |
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| 103 | PCI_CFG_R32(pcidev, ofs, &size); |
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| 104 | PCI_CFG_W32(pcidev, ofs, orig); |
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| 105 | |
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| 106 | if (size == 0 || size == 0xffffffff) |
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| 107 | return; |
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| 108 | if (bar == DEV_RES_ROM) { |
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[c1c37a1] | 109 | mask = PCIM_BIOS_ADDR_MASK; |
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[a31845f7] | 110 | DBG_SET_STR(str, "ROM"); |
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| 111 | if (dev->bus->flags & PCI_BUS_MEM) |
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| 112 | res->flags = PCI_RES_MEM; |
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| 113 | else |
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| 114 | res->flags = PCI_RES_MEMIO; |
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| 115 | } else if (((size & 0x1) == 0) && (size & 0x6)) { |
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| 116 | /* unsupported Memory type */ |
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| 117 | return; |
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| 118 | } else { |
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| 119 | mask = ~0xf; |
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| 120 | if (size & 0x1) { |
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| 121 | /* I/O */ |
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| 122 | mask = ~0x3; |
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| 123 | res->flags = PCI_RES_IO; |
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| 124 | DBG_SET_STR(str, "I/O"); |
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| 125 | if (size & 0xffff0000) |
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| 126 | res->flags |= PCI_RES_IO32; |
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| 127 | /* Limit size of I/O space to 256 byte */ |
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| 128 | size |= 0xffffff00; |
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| 129 | if ((dev->bus->flags & PCI_BUS_IO) == 0) { |
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| 130 | res->flags |= PCI_RES_FAIL; |
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| 131 | dev->flags |= PCI_DEV_RES_FAIL; |
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| 132 | } |
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| 133 | } else { |
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| 134 | /* Memory */ |
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| 135 | if (size & 0x8) { |
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| 136 | /* Prefetchable */ |
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| 137 | res->flags = PCI_RES_MEM; |
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| 138 | DBG_SET_STR(str, "MEM"); |
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| 139 | } else { |
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| 140 | res->flags = PCI_RES_MEMIO; |
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| 141 | DBG_SET_STR(str, "MEMIO"); |
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| 142 | } |
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| 143 | } |
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| 144 | } |
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| 145 | res->start = orig & mask; |
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| 146 | size &= mask; |
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| 147 | res->size = ~size + 1; |
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| 148 | res->boundary = res->size; |
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| 149 | res->end = res->start + res->size; |
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| 150 | |
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| 151 | DBG("Bus: %x, Slot: %x, function: %x, %s bar%d size: %x\n", |
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| 152 | PCI_DEV_EXPAND(pcidev), str, bar, res->size); |
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| 153 | |
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| 154 | /* Check if BAR is addressable by host */ |
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| 155 | if (pci_read_addressable(dev, res) == 0) { |
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| 156 | /* No matching bridge window contains this BAR */ |
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| 157 | res->flags |= PCI_RES_FAIL; |
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| 158 | dev->flags |= PCI_DEV_RES_FAIL; |
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| 159 | } |
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| 160 | } |
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| 161 | |
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| 162 | static void pci_read_devs(struct pci_bus *bus) |
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| 163 | { |
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| 164 | uint32_t id, tmp; |
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| 165 | uint16_t tmp16; |
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| 166 | uint8_t header; |
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| 167 | int slot, func, fail, i, maxbars, max_sord; |
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| 168 | struct pci_dev *dev, **listptr; |
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| 169 | struct pci_bus *bridge; |
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| 170 | pci_dev_t pcidev; |
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| 171 | struct pci_res *res; |
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| 172 | |
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| 173 | DBG("Scanning bus %d\n", bus->num); |
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| 174 | |
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| 175 | max_sord = bus->num; |
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| 176 | listptr = &bus->devs; |
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[c1c37a1] | 177 | for (slot = 0; slot <= PCI_SLOTMAX; slot++) { |
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[a31845f7] | 178 | |
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| 179 | /* Slot address */ |
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| 180 | pcidev = PCI_DEV(bus->num, slot, 0); |
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| 181 | |
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[c1c37a1] | 182 | for (func = 0; func <= PCI_FUNCMAX; func++, pcidev++) { |
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[a31845f7] | 183 | |
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[c1c37a1] | 184 | fail = PCI_CFG_R32(pcidev, PCIR_VENDOR, &id); |
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[a31845f7] | 185 | if (fail || id == 0xffffffff || id == 0) { |
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| 186 | /* |
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| 187 | * This slot is empty |
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| 188 | */ |
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| 189 | if (func == 0) |
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| 190 | break; |
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| 191 | else |
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| 192 | continue; |
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| 193 | } |
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| 194 | |
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| 195 | DBG("Found PCIDEV 0x%x at (bus %x, slot %x, func %x)\n", |
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| 196 | id, bus, slot, func); |
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| 197 | |
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[c1c37a1] | 198 | PCI_CFG_R32(pcidev, PCIR_REVID, &tmp); |
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[a31845f7] | 199 | tmp >>= 16; |
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[c1c37a1] | 200 | dev = pci_dev_create(tmp == PCID_PCI2PCI_BRIDGE); |
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[a31845f7] | 201 | *listptr = dev; |
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| 202 | listptr = &dev->next; |
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| 203 | |
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| 204 | dev->busdevfun = pcidev; |
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| 205 | dev->bus = bus; |
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[c1c37a1] | 206 | PCI_CFG_R16(pcidev, PCIR_VENDOR, &dev->vendor); |
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| 207 | PCI_CFG_R16(pcidev, PCIR_DEVICE, &dev->device); |
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| 208 | PCI_CFG_R32(pcidev, PCIR_REVID, &dev->classrev); |
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[a31845f7] | 209 | |
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[c1c37a1] | 210 | if (tmp == PCID_PCI2PCI_BRIDGE) { |
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[a31845f7] | 211 | DBG("Found PCI-PCI Bridge 0x%x at " |
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| 212 | "(bus %x, slot %x, func %x)\n", |
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| 213 | id, bus, slot, func); |
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| 214 | dev->flags = PCI_DEV_BRIDGE; |
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| 215 | bridge = (struct pci_bus *)dev; |
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| 216 | |
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[c1c37a1] | 217 | PCI_CFG_R32(pcidev, PCIR_PRIBUS_1, &tmp); |
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[a31845f7] | 218 | bridge->pri = tmp & 0xff; |
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| 219 | bridge->num = (tmp >> 8) & 0xff; |
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| 220 | bridge->sord = (tmp >> 16) & 0xff; |
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| 221 | if (bridge->sord > max_sord) |
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| 222 | max_sord = bridge->sord; |
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| 223 | |
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| 224 | DBG(" Primary %x, Secondary %x, " |
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| 225 | "Subordinate %x\n", |
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| 226 | bridge->pri, bridge->num, bridge->sord); |
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| 227 | |
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| 228 | /*** Probe Bridge Spaces ***/ |
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| 229 | |
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| 230 | /* MEMIO Window - always implemented */ |
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| 231 | bridge->flags = PCI_BUS_MEMIO; |
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| 232 | res = &bridge->dev.resources[BRIDGE_RES_MEMIO]; |
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| 233 | res->flags = PCI_RES_MEMIO; |
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| 234 | res->bar = BRIDGE_RES_MEMIO; |
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| 235 | PCI_CFG_R32(pcidev, 0x20, &tmp); |
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| 236 | res->start = (tmp & 0xfff0) << 16; |
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| 237 | res->end = 1 + ((tmp & 0xfff00000) | 0xfffff); |
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| 238 | if (res->end <= res->start) { |
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| 239 | /* Window disabled */ |
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| 240 | res->end = res->start = 0; |
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| 241 | } |
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| 242 | res->size = res->end - res->start; |
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| 243 | |
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| 244 | /* I/O Window - optional */ |
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| 245 | res = &bridge->dev.resources[BRIDGE_RES_IO]; |
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| 246 | res->bar = BRIDGE_RES_IO; |
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| 247 | PCI_CFG_R32(pcidev, 0x30, &tmp); |
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| 248 | PCI_CFG_R16(pcidev, 0x1c, &tmp16); |
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| 249 | if (tmp != 0 || tmp16 != 0) { |
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| 250 | bridge->flags |= PCI_BUS_IO; |
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| 251 | res->flags = PCI_RES_IO; |
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| 252 | if (tmp16 & 0x1) { |
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| 253 | bridge->flags |= PCI_BUS_IO32; |
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| 254 | res->flags |= PCI_RES_IO32; |
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| 255 | } |
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| 256 | |
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| 257 | res->start = (tmp & 0xffff) << 16 | |
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| 258 | (tmp16 & 0xf0) << 8; |
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| 259 | res->end = 1 + ((tmp & 0xffff0000) | |
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| 260 | (tmp16 & 0xf000) | |
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| 261 | 0xfff); |
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| 262 | if (res->end <= res->start) { |
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| 263 | /* Window disabled */ |
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| 264 | res->end = res->start = 0; |
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| 265 | } |
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| 266 | res->size = res->end - res->start; |
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| 267 | } |
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| 268 | |
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| 269 | /* MEM Window - optional */ |
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| 270 | res = &bridge->dev.resources[BRIDGE_RES_MEM]; |
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| 271 | res->bar = BRIDGE_RES_MEM; |
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| 272 | PCI_CFG_R32(pcidev, 0x24, &tmp); |
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| 273 | if (tmp != 0) { |
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| 274 | bridge->flags |= PCI_BUS_MEM; |
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| 275 | res->flags = PCI_RES_MEM; |
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| 276 | res->start = (tmp & 0xfff0) << 16; |
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| 277 | res->end = 1 + ((tmp & 0xfff00000) | |
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| 278 | 0xfffff); |
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| 279 | if (res->end <= res->start) { |
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| 280 | /* Window disabled */ |
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| 281 | res->end = res->start = 0; |
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| 282 | } |
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| 283 | res->size = res->end - res->start; |
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| 284 | } |
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| 285 | |
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| 286 | /* Scan Secondary Bus */ |
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| 287 | pci_read_devs(bridge); |
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| 288 | |
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| 289 | /* Only 2 BARs for Bridges */ |
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| 290 | maxbars = 2; |
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| 291 | } else { |
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| 292 | /* Devices have subsytem device and vendor ID */ |
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[c1c37a1] | 293 | PCI_CFG_R16(pcidev, PCIR_SUBVEND_0, |
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[a31845f7] | 294 | &dev->subvendor); |
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[c1c37a1] | 295 | PCI_CFG_R16(pcidev, PCIR_SUBDEV_0, |
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[a31845f7] | 296 | &dev->subdevice); |
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| 297 | |
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| 298 | /* Normal PCI Device has max 6 BARs */ |
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| 299 | maxbars = 6; |
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| 300 | } |
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| 301 | |
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| 302 | /* Probe BARs */ |
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| 303 | for (i = 0; i < maxbars; i++) |
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| 304 | pci_read_bar(dev, i); |
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| 305 | pci_read_bar(dev, DEV_RES_ROM); |
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| 306 | |
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| 307 | /* Get System Interrupt/Vector for device. |
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| 308 | * 0 means no-IRQ |
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| 309 | */ |
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[c1c37a1] | 310 | PCI_CFG_R8(pcidev, PCIR_INTLINE, &dev->sysirq); |
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[a31845f7] | 311 | |
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| 312 | /* Stop if not a multi-function device */ |
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| 313 | if (func == 0) { |
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[c1c37a1] | 314 | pci_cfg_r8(pcidev, PCIR_HDRTYPE, &header); |
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| 315 | if ((header & PCIM_MFDEV) == 0) |
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[a31845f7] | 316 | break; |
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| 317 | } |
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| 318 | } |
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| 319 | } |
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| 320 | |
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| 321 | if (bus->num == 0) |
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| 322 | bus->sord = max_sord; |
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| 323 | } |
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| 324 | |
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| 325 | int pci_config_read(void) |
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| 326 | { |
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| 327 | pci_system_type = PCI_SYSTEM_HOST; |
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| 328 | |
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| 329 | /* Find all devices and buses */ |
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| 330 | pci_hb.flags = PCI_BUS_IO|PCI_BUS_MEMIO|PCI_BUS_MEM; |
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| 331 | pci_hb.dev.flags = PCI_DEV_BRIDGE; |
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| 332 | pci_read_devs(&pci_hb); |
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| 333 | pci_bus_cnt = pci_hb.sord + 1; |
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| 334 | if (pci_hb.devs == NULL) |
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| 335 | return 0; |
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| 336 | |
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| 337 | return 0; |
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| 338 | } |
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