[a31845f7] | 1 | /* Read current PCI configuration that bootloader or BIOS has already setup |
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| 2 | * and initialize the PCI structures. |
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| 3 | * |
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[71e8a5c] | 4 | * COPYRIGHT (c) 2010 Cobham Gaisler AB. |
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[a31845f7] | 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * http://www.rtems.com/license/LICENSE. |
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| 9 | */ |
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| 10 | |
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| 11 | #include <rtems.h> |
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| 12 | #include <stdlib.h> |
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| 13 | #include <rtems/bspIo.h> |
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| 14 | #include <pci/cfg.h> |
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| 15 | #include <pci/access.h> |
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| 16 | |
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| 17 | /* PCI Library |
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| 18 | * (For debugging it might be good to use other functions or the driver's |
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| 19 | * directly) |
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| 20 | */ |
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| 21 | #define PCI_CFG_R8(dev, args...) pci_cfg_r8(dev, args) |
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| 22 | #define PCI_CFG_R16(dev, args...) pci_cfg_r16(dev, args) |
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| 23 | #define PCI_CFG_R32(dev, args...) pci_cfg_r32(dev, args) |
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| 24 | #define PCI_CFG_W8(dev, args...) pci_cfg_w8(dev, args) |
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| 25 | #define PCI_CFG_W16(dev, args...) pci_cfg_w16(dev, args) |
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| 26 | #define PCI_CFG_W32(dev, args...) pci_cfg_w32(dev, args) |
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| 27 | |
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| 28 | #ifdef DEBUG |
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| 29 | #define DBG(args...) printk(args) |
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| 30 | #else |
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| 31 | #define DBG(args...) |
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| 32 | #endif |
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| 33 | |
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| 34 | /* Number of buses */ |
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| 35 | extern int pci_bus_cnt; |
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| 36 | |
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| 37 | /* The Host Bridge bus is initialized here */ |
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| 38 | extern struct pci_bus pci_hb; |
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| 39 | |
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| 40 | static struct pci_dev *pci_dev_create(int isbus) |
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| 41 | { |
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| 42 | void *ptr; |
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| 43 | int size; |
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| 44 | |
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| 45 | if (isbus) |
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| 46 | size = sizeof(struct pci_bus); |
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| 47 | else |
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| 48 | size = sizeof(struct pci_dev); |
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| 49 | |
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| 50 | ptr = malloc(size); |
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| 51 | if (!ptr) |
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| 52 | rtems_fatal_error_occurred(RTEMS_NO_MEMORY); |
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| 53 | memset(ptr, 0, size); |
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| 54 | return ptr; |
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| 55 | } |
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| 56 | |
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| 57 | /* Check if address is accessible from host */ |
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| 58 | static int pci_read_addressable(struct pci_dev *dev, struct pci_res *res) |
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| 59 | { |
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| 60 | struct pci_bus *bus = dev->bus; |
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| 61 | int type = res->flags & PCI_RES_TYPE_MASK; |
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| 62 | struct pci_res *range0, *range1; |
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| 63 | |
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| 64 | if (type == PCI_BUS_IO && (bus->flags & PCI_BUS_IO) == 0) |
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| 65 | return 0; |
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| 66 | |
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| 67 | /* Assume that host bridge can access all */ |
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| 68 | if (bus->pri == 0) |
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| 69 | return 1; |
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| 70 | |
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| 71 | range1 = NULL; |
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| 72 | switch (type) { |
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| 73 | case PCI_RES_IO: |
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| 74 | range0 = &bus->dev.resources[BRIDGE_RES_IO]; |
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| 75 | break; |
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| 76 | case PCI_RES_MEM: |
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| 77 | range1 = &bus->dev.resources[BRIDGE_RES_MEM]; |
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| 78 | default: |
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| 79 | case PCI_RES_MEMIO: |
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| 80 | range0 = &bus->dev.resources[BRIDGE_RES_MEMIO]; |
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| 81 | break; |
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| 82 | } |
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| 83 | if ((res->start >= range0->start) && (res->end <= range0->end)) { |
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| 84 | return pci_read_addressable(&bus->dev, range0); |
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| 85 | } else if (range1 && (res->start >= range1->start) && |
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| 86 | (res->end <= range1->end)) { |
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| 87 | return pci_read_addressable(&bus->dev, range1); |
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| 88 | } |
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| 89 | |
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| 90 | return 0; |
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| 91 | } |
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| 92 | |
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| 93 | static void pci_read_bar(struct pci_dev *dev, int bar) |
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| 94 | { |
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| 95 | uint32_t orig, size, mask; |
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| 96 | struct pci_res *res = &dev->resources[bar]; |
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| 97 | pci_dev_t pcidev = dev->busdevfun; |
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| 98 | int ofs; |
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| 99 | #ifdef DEBUG |
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| 100 | char *str; |
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| 101 | #define DBG_SET_STR(str, val) str = (val) |
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| 102 | #else |
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| 103 | #define DBG_SET_STR(str, val) |
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| 104 | #endif |
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| 105 | |
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| 106 | DBG("Bus: %x, Slot: %x, function: %x, bar%d\n", |
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| 107 | PCI_DEV_EXPAND(pcidev), bar); |
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| 108 | |
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| 109 | res->bar = bar; |
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| 110 | if (bar == DEV_RES_ROM) { |
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| 111 | if (dev->flags & PCI_DEV_BRIDGE) |
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| 112 | ofs = PCI_ROM_ADDRESS1; |
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| 113 | else |
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| 114 | ofs = PCI_ROM_ADDRESS; |
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| 115 | } else { |
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| 116 | ofs = PCI_BASE_ADDRESS_0 + (bar << 2); |
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| 117 | } |
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| 118 | |
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| 119 | PCI_CFG_R32(pcidev, ofs, &orig); |
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| 120 | PCI_CFG_W32(pcidev, ofs, 0xffffffff); |
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| 121 | PCI_CFG_R32(pcidev, ofs, &size); |
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| 122 | PCI_CFG_W32(pcidev, ofs, orig); |
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| 123 | |
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| 124 | if (size == 0 || size == 0xffffffff) |
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| 125 | return; |
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| 126 | if (bar == DEV_RES_ROM) { |
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| 127 | mask = PCI_ROM_ADDRESS_MASK; |
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| 128 | DBG_SET_STR(str, "ROM"); |
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| 129 | if (dev->bus->flags & PCI_BUS_MEM) |
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| 130 | res->flags = PCI_RES_MEM; |
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| 131 | else |
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| 132 | res->flags = PCI_RES_MEMIO; |
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| 133 | } else if (((size & 0x1) == 0) && (size & 0x6)) { |
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| 134 | /* unsupported Memory type */ |
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| 135 | return; |
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| 136 | } else { |
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| 137 | mask = ~0xf; |
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| 138 | if (size & 0x1) { |
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| 139 | /* I/O */ |
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| 140 | mask = ~0x3; |
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| 141 | res->flags = PCI_RES_IO; |
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| 142 | DBG_SET_STR(str, "I/O"); |
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| 143 | if (size & 0xffff0000) |
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| 144 | res->flags |= PCI_RES_IO32; |
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| 145 | /* Limit size of I/O space to 256 byte */ |
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| 146 | size |= 0xffffff00; |
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| 147 | if ((dev->bus->flags & PCI_BUS_IO) == 0) { |
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| 148 | res->flags |= PCI_RES_FAIL; |
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| 149 | dev->flags |= PCI_DEV_RES_FAIL; |
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| 150 | } |
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| 151 | } else { |
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| 152 | /* Memory */ |
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| 153 | if (size & 0x8) { |
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| 154 | /* Prefetchable */ |
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| 155 | res->flags = PCI_RES_MEM; |
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| 156 | DBG_SET_STR(str, "MEM"); |
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| 157 | } else { |
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| 158 | res->flags = PCI_RES_MEMIO; |
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| 159 | DBG_SET_STR(str, "MEMIO"); |
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| 160 | } |
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| 161 | } |
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| 162 | } |
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| 163 | res->start = orig & mask; |
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| 164 | size &= mask; |
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| 165 | res->size = ~size + 1; |
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| 166 | res->boundary = res->size; |
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| 167 | res->end = res->start + res->size; |
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| 168 | |
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| 169 | DBG("Bus: %x, Slot: %x, function: %x, %s bar%d size: %x\n", |
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| 170 | PCI_DEV_EXPAND(pcidev), str, bar, res->size); |
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| 171 | |
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| 172 | /* Check if BAR is addressable by host */ |
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| 173 | if (pci_read_addressable(dev, res) == 0) { |
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| 174 | /* No matching bridge window contains this BAR */ |
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| 175 | res->flags |= PCI_RES_FAIL; |
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| 176 | dev->flags |= PCI_DEV_RES_FAIL; |
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| 177 | } |
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| 178 | } |
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| 179 | |
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| 180 | static void pci_read_devs(struct pci_bus *bus) |
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| 181 | { |
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| 182 | uint32_t id, tmp; |
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| 183 | uint16_t tmp16; |
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| 184 | uint8_t header; |
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| 185 | int slot, func, fail, i, maxbars, max_sord; |
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| 186 | struct pci_dev *dev, **listptr; |
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| 187 | struct pci_bus *bridge; |
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| 188 | pci_dev_t pcidev; |
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| 189 | struct pci_res *res; |
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| 190 | |
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| 191 | DBG("Scanning bus %d\n", bus->num); |
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| 192 | |
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| 193 | max_sord = bus->num; |
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| 194 | listptr = &bus->devs; |
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| 195 | for (slot = 0; slot < PCI_MAX_DEVICES; slot++) { |
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| 196 | |
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| 197 | /* Slot address */ |
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| 198 | pcidev = PCI_DEV(bus->num, slot, 0); |
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| 199 | |
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| 200 | for (func = 0; func < PCI_MAX_FUNCTIONS; func++, pcidev++) { |
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| 201 | |
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| 202 | fail = PCI_CFG_R32(pcidev, PCI_VENDOR_ID, &id); |
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| 203 | if (fail || id == 0xffffffff || id == 0) { |
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| 204 | /* |
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| 205 | * This slot is empty |
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| 206 | */ |
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| 207 | if (func == 0) |
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| 208 | break; |
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| 209 | else |
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| 210 | continue; |
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| 211 | } |
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| 212 | |
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| 213 | DBG("Found PCIDEV 0x%x at (bus %x, slot %x, func %x)\n", |
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| 214 | id, bus, slot, func); |
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| 215 | |
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| 216 | PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &tmp); |
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| 217 | tmp >>= 16; |
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| 218 | dev = pci_dev_create(tmp == PCI_CLASS_BRIDGE_PCI); |
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| 219 | *listptr = dev; |
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| 220 | listptr = &dev->next; |
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| 221 | |
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| 222 | dev->busdevfun = pcidev; |
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| 223 | dev->bus = bus; |
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| 224 | PCI_CFG_R16(pcidev, PCI_VENDOR_ID, &dev->vendor); |
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| 225 | PCI_CFG_R16(pcidev, PCI_DEVICE_ID, &dev->device); |
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| 226 | PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &dev->classrev); |
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| 227 | |
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| 228 | if (tmp == PCI_CLASS_BRIDGE_PCI) { |
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| 229 | DBG("Found PCI-PCI Bridge 0x%x at " |
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| 230 | "(bus %x, slot %x, func %x)\n", |
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| 231 | id, bus, slot, func); |
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| 232 | dev->flags = PCI_DEV_BRIDGE; |
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| 233 | bridge = (struct pci_bus *)dev; |
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| 234 | |
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| 235 | PCI_CFG_R32(pcidev, PCI_PRIMARY_BUS, &tmp); |
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| 236 | bridge->pri = tmp & 0xff; |
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| 237 | bridge->num = (tmp >> 8) & 0xff; |
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| 238 | bridge->sord = (tmp >> 16) & 0xff; |
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| 239 | if (bridge->sord > max_sord) |
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| 240 | max_sord = bridge->sord; |
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| 241 | |
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| 242 | DBG(" Primary %x, Secondary %x, " |
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| 243 | "Subordinate %x\n", |
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| 244 | bridge->pri, bridge->num, bridge->sord); |
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| 245 | |
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| 246 | /*** Probe Bridge Spaces ***/ |
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| 247 | |
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| 248 | /* MEMIO Window - always implemented */ |
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| 249 | bridge->flags = PCI_BUS_MEMIO; |
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| 250 | res = &bridge->dev.resources[BRIDGE_RES_MEMIO]; |
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| 251 | res->flags = PCI_RES_MEMIO; |
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| 252 | res->bar = BRIDGE_RES_MEMIO; |
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| 253 | PCI_CFG_R32(pcidev, 0x20, &tmp); |
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| 254 | res->start = (tmp & 0xfff0) << 16; |
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| 255 | res->end = 1 + ((tmp & 0xfff00000) | 0xfffff); |
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| 256 | if (res->end <= res->start) { |
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| 257 | /* Window disabled */ |
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| 258 | res->end = res->start = 0; |
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| 259 | } |
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| 260 | res->size = res->end - res->start; |
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| 261 | |
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| 262 | /* I/O Window - optional */ |
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| 263 | res = &bridge->dev.resources[BRIDGE_RES_IO]; |
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| 264 | res->bar = BRIDGE_RES_IO; |
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| 265 | PCI_CFG_R32(pcidev, 0x30, &tmp); |
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| 266 | PCI_CFG_R16(pcidev, 0x1c, &tmp16); |
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| 267 | if (tmp != 0 || tmp16 != 0) { |
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| 268 | bridge->flags |= PCI_BUS_IO; |
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| 269 | res->flags = PCI_RES_IO; |
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| 270 | if (tmp16 & 0x1) { |
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| 271 | bridge->flags |= PCI_BUS_IO32; |
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| 272 | res->flags |= PCI_RES_IO32; |
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| 273 | } |
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| 274 | |
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| 275 | res->start = (tmp & 0xffff) << 16 | |
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| 276 | (tmp16 & 0xf0) << 8; |
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| 277 | res->end = 1 + ((tmp & 0xffff0000) | |
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| 278 | (tmp16 & 0xf000) | |
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| 279 | 0xfff); |
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| 280 | if (res->end <= res->start) { |
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| 281 | /* Window disabled */ |
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| 282 | res->end = res->start = 0; |
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| 283 | } |
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| 284 | res->size = res->end - res->start; |
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| 285 | } |
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| 286 | |
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| 287 | /* MEM Window - optional */ |
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| 288 | res = &bridge->dev.resources[BRIDGE_RES_MEM]; |
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| 289 | res->bar = BRIDGE_RES_MEM; |
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| 290 | PCI_CFG_R32(pcidev, 0x24, &tmp); |
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| 291 | if (tmp != 0) { |
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| 292 | bridge->flags |= PCI_BUS_MEM; |
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| 293 | res->flags = PCI_RES_MEM; |
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| 294 | res->start = (tmp & 0xfff0) << 16; |
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| 295 | res->end = 1 + ((tmp & 0xfff00000) | |
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| 296 | 0xfffff); |
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| 297 | if (res->end <= res->start) { |
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| 298 | /* Window disabled */ |
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| 299 | res->end = res->start = 0; |
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| 300 | } |
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| 301 | res->size = res->end - res->start; |
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| 302 | } |
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| 303 | |
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| 304 | /* Scan Secondary Bus */ |
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| 305 | pci_read_devs(bridge); |
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| 306 | |
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| 307 | /* Only 2 BARs for Bridges */ |
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| 308 | maxbars = 2; |
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| 309 | } else { |
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| 310 | /* Devices have subsytem device and vendor ID */ |
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| 311 | PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_VENDOR_ID, |
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| 312 | &dev->subvendor); |
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| 313 | PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_ID, |
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| 314 | &dev->subdevice); |
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| 315 | |
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| 316 | /* Normal PCI Device has max 6 BARs */ |
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| 317 | maxbars = 6; |
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| 318 | } |
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| 319 | |
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| 320 | /* Probe BARs */ |
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| 321 | for (i = 0; i < maxbars; i++) |
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| 322 | pci_read_bar(dev, i); |
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| 323 | pci_read_bar(dev, DEV_RES_ROM); |
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| 324 | |
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| 325 | /* Get System Interrupt/Vector for device. |
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| 326 | * 0 means no-IRQ |
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| 327 | */ |
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| 328 | PCI_CFG_R8(pcidev, PCI_INTERRUPT_LINE, &dev->sysirq); |
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| 329 | |
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| 330 | /* Stop if not a multi-function device */ |
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| 331 | if (func == 0) { |
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| 332 | pci_cfg_r8(pcidev, PCI_HEADER_TYPE, &header); |
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| 333 | if ((header & PCI_MULTI_FUNCTION) == 0) |
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| 334 | break; |
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| 335 | } |
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| 336 | } |
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| 337 | } |
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| 338 | |
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| 339 | if (bus->num == 0) |
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| 340 | bus->sord = max_sord; |
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| 341 | } |
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| 342 | |
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| 343 | int pci_config_read(void) |
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| 344 | { |
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| 345 | pci_system_type = PCI_SYSTEM_HOST; |
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| 346 | |
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| 347 | /* Find all devices and buses */ |
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| 348 | pci_hb.flags = PCI_BUS_IO|PCI_BUS_MEMIO|PCI_BUS_MEM; |
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| 349 | pci_hb.dev.flags = PCI_DEV_BRIDGE; |
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| 350 | pci_read_devs(&pci_hb); |
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| 351 | pci_bus_cnt = pci_hb.sord + 1; |
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| 352 | if (pci_hb.devs == NULL) |
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| 353 | return 0; |
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| 354 | |
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| 355 | return 0; |
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| 356 | } |
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