1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* Read current PCI configuration that bootloader or BIOS has already setup |
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4 | * and initialize the PCI structures. |
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5 | * |
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6 | * COPYRIGHT (c) 2010 Cobham Gaisler AB. |
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7 | * |
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8 | * Redistribution and use in source and binary forms, with or without |
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9 | * modification, are permitted provided that the following conditions |
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10 | * are met: |
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11 | * 1. Redistributions of source code must retain the above copyright |
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12 | * notice, this list of conditions and the following disclaimer. |
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13 | * 2. Redistributions in binary form must reproduce the above copyright |
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14 | * notice, this list of conditions and the following disclaimer in the |
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15 | * documentation and/or other materials provided with the distribution. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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21 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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27 | * POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |
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30 | #include <rtems.h> |
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31 | #include <stdlib.h> |
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32 | #include <rtems/bspIo.h> |
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33 | #include <pci/cfg.h> |
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34 | #include <pci/access.h> |
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35 | |
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36 | #include "pci_internal.h" |
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37 | |
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38 | /* PCI Library |
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39 | * (For debugging it might be good to use other functions or the driver's |
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40 | * directly) |
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41 | */ |
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42 | #define PCI_CFG_R8(dev, args...) pci_cfg_r8(dev, args) |
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43 | #define PCI_CFG_R16(dev, args...) pci_cfg_r16(dev, args) |
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44 | #define PCI_CFG_R32(dev, args...) pci_cfg_r32(dev, args) |
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45 | #define PCI_CFG_W8(dev, args...) pci_cfg_w8(dev, args) |
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46 | #define PCI_CFG_W16(dev, args...) pci_cfg_w16(dev, args) |
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47 | #define PCI_CFG_W32(dev, args...) pci_cfg_w32(dev, args) |
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48 | |
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49 | #ifdef DEBUG |
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50 | #define DBG(args...) printk(args) |
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51 | #else |
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52 | #define DBG(args...) |
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53 | #endif |
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54 | |
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55 | /* The Host Bridge bus is initialized here */ |
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56 | extern struct pci_bus pci_hb; |
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57 | |
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58 | static struct pci_dev *pci_dev_create(int isbus) |
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59 | { |
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60 | void *ptr; |
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61 | int size; |
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62 | |
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63 | if (isbus) |
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64 | size = sizeof(struct pci_bus); |
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65 | else |
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66 | size = sizeof(struct pci_dev); |
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67 | |
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68 | ptr = calloc(1, size); |
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69 | if (!ptr) |
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70 | rtems_fatal_error_occurred(RTEMS_NO_MEMORY); |
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71 | return ptr; |
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72 | } |
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73 | |
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74 | /* Check if address is accessible from host */ |
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75 | static int pci_read_addressable(struct pci_dev *dev, struct pci_res *res) |
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76 | { |
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77 | struct pci_bus *bus = dev->bus; |
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78 | int type = res->flags & PCI_RES_TYPE_MASK; |
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79 | struct pci_res *range0, *range1; |
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80 | |
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81 | if (type == PCI_BUS_IO && (bus->flags & PCI_BUS_IO) == 0) |
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82 | return 0; |
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83 | |
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84 | /* Assume that host bridge can access all */ |
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85 | if (bus->pri == 0) |
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86 | return 1; |
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87 | |
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88 | range1 = NULL; |
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89 | switch (type) { |
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90 | case PCI_RES_IO: |
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91 | range0 = &bus->dev.resources[BRIDGE_RES_IO]; |
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92 | break; |
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93 | case PCI_RES_MEM: |
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94 | range1 = &bus->dev.resources[BRIDGE_RES_MEM]; |
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95 | /* Fall through */ |
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96 | default: |
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97 | case PCI_RES_MEMIO: |
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98 | range0 = &bus->dev.resources[BRIDGE_RES_MEMIO]; |
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99 | break; |
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100 | } |
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101 | if ((res->start >= range0->start) && (res->end <= range0->end)) { |
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102 | return pci_read_addressable(&bus->dev, range0); |
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103 | } else if (range1 && (res->start >= range1->start) && |
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104 | (res->end <= range1->end)) { |
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105 | return pci_read_addressable(&bus->dev, range1); |
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106 | } |
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107 | |
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108 | return 0; |
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109 | } |
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110 | |
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111 | static void pci_read_bar(struct pci_dev *dev, int bar) |
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112 | { |
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113 | uint32_t orig, size, mask; |
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114 | struct pci_res *res = &dev->resources[bar]; |
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115 | pci_dev_t pcidev = dev->busdevfun; |
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116 | int ofs; |
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117 | #ifdef DEBUG |
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118 | char *str; |
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119 | #define DBG_SET_STR(str, val) str = (val) |
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120 | #else |
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121 | #define DBG_SET_STR(str, val) |
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122 | #endif |
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123 | |
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124 | DBG("Bus: %x, Slot: %x, function: %x, bar%d\n", |
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125 | PCI_DEV_EXPAND(pcidev), bar); |
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126 | |
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127 | res->bar = bar; |
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128 | if (bar == DEV_RES_ROM) { |
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129 | if (dev->flags & PCI_DEV_BRIDGE) |
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130 | ofs = PCIR_BIOS_1; |
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131 | else |
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132 | ofs = PCIR_BIOS; |
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133 | } else { |
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134 | ofs = PCIR_BAR(0) + (bar << 2); |
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135 | } |
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136 | |
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137 | PCI_CFG_R32(pcidev, ofs, &orig); |
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138 | PCI_CFG_W32(pcidev, ofs, 0xffffffff); |
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139 | PCI_CFG_R32(pcidev, ofs, &size); |
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140 | PCI_CFG_W32(pcidev, ofs, orig); |
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141 | |
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142 | if (size == 0 || size == 0xffffffff) |
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143 | return; |
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144 | if (bar == DEV_RES_ROM) { |
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145 | mask = PCIM_BIOS_ADDR_MASK; |
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146 | DBG_SET_STR(str, "ROM"); |
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147 | if (dev->bus->flags & PCI_BUS_MEM) |
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148 | res->flags = PCI_RES_MEM; |
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149 | else |
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150 | res->flags = PCI_RES_MEMIO; |
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151 | } else if (((size & 0x1) == 0) && (size & 0x6)) { |
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152 | /* unsupported Memory type */ |
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153 | return; |
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154 | } else { |
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155 | mask = ~0xf; |
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156 | if (size & 0x1) { |
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157 | /* I/O */ |
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158 | mask = ~0x3; |
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159 | res->flags = PCI_RES_IO; |
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160 | DBG_SET_STR(str, "I/O"); |
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161 | if (size & 0xffff0000) |
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162 | res->flags |= PCI_RES_IO32; |
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163 | /* Limit size of I/O space to 256 byte */ |
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164 | size |= 0xffffff00; |
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165 | if ((dev->bus->flags & PCI_BUS_IO) == 0) { |
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166 | res->flags |= PCI_RES_FAIL; |
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167 | dev->flags |= PCI_DEV_RES_FAIL; |
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168 | } |
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169 | } else { |
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170 | /* Memory */ |
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171 | if (size & 0x8) { |
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172 | /* Prefetchable */ |
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173 | res->flags = PCI_RES_MEM; |
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174 | DBG_SET_STR(str, "MEM"); |
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175 | } else { |
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176 | res->flags = PCI_RES_MEMIO; |
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177 | DBG_SET_STR(str, "MEMIO"); |
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178 | } |
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179 | } |
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180 | } |
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181 | res->start = orig & mask; |
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182 | size &= mask; |
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183 | res->size = ~size + 1; |
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184 | res->boundary = res->size; |
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185 | res->end = res->start + res->size; |
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186 | |
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187 | DBG("Bus: %x, Slot: %x, function: %x, %s bar%d size: %x\n", |
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188 | PCI_DEV_EXPAND(pcidev), str, bar, res->size); |
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189 | |
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190 | /* Check if BAR is addressable by host */ |
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191 | if (pci_read_addressable(dev, res) == 0) { |
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192 | /* No matching bridge window contains this BAR */ |
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193 | res->flags |= PCI_RES_FAIL; |
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194 | dev->flags |= PCI_DEV_RES_FAIL; |
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195 | } |
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196 | } |
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197 | |
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198 | static void pci_read_devs(struct pci_bus *bus) |
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199 | { |
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200 | uint32_t id, tmp; |
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201 | uint16_t tmp16; |
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202 | uint8_t header; |
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203 | int slot, func, fail, i, maxbars, max_sord; |
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204 | struct pci_dev *dev, **listptr; |
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205 | struct pci_bus *bridge; |
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206 | pci_dev_t pcidev; |
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207 | struct pci_res *res; |
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208 | |
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209 | DBG("Scanning bus %d\n", bus->num); |
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210 | |
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211 | max_sord = bus->num; |
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212 | listptr = &bus->devs; |
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213 | for (slot = 0; slot <= PCI_SLOTMAX; slot++) { |
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214 | |
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215 | /* Slot address */ |
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216 | pcidev = PCI_DEV(bus->num, slot, 0); |
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217 | |
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218 | for (func = 0; func <= PCI_FUNCMAX; func++, pcidev++) { |
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219 | |
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220 | fail = PCI_CFG_R32(pcidev, PCIR_VENDOR, &id); |
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221 | if (fail || id == 0xffffffff || id == 0) { |
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222 | /* |
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223 | * This slot is empty |
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224 | */ |
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225 | if (func == 0) |
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226 | break; |
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227 | else |
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228 | continue; |
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229 | } |
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230 | |
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231 | DBG("Found PCIDEV 0x%x at (bus %x, slot %x, func %x)\n", |
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232 | id, bus, slot, func); |
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233 | |
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234 | PCI_CFG_R32(pcidev, PCIR_REVID, &tmp); |
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235 | tmp >>= 16; |
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236 | dev = pci_dev_create(tmp == PCID_PCI2PCI_BRIDGE); |
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237 | *listptr = dev; |
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238 | listptr = &dev->next; |
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239 | |
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240 | dev->busdevfun = pcidev; |
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241 | dev->bus = bus; |
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242 | PCI_CFG_R16(pcidev, PCIR_VENDOR, &dev->vendor); |
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243 | PCI_CFG_R16(pcidev, PCIR_DEVICE, &dev->device); |
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244 | PCI_CFG_R32(pcidev, PCIR_REVID, &dev->classrev); |
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245 | |
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246 | if (tmp == PCID_PCI2PCI_BRIDGE) { |
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247 | DBG("Found PCI-PCI Bridge 0x%x at " |
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248 | "(bus %x, slot %x, func %x)\n", |
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249 | id, bus, slot, func); |
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250 | dev->flags = PCI_DEV_BRIDGE; |
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251 | bridge = (struct pci_bus *)dev; |
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252 | |
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253 | PCI_CFG_R32(pcidev, PCIR_PRIBUS_1, &tmp); |
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254 | bridge->pri = tmp & 0xff; |
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255 | bridge->num = (tmp >> 8) & 0xff; |
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256 | bridge->sord = (tmp >> 16) & 0xff; |
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257 | if (bridge->sord > max_sord) |
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258 | max_sord = bridge->sord; |
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259 | |
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260 | DBG(" Primary %x, Secondary %x, " |
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261 | "Subordinate %x\n", |
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262 | bridge->pri, bridge->num, bridge->sord); |
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263 | |
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264 | /*** Probe Bridge Spaces ***/ |
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265 | |
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266 | /* MEMIO Window - always implemented */ |
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267 | bridge->flags = PCI_BUS_MEMIO; |
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268 | res = &bridge->dev.resources[BRIDGE_RES_MEMIO]; |
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269 | res->flags = PCI_RES_MEMIO; |
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270 | res->bar = BRIDGE_RES_MEMIO; |
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271 | PCI_CFG_R32(pcidev, 0x20, &tmp); |
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272 | res->start = (tmp & 0xfff0) << 16; |
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273 | res->end = 1 + ((tmp & 0xfff00000) | 0xfffff); |
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274 | if (res->end <= res->start) { |
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275 | /* Window disabled */ |
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276 | res->end = res->start = 0; |
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277 | } |
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278 | res->size = res->end - res->start; |
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279 | |
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280 | /* I/O Window - optional */ |
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281 | res = &bridge->dev.resources[BRIDGE_RES_IO]; |
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282 | res->bar = BRIDGE_RES_IO; |
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283 | PCI_CFG_R32(pcidev, 0x30, &tmp); |
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284 | PCI_CFG_R16(pcidev, 0x1c, &tmp16); |
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285 | if (tmp != 0 || tmp16 != 0) { |
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286 | bridge->flags |= PCI_BUS_IO; |
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287 | res->flags = PCI_RES_IO; |
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288 | if (tmp16 & 0x1) { |
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289 | bridge->flags |= PCI_BUS_IO32; |
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290 | res->flags |= PCI_RES_IO32; |
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291 | } |
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292 | |
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293 | res->start = (tmp & 0xffff) << 16 | |
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294 | (tmp16 & 0xf0) << 8; |
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295 | res->end = 1 + ((tmp & 0xffff0000) | |
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296 | (tmp16 & 0xf000) | |
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297 | 0xfff); |
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298 | if (res->end <= res->start) { |
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299 | /* Window disabled */ |
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300 | res->end = res->start = 0; |
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301 | } |
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302 | res->size = res->end - res->start; |
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303 | } |
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304 | |
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305 | /* MEM Window - optional */ |
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306 | res = &bridge->dev.resources[BRIDGE_RES_MEM]; |
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307 | res->bar = BRIDGE_RES_MEM; |
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308 | PCI_CFG_R32(pcidev, 0x24, &tmp); |
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309 | if (tmp != 0) { |
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310 | bridge->flags |= PCI_BUS_MEM; |
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311 | res->flags = PCI_RES_MEM; |
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312 | res->start = (tmp & 0xfff0) << 16; |
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313 | res->end = 1 + ((tmp & 0xfff00000) | |
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314 | 0xfffff); |
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315 | if (res->end <= res->start) { |
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316 | /* Window disabled */ |
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317 | res->end = res->start = 0; |
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318 | } |
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319 | res->size = res->end - res->start; |
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320 | } |
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321 | |
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322 | /* Scan Secondary Bus */ |
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323 | pci_read_devs(bridge); |
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324 | |
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325 | /* Only 2 BARs for Bridges */ |
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326 | maxbars = 2; |
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327 | } else { |
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328 | /* Devices have subsytem device and vendor ID */ |
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329 | PCI_CFG_R16(pcidev, PCIR_SUBVEND_0, |
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330 | &dev->subvendor); |
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331 | PCI_CFG_R16(pcidev, PCIR_SUBDEV_0, |
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332 | &dev->subdevice); |
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333 | |
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334 | /* Normal PCI Device has max 6 BARs */ |
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335 | maxbars = 6; |
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336 | } |
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337 | |
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338 | /* Probe BARs */ |
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339 | for (i = 0; i < maxbars; i++) |
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340 | pci_read_bar(dev, i); |
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341 | pci_read_bar(dev, DEV_RES_ROM); |
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342 | |
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343 | /* Get System Interrupt/Vector for device. |
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344 | * 0 means no-IRQ |
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345 | */ |
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346 | PCI_CFG_R8(pcidev, PCIR_INTLINE, &dev->sysirq); |
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347 | |
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348 | /* Stop if not a multi-function device */ |
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349 | if (func == 0) { |
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350 | pci_cfg_r8(pcidev, PCIR_HDRTYPE, &header); |
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351 | if ((header & PCIM_MFDEV) == 0) |
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352 | break; |
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353 | } |
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354 | } |
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355 | } |
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356 | |
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357 | if (bus->num == 0) |
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358 | bus->sord = max_sord; |
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359 | } |
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360 | |
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361 | int pci_config_read(void) |
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362 | { |
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363 | pci_system_type = PCI_SYSTEM_HOST; |
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364 | |
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365 | /* Find all devices and buses */ |
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366 | pci_hb.flags = PCI_BUS_IO|PCI_BUS_MEMIO|PCI_BUS_MEM; |
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367 | pci_hb.dev.flags = PCI_DEV_BRIDGE; |
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368 | pci_read_devs(&pci_hb); |
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369 | pci_bus_cnt = pci_hb.sord + 1; |
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370 | if (pci_hb.devs == NULL) |
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371 | return 0; |
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372 | |
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373 | return 0; |
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374 | } |
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