source: rtems/cpukit/libpci/pci_bus.h @ 61788e76

Last change on this file since 61788e76 was 61788e76, checked in by Javier Jalle <javier.jalle@…>, on Jan 31, 2017 at 9:13:41 AM

leon, GR-CPCI-GR740: Added peripheral PCI driver

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File size: 5.6 KB
Line 
1/*  PCI bus driver Interface.
2 *
3 *  COPYRIGHT (c) 2008 Cobham Gaisler AB.
4 *
5 *  The license and distribution terms for this file may be
6 *  found in the file LICENSE in this distribution or at
7 *  http://www.rtems.org/license/LICENSE.
8 *
9 */
10
11/* General part of drvmgr PCI Bus driver. The driver is typically
12 * initialized from the PCI host driver separating the host
13 * driver from the common parts in PCI drivers.
14 * The PCI library must be initialized before starting the
15 * PCI bus driver. The PCI library have set up BARs and
16 * assigned system IRQs for targets.
17 * This PCI bus driver rely on the PCI library (pci.c) for
18 * interrupt registeration (pci_interrupt_register) and PCI
19 * target set up.
20 */
21
22#ifndef __PCI_BUS_H__
23#define __PCI_BUS_H__
24
25#include <drvmgr/drvmgr.h>
26#include <pci.h>
27#include <pci/access.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */
34#define DRIVER_PCI_ID(vendor, device) \
35        DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \
36                ((((vendor) & 0xffff) << 16) | ((device) & 0xffff)))
37
38/* PCI Driver ID generation (CLASS: 24-bit) */
39#define DRIVER_PCI_CLASS(class) \
40        DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff)))
41
42/* PCI driver IDs  (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */
43#define DRIVER_PCI_GAISLER_RASTAIO_ID           DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO)
44#define DRIVER_PCI_GAISLER_RASTATMTC_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC)
45#define DRIVER_PCI_GAISLER_GR701_ID             DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701)
46#define DRIVER_PCI_GAISLER_RASTAADCDAC_ID       DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC)
47#define DRIVER_PCI_GAISLER_TMTC_1553_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553)
48#define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID  DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR)
49#define DRIVER_PCI_GAISLER_LEON4_N2X_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X)
50#define DRIVER_PCI_GAISLER_CPCI_GR740_ID        DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_CPCI_GR740)
51
52struct pci_dev_id {
53        uint16_t                vendor;
54        uint16_t                device;
55        uint16_t                subvendor;
56        uint16_t                subdevice;
57        uint32_t                class; /* 24 lower bits */
58};
59
60struct pci_dev_id_match {
61        uint16_t                vendor;
62        uint16_t                device;
63        uint16_t                subvendor;
64        uint16_t                subdevice;
65        uint32_t                class;  /* 24 lower bits */
66        uint32_t                class_mask; /* 24 lower bits */
67};
68#define PCIID_DEVVEND(vendor, device) \
69        {vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0}
70#define PCIID_END_TABLE {0, 0, 0, 0, 0, 0}
71
72enum {
73        /* A Device has up to 6 BARs and an optional ROM BAR */
74        PCIDEV_RES_BAR1 = 0,
75        PCIDEV_RES_BAR2 = 1,
76        PCIDEV_RES_BAR3 = 2,
77        PCIDEV_RES_BAR4 = 3,
78        PCIDEV_RES_BAR5 = 4,
79        PCIDEV_RES_BAR6 = 5,
80        PCIDEV_RES_ROM  = 6,
81};
82/* Maximum Number of Resources of a device */
83#define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1)
84
85/* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */
86struct pcibus_res {
87        uint32_t                address; /* Base Address, CPU accessible */
88        uint32_t                size;    /* 0=Unimplemented, 0!=Resource Size */
89        struct pci_res          *res;    /* PCI-layer resource */
90};
91
92struct pci_dev_info {
93        struct pci_dev_id       id;
94        uint8_t                 rev;
95        uint8_t                 irq; /* 0 = NO IRQ */
96        pci_dev_t               pcidev;
97        struct pcibus_res       resources[PCIDEV_RES_CNT];
98        struct pci_dev          *pci_device;
99};
100
101struct pci_drv_info {
102        struct drvmgr_drv       general;        /* General bus info */
103        /* PCI specific bus information */
104        struct pci_dev_id_match         *ids;           /* Supported hardware */
105};
106
107/* Access routines */
108struct pcibus_regmem_ops {
109        drvmgr_r8 r8;
110        drvmgr_r16 r16;
111        drvmgr_r32 r32;
112        drvmgr_r64 r64;
113        drvmgr_w8 w8;
114        drvmgr_w16 w16;
115        drvmgr_w32 w32;
116        drvmgr_w64 w64;
117};
118
119/* Let driver configure PCI bus driver */
120struct pcibus_config {
121        struct drvmgr_map_entry         *maps_up;
122        struct drvmgr_map_entry         *maps_down;
123};
124
125/* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */
126#define PCI_FUNC_CFG_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG)
127#define PCI_FUNC_CFG_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG)
128#define PCI_FUNC_CFG_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG)
129#define PCI_FUNC_CFG_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG)
130#define PCI_FUNC_CFG_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG)
131#define PCI_FUNC_CFG_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG)
132
133/* PCI I/O Register Access - Not implemented (use PCI Lib directly) */
134#define PCI_FUNC_IO_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO)
135#define PCI_FUNC_IO_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO)
136#define PCI_FUNC_IO_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO)
137#define PCI_FUNC_IO_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO)
138#define PCI_FUNC_IO_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO)
139#define PCI_FUNC_IO_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO)
140
141/* PCI Register Access over Memory Space (Little Endian) */
142#define PCI_FUNC_MREG_R8   DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG)
143#define PCI_FUNC_MREG_R16  DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE)
144#define PCI_FUNC_MREG_R32  DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE)
145#define PCI_FUNC_MREG_W8   DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG)
146#define PCI_FUNC_MREG_W16  DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE)
147#define PCI_FUNC_MREG_W32  DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE)
148
149/* Weak default PCI driver resources, override this from project configuration
150 * to set PCI Bus resources used to configure PCI device drivers.
151 */
152extern struct drvmgr_bus_res pcibus_drv_resources;
153
154/* Attach a PCI bus on top of a PCI Host device */
155extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg);
156
157#ifdef __cplusplus
158}
159#endif
160
161#endif
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