source: rtems/cpukit/libpci/pci_bus.h @ 1f66914

4.11
Last change on this file since 1f66914 was 1f66914, checked in by Daniel Hellstrom <daniel@…>, on Apr 13, 2015 at 8:12:08 AM

LIBPCI: moved pci_bus copyright into a single line

  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*  PCI bus driver Interface.
2 *
3 *  COPYRIGHT (c) 2008 Cobham Gaisler AB.
4 *
5 *  General part of PCI Bus driver. The driver is typically
6 *  initialized from the PCI host driver separating the host
7 *  driver from the common parts in PCI drivers.
8 *  The PCI library must be initialized before starting the
9 *  PCI bus driver. The PCI library have set up BARs and
10 *  assigned system IRQs for targets.
11 *  This PCI bus driver rely on the PCI library (pci.c) for
12 *  interrupt registeration (pci_interrupt_register) and PCI
13 *  target set up.
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.com/license/LICENSE.
18 *
19 */
20
21#ifndef __PCI_BUS_H__
22#define __PCI_BUS_H__
23
24#include <drvmgr/drvmgr.h>
25#include <pci.h>
26#include <pci/access.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */
33#define DRIVER_PCI_ID(vendor, device) \
34        DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \
35                ((((vendor) & 0xffff) << 16) | ((device) & 0xffff)))
36
37/* PCI Driver ID generation (CLASS: 24-bit) */
38#define DRIVER_PCI_CLASS(class) \
39        DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff)))
40
41/* PCI driver IDs  (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */
42#define DRIVER_PCI_GAISLER_RASTAIO_ID           DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO)
43#define DRIVER_PCI_GAISLER_RASTATMTC_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC)
44#define DRIVER_PCI_GAISLER_GR701_ID             DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701)
45#define DRIVER_PCI_GAISLER_RASTAADCDAC_ID       DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC)
46#define DRIVER_PCI_GAISLER_TMTC_1553_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553)
47#define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID  DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR)
48#define DRIVER_PCI_GAISLER_LEON4_N2X_ID         DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X)
49
50struct pci_dev_id {
51        uint16_t                vendor;
52        uint16_t                device;
53        uint16_t                subvendor;
54        uint16_t                subdevice;
55        uint32_t                class; /* 24 lower bits */
56};
57
58struct pci_dev_id_match {
59        uint16_t                vendor;
60        uint16_t                device;
61        uint16_t                subvendor;
62        uint16_t                subdevice;
63        uint32_t                class;  /* 24 lower bits */
64        uint32_t                class_mask; /* 24 lower bits */
65};
66#define PCIID_DEVVEND(vendor, device) \
67        {vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0}
68#define PCIID_END_TABLE {0, 0, 0, 0, 0, 0}
69
70enum {
71        /* A Device has up to 6 BARs and an optional ROM BAR */
72        PCIDEV_RES_BAR1 = 0,
73        PCIDEV_RES_BAR2 = 1,
74        PCIDEV_RES_BAR3 = 2,
75        PCIDEV_RES_BAR4 = 3,
76        PCIDEV_RES_BAR5 = 4,
77        PCIDEV_RES_BAR6 = 5,
78        PCIDEV_RES_ROM  = 6,
79};
80/* Maximum Number of Resources of a device */
81#define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1)
82
83/* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */
84struct pcibus_res {
85        uint32_t                address; /* Base Address, CPU accessible */
86        uint32_t                size;    /* 0=Unimplemented, 0!=Resource Size */
87        struct pci_res          *res;    /* PCI-layer resource */
88};
89
90struct pci_dev_info {
91        struct pci_dev_id       id;
92        uint8_t                 rev;
93        uint8_t                 irq; /* 0 = NO IRQ */
94        pci_dev_t               pcidev;
95        struct pcibus_res       resources[PCIDEV_RES_CNT];
96        struct pci_dev          *pci_device;
97};
98
99struct pci_drv_info {
100        struct drvmgr_drv       general;        /* General bus info */
101        /* PCI specific bus information */
102        struct pci_dev_id_match         *ids;           /* Supported hardware */
103};
104
105/* Access routines */
106struct pcibus_regmem_ops {
107        drvmgr_r8 r8;
108        drvmgr_r16 r16;
109        drvmgr_r32 r32;
110        drvmgr_r64 r64;
111        drvmgr_w8 w8;
112        drvmgr_w16 w16;
113        drvmgr_w32 w32;
114        drvmgr_w64 w64;
115};
116
117/* Let driver configure PCI bus driver */
118struct pcibus_config {
119        struct drvmgr_map_entry         *maps_up;
120        struct drvmgr_map_entry         *maps_down;
121};
122
123/* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */
124#define PCI_FUNC_CFG_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG)
125#define PCI_FUNC_CFG_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG)
126#define PCI_FUNC_CFG_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG)
127#define PCI_FUNC_CFG_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG)
128#define PCI_FUNC_CFG_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG)
129#define PCI_FUNC_CFG_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG)
130
131/* PCI I/O Register Access - Not implemented (use PCI Lib directly) */
132#define PCI_FUNC_IO_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO)
133#define PCI_FUNC_IO_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO)
134#define PCI_FUNC_IO_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO)
135#define PCI_FUNC_IO_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO)
136#define PCI_FUNC_IO_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO)
137#define PCI_FUNC_IO_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO)
138
139/* PCI Register Access over Memory Space (Little Endian) */
140#define PCI_FUNC_MREG_R8   DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG)
141#define PCI_FUNC_MREG_R16  DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE)
142#define PCI_FUNC_MREG_R32  DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE)
143#define PCI_FUNC_MREG_W8   DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG)
144#define PCI_FUNC_MREG_W16  DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE)
145#define PCI_FUNC_MREG_W32  DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE)
146
147/* Weak default PCI driver resources, override this from project configuration
148 * to set PCI Bus resources used to configure PCI device drivers.
149 */
150extern struct drvmgr_bus_res pcibus_drv_resources;
151
152/* Attach a PCI bus on top of a PCI Host device */
153extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg);
154
155#ifdef __cplusplus
156}
157#endif
158
159#endif
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