[1c5a7e5] | 1 | /* PCI bus driver Interface. |
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| 2 | * |
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[1f66914] | 3 | * COPYRIGHT (c) 2008 Cobham Gaisler AB. |
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[1c5a7e5] | 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in the file LICENSE in this distribution or at |
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[e53daed] | 7 | * http://www.rtems.org/license/LICENSE. |
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[1c5a7e5] | 8 | * |
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| 9 | */ |
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| 10 | |
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[e189f241] | 11 | /* General part of drvmgr PCI Bus driver. The driver is typically |
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| 12 | * initialized from the PCI host driver separating the host |
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| 13 | * driver from the common parts in PCI drivers. |
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| 14 | * The PCI library must be initialized before starting the |
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| 15 | * PCI bus driver. The PCI library have set up BARs and |
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| 16 | * assigned system IRQs for targets. |
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| 17 | * This PCI bus driver rely on the PCI library (pci.c) for |
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| 18 | * interrupt registeration (pci_interrupt_register) and PCI |
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| 19 | * target set up. |
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| 20 | */ |
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| 21 | |
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[1c5a7e5] | 22 | #ifndef __PCI_BUS_H__ |
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| 23 | #define __PCI_BUS_H__ |
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| 24 | |
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| 25 | #include <drvmgr/drvmgr.h> |
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| 26 | #include <pci.h> |
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| 27 | #include <pci/access.h> |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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| 33 | /* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */ |
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| 34 | #define DRIVER_PCI_ID(vendor, device) \ |
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| 35 | DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \ |
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| 36 | ((((vendor) & 0xffff) << 16) | ((device) & 0xffff))) |
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| 37 | |
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| 38 | /* PCI Driver ID generation (CLASS: 24-bit) */ |
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| 39 | #define DRIVER_PCI_CLASS(class) \ |
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| 40 | DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff))) |
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| 41 | |
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| 42 | /* PCI driver IDs (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */ |
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| 43 | #define DRIVER_PCI_GAISLER_RASTAIO_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO) |
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| 44 | #define DRIVER_PCI_GAISLER_RASTATMTC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC) |
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| 45 | #define DRIVER_PCI_GAISLER_GR701_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701) |
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| 46 | #define DRIVER_PCI_GAISLER_RASTAADCDAC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC) |
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| 47 | #define DRIVER_PCI_GAISLER_TMTC_1553_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553) |
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| 48 | #define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR) |
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[ffd8002d] | 49 | #define DRIVER_PCI_GAISLER_LEON4_N2X_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X) |
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[1c5a7e5] | 50 | |
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| 51 | struct pci_dev_id { |
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| 52 | uint16_t vendor; |
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| 53 | uint16_t device; |
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| 54 | uint16_t subvendor; |
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| 55 | uint16_t subdevice; |
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| 56 | uint32_t class; /* 24 lower bits */ |
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| 57 | }; |
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| 58 | |
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| 59 | struct pci_dev_id_match { |
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| 60 | uint16_t vendor; |
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| 61 | uint16_t device; |
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| 62 | uint16_t subvendor; |
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| 63 | uint16_t subdevice; |
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| 64 | uint32_t class; /* 24 lower bits */ |
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| 65 | uint32_t class_mask; /* 24 lower bits */ |
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| 66 | }; |
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| 67 | #define PCIID_DEVVEND(vendor, device) \ |
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| 68 | {vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0} |
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| 69 | #define PCIID_END_TABLE {0, 0, 0, 0, 0, 0} |
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| 70 | |
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| 71 | enum { |
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| 72 | /* A Device has up to 6 BARs and an optional ROM BAR */ |
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| 73 | PCIDEV_RES_BAR1 = 0, |
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| 74 | PCIDEV_RES_BAR2 = 1, |
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| 75 | PCIDEV_RES_BAR3 = 2, |
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| 76 | PCIDEV_RES_BAR4 = 3, |
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| 77 | PCIDEV_RES_BAR5 = 4, |
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| 78 | PCIDEV_RES_BAR6 = 5, |
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| 79 | PCIDEV_RES_ROM = 6, |
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| 80 | }; |
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| 81 | /* Maximum Number of Resources of a device */ |
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| 82 | #define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1) |
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| 83 | |
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| 84 | /* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */ |
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| 85 | struct pcibus_res { |
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| 86 | uint32_t address; /* Base Address, CPU accessible */ |
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| 87 | uint32_t size; /* 0=Unimplemented, 0!=Resource Size */ |
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| 88 | struct pci_res *res; /* PCI-layer resource */ |
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| 89 | }; |
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| 90 | |
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| 91 | struct pci_dev_info { |
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| 92 | struct pci_dev_id id; |
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| 93 | uint8_t rev; |
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| 94 | uint8_t irq; /* 0 = NO IRQ */ |
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| 95 | pci_dev_t pcidev; |
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| 96 | struct pcibus_res resources[PCIDEV_RES_CNT]; |
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| 97 | struct pci_dev *pci_device; |
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| 98 | }; |
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| 99 | |
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| 100 | struct pci_drv_info { |
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| 101 | struct drvmgr_drv general; /* General bus info */ |
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| 102 | /* PCI specific bus information */ |
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| 103 | struct pci_dev_id_match *ids; /* Supported hardware */ |
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| 104 | }; |
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| 105 | |
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| 106 | /* Access routines */ |
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| 107 | struct pcibus_regmem_ops { |
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| 108 | drvmgr_r8 r8; |
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| 109 | drvmgr_r16 r16; |
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| 110 | drvmgr_r32 r32; |
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| 111 | drvmgr_r64 r64; |
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| 112 | drvmgr_w8 w8; |
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| 113 | drvmgr_w16 w16; |
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| 114 | drvmgr_w32 w32; |
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| 115 | drvmgr_w64 w64; |
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| 116 | }; |
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| 117 | |
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| 118 | /* Let driver configure PCI bus driver */ |
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| 119 | struct pcibus_config { |
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| 120 | struct drvmgr_map_entry *maps_up; |
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| 121 | struct drvmgr_map_entry *maps_down; |
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| 122 | }; |
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| 123 | |
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| 124 | /* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */ |
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| 125 | #define PCI_FUNC_CFG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG) |
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| 126 | #define PCI_FUNC_CFG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG) |
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| 127 | #define PCI_FUNC_CFG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG) |
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| 128 | #define PCI_FUNC_CFG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG) |
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| 129 | #define PCI_FUNC_CFG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG) |
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| 130 | #define PCI_FUNC_CFG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG) |
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| 131 | |
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| 132 | /* PCI I/O Register Access - Not implemented (use PCI Lib directly) */ |
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| 133 | #define PCI_FUNC_IO_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO) |
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| 134 | #define PCI_FUNC_IO_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO) |
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| 135 | #define PCI_FUNC_IO_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO) |
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| 136 | #define PCI_FUNC_IO_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO) |
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| 137 | #define PCI_FUNC_IO_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO) |
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| 138 | #define PCI_FUNC_IO_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO) |
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| 139 | |
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| 140 | /* PCI Register Access over Memory Space (Little Endian) */ |
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| 141 | #define PCI_FUNC_MREG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG) |
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| 142 | #define PCI_FUNC_MREG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE) |
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| 143 | #define PCI_FUNC_MREG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE) |
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| 144 | #define PCI_FUNC_MREG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG) |
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| 145 | #define PCI_FUNC_MREG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE) |
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| 146 | #define PCI_FUNC_MREG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE) |
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| 147 | |
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| 148 | /* Weak default PCI driver resources, override this from project configuration |
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| 149 | * to set PCI Bus resources used to configure PCI device drivers. |
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| 150 | */ |
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| 151 | extern struct drvmgr_bus_res pcibus_drv_resources; |
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| 152 | |
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| 153 | /* Attach a PCI bus on top of a PCI Host device */ |
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| 154 | extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg); |
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| 155 | |
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| 156 | #ifdef __cplusplus |
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| 157 | } |
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| 158 | #endif |
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| 159 | |
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| 160 | #endif |
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