[1c5a7e5] | 1 | /* PCI bus driver. |
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| 2 | * |
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[1f66914] | 3 | * COPYRIGHT (c) 2008 Cobham Gaisler AB. |
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[1c5a7e5] | 4 | * |
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| 5 | * General part of PCI Bus driver. The driver is typically |
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| 6 | * initialized from the PCI host driver separating the host |
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| 7 | * driver from the common parts in PCI drivers. |
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| 8 | * The PCI library must be initialized before starting the |
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| 9 | * PCI bus driver. The PCI library have set up BARs and |
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| 10 | * assigned system IRQs for targets. |
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| 11 | * This PCI bus driver rely on the PCI library (pci.c) for |
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| 12 | * interrupt registeration (pci_interrupt_register) and PCI |
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| 13 | * target set up. |
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| 14 | * |
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| 15 | * The license and distribution terms for this file may be |
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| 16 | * found in the file LICENSE in this distribution or at |
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| 17 | * http://www.rtems.com/license/LICENSE. |
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| 18 | * |
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| 19 | * 2008-12-03, Daniel Hellstrom <daniel@gaisler.com> |
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| 20 | * Created |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | /* Use PCI Configuration libarary pci_hb RAM device structure to find devices, |
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| 25 | * undefine to access PCI configuration space directly. |
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| 26 | */ |
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| 27 | #define USE_PCI_CFG_LIB |
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| 28 | |
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| 29 | /* On small systems undefine PCIBUS_INFO to avoid sprintf get dragged in */ |
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| 30 | #define PCIBUS_INFO |
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| 31 | |
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| 32 | #include <stdlib.h> |
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| 33 | #include <stdio.h> |
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| 34 | #include <string.h> |
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| 35 | |
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| 36 | #include <pci.h> |
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| 37 | #ifdef USE_PCI_CFG_LIB |
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| 38 | #include <pci/cfg.h> |
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| 39 | #endif |
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| 40 | #include <pci/irq.h> |
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| 41 | |
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| 42 | #include <drvmgr/drvmgr.h> |
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| 43 | #include <drvmgr/pci_bus.h> |
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| 44 | |
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| 45 | #ifdef DEBUG |
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| 46 | #define DBG(args...) printk(args) |
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| 47 | #else |
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| 48 | #define DBG(args...) |
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| 49 | #endif |
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| 50 | |
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| 51 | int pcibus_bus_init1(struct drvmgr_bus *bus); |
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| 52 | int pcibus_unite(struct drvmgr_drv *drv, struct drvmgr_dev *dev); |
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| 53 | int pcibus_int_register( |
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| 54 | struct drvmgr_dev *dev, |
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| 55 | int index, |
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| 56 | const char *info, |
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| 57 | drvmgr_isr isr, |
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| 58 | void *arg); |
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| 59 | int pcibus_int_unregister( |
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| 60 | struct drvmgr_dev *dev, |
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| 61 | int index, |
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| 62 | drvmgr_isr isr, |
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| 63 | void *arg); |
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| 64 | int pcibus_int_clear( |
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| 65 | struct drvmgr_dev *dev, |
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| 66 | int index); |
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| 67 | int pcibus_freq_get( |
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| 68 | struct drvmgr_dev *dev, |
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| 69 | int options, |
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| 70 | unsigned int *freq_hz); |
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| 71 | |
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| 72 | int pcibus_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params); |
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| 73 | |
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| 74 | void pcibus_dev_info( |
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| 75 | struct drvmgr_dev *dev, |
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| 76 | void (*print_line)(void *p, char *str), |
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| 77 | void *p); |
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| 78 | |
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| 79 | struct drvmgr_bus_ops pcibus_ops = { |
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| 80 | .init = { |
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| 81 | pcibus_bus_init1, |
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| 82 | NULL, |
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| 83 | NULL, |
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| 84 | NULL |
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| 85 | }, |
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| 86 | .remove = NULL, |
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| 87 | .unite = pcibus_unite, |
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| 88 | .int_register = pcibus_int_register, |
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| 89 | .int_unregister = pcibus_int_unregister, |
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| 90 | #if 0 |
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| 91 | .int_enable = pcibus_int_enable, |
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| 92 | .int_disable = pcibus_int_disable, |
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| 93 | #endif |
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| 94 | .int_clear = pcibus_int_clear, |
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| 95 | .int_mask = NULL, |
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| 96 | .int_unmask = NULL, |
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| 97 | .get_params = pcibus_get_params, |
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| 98 | .freq_get = pcibus_freq_get, |
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| 99 | #ifdef PCIBUS_INFO |
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| 100 | .info_dev = pcibus_dev_info, |
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| 101 | #endif |
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| 102 | }; |
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| 103 | |
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| 104 | struct drvmgr_func pcibus_funcs[] = { |
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| 105 | DRVMGR_FUNC(PCI_FUNC_MREG_R8, NULL), |
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| 106 | DRVMGR_FUNC(PCI_FUNC_MREG_R16, NULL), |
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| 107 | DRVMGR_FUNC(PCI_FUNC_MREG_R32, NULL), |
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| 108 | DRVMGR_FUNC(PCI_FUNC_MREG_W8, NULL), |
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| 109 | DRVMGR_FUNC(PCI_FUNC_MREG_W16, NULL), |
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| 110 | DRVMGR_FUNC(PCI_FUNC_MREG_W32, NULL), |
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| 111 | DRVMGR_FUNC_END |
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| 112 | }; |
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| 113 | |
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| 114 | /* Driver resources configuration for the PCI bus. It is declared weak so that |
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| 115 | * the user may override it from the project file, if the default settings are |
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| 116 | * not enough. |
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| 117 | */ |
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| 118 | struct drvmgr_bus_res pcibus_drv_resources __attribute__((weak)) = { |
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| 119 | .next = NULL, |
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| 120 | .resource = { |
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| 121 | RES_EMPTY, |
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| 122 | }, |
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| 123 | }; |
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| 124 | |
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| 125 | struct pcibus_priv { |
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| 126 | struct drvmgr_dev *dev; |
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| 127 | }; |
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| 128 | |
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| 129 | static int compatible(struct pci_dev_id *id, struct pci_dev_id_match *drv) |
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| 130 | { |
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| 131 | if (((drv->vendor==PCI_ID_ANY) || (id->vendor==drv->vendor)) && |
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| 132 | ((drv->device==PCI_ID_ANY) || (id->device==drv->device)) && |
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| 133 | ((drv->subvendor==PCI_ID_ANY) || (id->subvendor==drv->subvendor)) && |
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| 134 | ((drv->subdevice==PCI_ID_ANY) || (id->subdevice==drv->subdevice)) && |
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| 135 | ((id->class & drv->class_mask) == drv->class)) |
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| 136 | return 1; |
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| 137 | else |
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| 138 | return 0; |
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| 139 | } |
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| 140 | |
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| 141 | int pcibus_unite(struct drvmgr_drv *drv, |
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| 142 | struct drvmgr_dev *dev) |
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| 143 | { |
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| 144 | struct pci_drv_info *pdrv; |
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| 145 | struct pci_dev_id_match *drvid; |
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| 146 | struct pci_dev_info *pci; |
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| 147 | |
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| 148 | if (!drv || !dev || !dev->parent) |
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| 149 | return 0; |
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| 150 | |
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| 151 | if ((drv->bus_type != DRVMGR_BUS_TYPE_PCI) || |
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| 152 | (dev->parent->bus_type != DRVMGR_BUS_TYPE_PCI)) |
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| 153 | return 0; |
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| 154 | |
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| 155 | pci = (struct pci_dev_info *)dev->businfo; |
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| 156 | if (!pci) |
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| 157 | return 0; |
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| 158 | |
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| 159 | pdrv = (struct pci_drv_info *)drv; |
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| 160 | drvid = pdrv->ids; |
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| 161 | if (!drvid) |
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| 162 | return 0; |
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| 163 | while (drvid->vendor != 0) { |
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| 164 | if (compatible(&pci->id, drvid)) { |
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| 165 | /* Unite device and driver */ |
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| 166 | DBG("DRV %p and DEV %p united\n", drv, dev); |
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| 167 | return 1; |
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| 168 | } |
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| 169 | drvid++; |
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| 170 | } |
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| 171 | |
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| 172 | return 0; |
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| 173 | } |
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| 174 | |
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| 175 | static int pcibus_int_get(struct drvmgr_dev *dev, int index) |
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| 176 | { |
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| 177 | int irq; |
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| 178 | |
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| 179 | /* Relative (positive) or absolute (negative) IRQ number */ |
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| 180 | if (index > 0) { |
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| 181 | /* PCI devices only have one IRQ per function */ |
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| 182 | return -1; |
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| 183 | } else if (index == 0) { |
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| 184 | /* IRQ Index relative to Cores base IRQ */ |
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| 185 | |
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| 186 | /* Get Base IRQ */ |
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| 187 | irq = ((struct pci_dev_info *)dev->businfo)->irq; |
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| 188 | if (irq <= 0) |
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| 189 | return -1; |
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| 190 | } else { |
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| 191 | /* Absolute IRQ number */ |
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| 192 | irq = -index; |
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| 193 | } |
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| 194 | return irq; |
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| 195 | } |
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| 196 | |
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| 197 | /* Use standard PCI facility to register interrupt handler */ |
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| 198 | int pcibus_int_register( |
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| 199 | struct drvmgr_dev *dev, |
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| 200 | int index, |
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| 201 | const char *info, |
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| 202 | drvmgr_isr isr, |
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| 203 | void *arg) |
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| 204 | { |
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| 205 | #ifdef DEBUG |
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| 206 | struct drvmgr_dev *busdev = dev->parent->dev; |
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| 207 | #endif |
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| 208 | int irq; |
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| 209 | |
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| 210 | /* Get IRQ number from index and device information */ |
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| 211 | irq = pcibus_int_get(dev, index); |
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| 212 | if (irq < 0) |
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| 213 | return -1; |
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| 214 | |
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| 215 | DBG("Register PCI interrupt on %p for dev %p (IRQ: %d)\n", |
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| 216 | busdev, dev, irq); |
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| 217 | |
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| 218 | return pci_interrupt_register(irq, info, isr, arg); |
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| 219 | } |
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| 220 | |
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| 221 | /* Use standard PCI facility to unregister interrupt handler */ |
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| 222 | int pcibus_int_unregister( |
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| 223 | struct drvmgr_dev *dev, |
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| 224 | int index, |
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| 225 | drvmgr_isr isr, |
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| 226 | void *arg) |
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| 227 | { |
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| 228 | #ifdef DEBUG |
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| 229 | struct drvmgr_dev *busdev = dev->parent->dev; |
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| 230 | #endif |
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| 231 | int irq; |
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| 232 | |
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| 233 | /* Get IRQ number from index and device information */ |
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| 234 | irq = pcibus_int_get(dev, index); |
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| 235 | if (irq < 0) |
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| 236 | return -1; |
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| 237 | |
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| 238 | DBG("Unregister PCI interrupt on %p for dev %p (IRQ: %d)\n", |
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| 239 | busdev, dev, irq); |
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| 240 | |
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| 241 | return pci_interrupt_unregister(irq, isr, arg); |
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| 242 | } |
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| 243 | |
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| 244 | /* Use standard PCI facility to clear interrupt */ |
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| 245 | int pcibus_int_clear( |
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| 246 | struct drvmgr_dev *dev, |
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| 247 | int index) |
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| 248 | { |
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| 249 | int irq; |
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| 250 | |
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| 251 | /* Get IRQ number from index and device information */ |
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| 252 | irq = pcibus_int_get(dev, index); |
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| 253 | if (irq < 0) |
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| 254 | return -1; |
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| 255 | |
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| 256 | pci_interrupt_clear(irq); |
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| 257 | |
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| 258 | return 0; |
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| 259 | } |
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| 260 | |
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| 261 | int pcibus_freq_get( |
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| 262 | struct drvmgr_dev *dev, |
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| 263 | int options, |
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| 264 | unsigned int *freq_hz) |
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| 265 | { |
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| 266 | /* Standard PCI Bus frequency */ |
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| 267 | *freq_hz = 33000000; |
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| 268 | return 0; |
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| 269 | } |
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| 270 | |
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| 271 | int pcibus_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
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| 272 | { |
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| 273 | /* No device prefix */ |
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| 274 | params->dev_prefix = NULL; |
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| 275 | |
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| 276 | return 0; |
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| 277 | } |
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| 278 | |
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| 279 | #ifdef PCIBUS_INFO |
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| 280 | void pcibus_dev_info( |
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| 281 | struct drvmgr_dev *dev, |
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| 282 | void (*print_line)(void *p, char *str), |
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| 283 | void *p) |
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| 284 | { |
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| 285 | struct pci_dev_info *devinfo; |
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| 286 | struct pcibus_res *pcibusres; |
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| 287 | struct pci_res *res; |
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| 288 | char buf[64]; |
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| 289 | int i; |
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| 290 | char *str1, *res_types[3] = {" IO16", "MEMIO", " MEM"}; |
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| 291 | uint32_t pcistart; |
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| 292 | |
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| 293 | if (!dev) |
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| 294 | return; |
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| 295 | |
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| 296 | devinfo = (struct pci_dev_info *)dev->businfo; |
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| 297 | if (!devinfo) |
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| 298 | return; |
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| 299 | |
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[56ea46ba] | 300 | if ((devinfo->id.class >> 8) == PCID_PCI2PCI_BRIDGE) |
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[1c5a7e5] | 301 | print_line(p, "PCI BRIDGE DEVICE"); |
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| 302 | else |
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| 303 | print_line(p, "PCI DEVICE"); |
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| 304 | sprintf(buf, "LOCATION: BUS:SLOT:FUNCTION [%x:%x:%x]", |
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| 305 | PCI_DEV_EXPAND(devinfo->pcidev)); |
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| 306 | print_line(p, buf); |
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| 307 | sprintf(buf, "PCIID 0x%lx", (uint32_t)devinfo->pcidev); |
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| 308 | print_line(p, buf); |
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| 309 | sprintf(buf, "VENDOR ID: %04x", devinfo->id.vendor); |
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| 310 | print_line(p, buf); |
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| 311 | sprintf(buf, "DEVICE ID: %04x", devinfo->id.device); |
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| 312 | print_line(p, buf); |
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| 313 | sprintf(buf, "SUBVEN ID: %04x", devinfo->id.subvendor); |
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| 314 | print_line(p, buf); |
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| 315 | sprintf(buf, "SUBDEV ID: %04x", devinfo->id.subdevice); |
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| 316 | print_line(p, buf); |
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| 317 | sprintf(buf, "CLASS: %lx", devinfo->id.class); |
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| 318 | print_line(p, buf); |
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| 319 | sprintf(buf, "REVISION: %x", devinfo->rev); |
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| 320 | print_line(p, buf); |
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| 321 | sprintf(buf, "IRQ: %d", devinfo->irq); |
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| 322 | print_line(p, buf); |
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| 323 | sprintf(buf, "PCIDEV ptr: %p", devinfo->pci_device); |
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| 324 | print_line(p, buf); |
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| 325 | |
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| 326 | /* List Resources */ |
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| 327 | print_line(p, "RESOURCES"); |
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| 328 | for (i = 0; i < PCIDEV_RES_CNT; i++) { |
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| 329 | pcibusres = &devinfo->resources[i]; |
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| 330 | |
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| 331 | str1 = " RES"; |
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| 332 | pcistart = -1; |
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| 333 | res = pcibusres->res; |
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| 334 | if (res && (res->flags & PCI_RES_TYPE_MASK)) { |
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| 335 | str1 = res_types[(res->flags & PCI_RES_TYPE_MASK) - 1]; |
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| 336 | if (res->flags & PCI_RES_IO32) |
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| 337 | str1 = " IO32"; |
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| 338 | pcistart = res->start; |
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| 339 | } |
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| 340 | |
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| 341 | if (res && (res->flags & PCI_RES_FAIL)) { |
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| 342 | sprintf(buf, " %s[%d]: NOT ASSIGNED", str1, i); |
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| 343 | print_line(p, buf); |
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| 344 | continue; |
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| 345 | } |
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| 346 | if (!pcibusres->size) |
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| 347 | continue; |
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| 348 | |
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| 349 | sprintf(buf, " %s[%d]: %08lx-%08lx [PCIADR %lx]", |
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| 350 | str1, i, pcibusres->address, |
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| 351 | pcibusres->address + pcibusres->size - 1, pcistart); |
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| 352 | print_line(p, buf); |
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| 353 | } |
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| 354 | } |
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| 355 | #endif |
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| 356 | |
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| 357 | #ifdef USE_PCI_CFG_LIB |
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| 358 | |
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| 359 | static int pcibus_dev_register(struct pci_dev *dev, void *arg) |
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| 360 | { |
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| 361 | struct drvmgr_bus *pcibus = arg; |
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| 362 | struct drvmgr_dev *newdev; |
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| 363 | struct pci_dev_info *pciinfo; |
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| 364 | int i, type; |
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| 365 | struct pcibus_res *pcibusres; |
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| 366 | struct pci_res *pcires; |
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| 367 | |
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| 368 | pci_dev_t pcidev = dev->busdevfun; |
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| 369 | |
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| 370 | DBG("PCI DEV REGISTER: %x:%x:%x\n", PCI_DEV_EXPAND(pcidev)); |
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| 371 | |
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| 372 | /* Allocate a device */ |
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| 373 | drvmgr_alloc_dev(&newdev, 24 + sizeof(struct pci_dev_info)); |
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| 374 | newdev->next = NULL; |
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| 375 | newdev->parent = pcibus; /* Ourselfs */ |
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| 376 | newdev->minor_drv = 0; |
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| 377 | newdev->minor_bus = 0; |
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| 378 | newdev->priv = NULL; |
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| 379 | newdev->drv = NULL; |
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| 380 | newdev->name = (char *)(newdev + 1); |
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| 381 | newdev->next_in_drv = NULL; |
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| 382 | newdev->bus = NULL; |
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| 383 | |
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| 384 | /* Init PnP information, Assign Core interfaces with this device */ |
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| 385 | pciinfo = (struct pci_dev_info *)((char *)(newdev + 1) + 24); |
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| 386 | |
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| 387 | /* Read Device and Vendor */ |
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| 388 | pciinfo->id.vendor = dev->vendor; |
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| 389 | pciinfo->id.device = dev->device; |
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| 390 | pciinfo->id.subvendor = dev->subvendor; |
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| 391 | pciinfo->id.subdevice = dev->subdevice; |
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| 392 | pciinfo->rev = dev->classrev & 0xff; |
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| 393 | pciinfo->id.class = (dev->classrev >> 8) & 0xffffff; |
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| 394 | |
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| 395 | /* Read IRQ information set by PCI layer */ |
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| 396 | pciinfo->irq = dev->sysirq; |
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| 397 | |
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| 398 | /* Save Location on PCI bus */ |
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| 399 | pciinfo->pcidev = pcidev; |
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| 400 | |
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| 401 | /* Connect device with PCI data structure */ |
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| 402 | pciinfo->pci_device = dev; |
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| 403 | |
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| 404 | /* Build resources so that PCI device drivers doesn't have to scan |
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| 405 | * configuration space themselves, also the address is translated |
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| 406 | * into CPU accessible addresses. |
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| 407 | */ |
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| 408 | for (i = 0; i < PCIDEV_RES_CNT; i++) { |
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| 409 | pcibusres = &pciinfo->resources[i]; |
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| 410 | pcires = &dev->resources[i]; |
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| 411 | type = pcires->flags & PCI_RES_TYPE_MASK; |
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| 412 | if (type == 0 || (pcires->flags & PCI_RES_FAIL)) |
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| 413 | continue; /* size=0 */ |
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| 414 | |
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| 415 | pcibusres->address = pcires->start; |
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| 416 | if (pci_pci2cpu(&pcibusres->address, type)) |
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| 417 | continue; /* size=0 */ |
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| 418 | pcibusres->res = pcires; |
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| 419 | pcibusres->size = pcires->end - pcires->start; |
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| 420 | } |
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| 421 | |
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| 422 | /* Connect device with PCI information */ |
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| 423 | newdev->businfo = (void *)pciinfo; |
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| 424 | |
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| 425 | /* Create Device Name */ |
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| 426 | sprintf(newdev->name, "PCI_%x:%x:%x_%04x:%04x", |
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| 427 | PCI_DEV_BUS(pcidev), PCI_DEV_SLOT(pcidev), PCI_DEV_FUNC(pcidev), |
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| 428 | pciinfo->id.vendor, pciinfo->id.device); |
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| 429 | |
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| 430 | /* Register New Device */ |
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| 431 | drvmgr_dev_register(newdev); |
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| 432 | |
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| 433 | return 0; |
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| 434 | } |
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| 435 | |
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| 436 | #else |
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| 437 | |
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| 438 | static int pcibus_dev_register(pci_dev_t pcidev, void *arg) |
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| 439 | { |
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| 440 | struct drvmgr_bus *pcibus = arg; |
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| 441 | struct drvmgr_dev *newdev; |
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| 442 | struct pci_dev_info *pciinfo; |
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| 443 | |
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| 444 | DBG("PCI DEV REGISTER: %x:%x:%x\n", PCI_DEV_EXPAND(pcidev)); |
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| 445 | |
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| 446 | /* Allocate a device */ |
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| 447 | drvmgr_alloc_dev(&newdev, 24 + sizeof(struct pci_dev_info)); |
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| 448 | newdev->next = NULL; |
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| 449 | newdev->parent = pcibus; /* Ourselfs */ |
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| 450 | newdev->minor_drv = 0; |
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| 451 | newdev->minor_bus = 0; |
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| 452 | newdev->priv = NULL; |
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| 453 | newdev->drv = NULL; |
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| 454 | newdev->name = (char *)(newdev + 1); |
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| 455 | newdev->next_in_drv = NULL; |
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| 456 | newdev->bus = NULL; |
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| 457 | |
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| 458 | /* Init PnP information, Assign Core interfaces with this device */ |
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| 459 | pciinfo = (struct pci_dev_info *)((char *)(newdev + 1) + 24); |
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| 460 | |
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| 461 | /* Read Device and Vendor */ |
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[56ea46ba] | 462 | pci_cfg_r16(pcidev, PCIR_VENDOR, &pciinfo->id.vendor); |
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| 463 | pci_cfg_r16(pcidev, PCIR_DEVICE, &pciinfo->id.device); |
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| 464 | pci_cfg_r32(pcidev, PCIR_REVID, &pciinfo->id.class); |
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[1c5a7e5] | 465 | pciinfo->rev = pciinfo->id.class & 0xff; |
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| 466 | pciinfo->id.class = pciinfo->id.class >> 8; |
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| 467 | |
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| 468 | /* Devices have subsytem device and vendor ID */ |
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[56ea46ba] | 469 | if ((pciinfo->id.class >> 8) != PCID_PCI2PCI_BRIDGE) { |
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| 470 | pci_cfg_r16(pcidev, PCIR_SUBVEND_0, |
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[1c5a7e5] | 471 | &pciinfo->id.subvendor); |
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[56ea46ba] | 472 | pci_cfg_r16(pcidev, PCIR_SUBDEV_0, &pciinfo->id.subdevice); |
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[1c5a7e5] | 473 | } else { |
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| 474 | pciinfo->id.subvendor = 0; |
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| 475 | pciinfo->id.subdevice = 0; |
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| 476 | } |
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| 477 | |
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| 478 | /* Read IRQ information set by PCI layer */ |
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[56ea46ba] | 479 | pci_cfg_r8(pcidev, PCIR_INTLINE, &pciinfo->irq); |
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[1c5a7e5] | 480 | |
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| 481 | /* Save Location */ |
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| 482 | pciinfo->pcidev = pcidev; |
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| 483 | |
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| 484 | /* There is no way we can know this information this way */ |
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| 485 | pciinfo->pci_device = NULL; |
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| 486 | |
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| 487 | /* Connect device with PCI information */ |
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| 488 | newdev->businfo = (void *)pciinfo; |
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| 489 | |
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| 490 | /* Create Device Name */ |
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| 491 | sprintf(newdev->name, "PCI_%d:%d:%d_%04x:%04x", |
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| 492 | PCI_DEV_BUS(pcidev), PCI_DEV_SLOT(pcidev), PCI_DEV_FUNC(pcidev), |
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| 493 | pciinfo->id.vendor, pciinfo->id.device); |
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| 494 | |
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| 495 | /* Register New Device */ |
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| 496 | drvmgr_dev_register(newdev); |
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| 497 | |
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| 498 | return 0; |
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| 499 | } |
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| 500 | |
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| 501 | #endif |
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| 502 | |
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| 503 | /* Register all AMBA devices available on the AMBAPP bus */ |
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| 504 | static int pcibus_devs_register(struct drvmgr_bus *bus) |
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| 505 | { |
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| 506 | /* return value 0=DRVMGR_OK works with pci_for_each/pci_for_each_dev */ |
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| 507 | #ifdef USE_PCI_CFG_LIB |
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| 508 | /* Walk the PCI device tree in RAM */ |
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| 509 | return pci_for_each_dev(pcibus_dev_register, bus); |
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| 510 | #else |
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| 511 | /* Scan PCI Configuration space */ |
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| 512 | return pci_for_each(pcibus_dev_register, bus); |
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| 513 | #endif |
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| 514 | } |
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| 515 | |
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| 516 | /*** DEVICE FUNCTIONS ***/ |
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| 517 | |
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| 518 | int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *config) |
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| 519 | { |
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| 520 | struct pcibus_priv *priv; |
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| 521 | int i, fid, rc; |
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| 522 | |
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| 523 | DBG("PCI BUS: initializing\n"); |
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| 524 | |
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| 525 | /* Create BUS */ |
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| 526 | drvmgr_alloc_bus(&dev->bus, sizeof(struct pcibus_priv)); |
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| 527 | dev->bus->bus_type = DRVMGR_BUS_TYPE_PCI; |
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| 528 | dev->bus->next = NULL; |
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| 529 | dev->bus->dev = dev; |
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| 530 | dev->bus->children = NULL; |
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| 531 | dev->bus->ops = &pcibus_ops; |
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| 532 | dev->bus->dev_cnt = 0; |
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| 533 | dev->bus->reslist = NULL; |
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| 534 | dev->bus->maps_up = config->maps_up; |
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| 535 | dev->bus->maps_down = config->maps_down; |
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| 536 | dev->bus->funcs = &pcibus_funcs[0]; |
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| 537 | |
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| 538 | /* Copy function definitions from PCI Layer */ |
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| 539 | for (i=0; i<6; i++) { |
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| 540 | fid = pcibus_funcs[i].funcid; |
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| 541 | rc = pci_access_func(RW_DIR(fid), RW_SIZE(fid), |
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| 542 | &pcibus_funcs[i].func, PCI_LITTLE_ENDIAN, 3); |
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| 543 | if (rc != 0) |
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| 544 | DBG("PCI BUS: MEMREG 0x%x function not defined\n", fid); |
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| 545 | } |
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| 546 | |
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| 547 | /* Add resource configuration if user overrided the default empty cfg */ |
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| 548 | if (pcibus_drv_resources.resource[0].drv_id != 0) |
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| 549 | drvmgr_bus_res_add(dev->bus, &pcibus_drv_resources); |
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| 550 | |
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| 551 | /* Init BUS private structures */ |
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| 552 | priv = (struct pcibus_priv *)(dev->bus + 1); |
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| 553 | dev->bus->priv = priv; |
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| 554 | |
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| 555 | /* Register BUS */ |
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| 556 | drvmgr_bus_register(dev->bus); |
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| 557 | |
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| 558 | return DRVMGR_OK; |
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| 559 | } |
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| 560 | |
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| 561 | /*** BUS INITIALIZE FUNCTIONS ***/ |
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| 562 | |
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| 563 | int pcibus_bus_init1(struct drvmgr_bus *bus) |
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| 564 | { |
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| 565 | return pcibus_devs_register(bus); |
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| 566 | } |
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