1 | /* Routines to access PCI memory/configuration space and other PCI related |
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2 | * functions the PCI Library provides. |
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3 | * |
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4 | * COPYRIGHT (c) 2010. |
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5 | * Cobham Gaisler AB. |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | */ |
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11 | |
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12 | |
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13 | #ifndef __PCI_ACCESS_H__ |
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14 | #define __PCI_ACCESS_H__ |
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15 | |
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16 | #include <stdint.h> |
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17 | #include <libcpu/byteorder.h> |
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18 | #include <pci.h> |
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19 | |
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20 | /* Let BSP configure load/store from PCI */ |
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21 | #include <bsp.h> |
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22 | |
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23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif |
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26 | |
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27 | /* Identification of a PCI configuration space device (16-bit) */ |
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28 | typedef uint16_t pci_dev_t; |
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29 | /* Create a PCI Configuration Space ID */ |
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30 | #define PCI_DEV(bus, slot, func) (((bus)<<8) | ((slot)<<3) | (func)) |
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31 | /* Get Bus of a PCI Configuration Space ID */ |
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32 | #define PCI_DEV_BUS(dev) (((dev) >> 8) & 0xff) |
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33 | /* Get Slot/Device of a PCI Configuration Space ID */ |
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34 | #define PCI_DEV_SLOT(dev) (((dev) >> 3) & 0x1f) |
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35 | /* Get Function of a PCI Configuration Space ID */ |
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36 | #define PCI_DEV_FUNC(dev) ((dev) & 0x7) |
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37 | /* Get Device and Function of a PCI Configuration Space ID */ |
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38 | #define PCI_DEV_DEVFUNC(dev) ((dev) & 0xff) |
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39 | /* Expand Device into argument lists */ |
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40 | #define PCI_DEV_EXPAND(dev) PCI_DEV_BUS((dev)), PCI_DEV_SLOT((dev)), PCI_DEV_FUNC((dev)) |
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41 | |
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42 | /* Configuration Space Read/Write Operations */ |
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43 | struct pci_cfg_ops { |
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44 | /* Configuration Space Access and Setup Routines */ |
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45 | int (*read8)(pci_dev_t dev, int ofs, uint8_t *data); |
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46 | int (*read16)(pci_dev_t dev, int ofs, uint16_t *data); |
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47 | int (*read32)(pci_dev_t dev, int ofs, uint32_t *data); |
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48 | int (*write8)(pci_dev_t dev, int ofs, uint8_t data); |
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49 | int (*write16)(pci_dev_t dev, int ofs, uint16_t data); |
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50 | int (*write32)(pci_dev_t dev, int ofs, uint32_t data); |
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51 | }; |
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52 | |
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53 | /* Read a register over PCI I/O Space, and swap it if necessary (due to |
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54 | * PCI endianness) |
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55 | */ |
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56 | struct pci_io_ops { |
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57 | uint8_t (*read8)(uint8_t *adr); |
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58 | uint16_t(*read16)(uint16_t *adr); |
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59 | uint32_t (*read32)(uint32_t *adr); |
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60 | void (*write8)(uint8_t *adr, uint8_t data); |
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61 | void (*write16)(uint16_t *adr, uint16_t data); |
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62 | void (*write32)(uint32_t *adr, uint32_t data); |
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63 | }; |
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64 | |
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65 | /* Read a register over PCI Memory Space (non-prefetchable memory), and |
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66 | * swap it if necessary (due to PCI endianness) |
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67 | */ |
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68 | struct pci_memreg_ops { |
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69 | uint8_t (*ld8)(uint8_t *adr); |
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70 | void (*st8)(uint8_t *adr, uint8_t data); |
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71 | |
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72 | uint16_t(*ld_le16)(uint16_t *adr); |
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73 | void (*st_le16)(uint16_t *adr, uint16_t data); |
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74 | uint16_t(*ld_be16)(uint16_t *adr); |
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75 | void (*st_be16)(uint16_t *adr, uint16_t data); |
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76 | |
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77 | uint32_t (*ld_le32)(uint32_t *adr); |
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78 | void (*st_le32)(uint32_t *adr, uint32_t data); |
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79 | uint32_t (*ld_be32)(uint32_t *adr); |
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80 | void (*st_be32)(uint32_t *adr, uint32_t data); |
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81 | }; |
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82 | |
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83 | typedef uint8_t (*pci_ld8_t)(uint8_t *adr); |
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84 | typedef void (*pci_st8_t)(uint8_t *adr, uint8_t data); |
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85 | typedef uint16_t(pci_ld16_t)(uint16_t *adr); |
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86 | typedef void (*pci_st16_t)(uint16_t *adr, uint16_t data); |
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87 | typedef uint32_t (*pci_ld32_t)(uint32_t *adr); |
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88 | typedef void (*pci_st32_t)(uint32_t *adr, uint32_t data); |
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89 | |
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90 | struct pci_access_drv { |
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91 | /* Configuration */ |
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92 | struct pci_cfg_ops cfg; |
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93 | |
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94 | /* I/O Access operations */ |
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95 | struct pci_io_ops io; |
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96 | |
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97 | /* Registers over Memory Access operations. Note that these funcs |
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98 | * are only for code that need to be compatible with both Big-Endian |
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99 | * and Little-Endian PCI bus or for some other reason need function |
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100 | * pointers to access functions. Normally drivers use the inline |
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101 | * functions for Registers-over-Memory access to avoid extra function |
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102 | * call. |
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103 | */ |
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104 | struct pci_memreg_ops *memreg; |
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105 | |
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106 | /* Translate from PCI address to CPU address (dir=0). Translate |
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107 | * CPU address to PCI address (dir!=0). The address will can be |
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108 | * used to perform I/O access or memory access by CPU or PCI DMA |
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109 | * peripheral. |
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110 | * |
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111 | * address In/Out. CPU address or PCI address. |
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112 | * type Access type. 1=I/O, 2=MEMIO, 3=MEM |
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113 | * dir Translate direction. 0=PCI-to-CPU, 0!=CPU-to-PCI, |
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114 | * |
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115 | * Return Value |
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116 | * 0 = Success |
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117 | * -1 = Requested Address not mapped into other address space |
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118 | * i.e. not accessible |
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119 | */ |
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120 | int (*translate)(uint32_t *address, int type, int dir); |
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121 | }; |
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122 | |
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123 | /* Access Routines valid after a PCI-Access-Driver has registered */ |
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124 | extern struct pci_access_drv pci_access_ops; |
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125 | |
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126 | /* Register PCI Access Driver */ |
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127 | extern int pci_access_drv_register(struct pci_access_drv *drv); |
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128 | |
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129 | /* Set/unset bits in command and status register of a PCI device */ |
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130 | extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val); |
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131 | |
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132 | /* Enable Memory in command register */ |
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133 | static inline void pci_mem_enable(pci_dev_t dev) |
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134 | { |
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135 | pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, PCI_COMMAND_MEMORY); |
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136 | } |
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137 | |
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138 | static inline void pci_mem_disable(pci_dev_t dev) |
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139 | { |
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140 | pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, 0); |
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141 | } |
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142 | |
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143 | static inline void pci_io_enable(pci_dev_t dev) |
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144 | { |
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145 | pci_modify_cmdsts(dev, PCI_COMMAND_IO, PCI_COMMAND_IO); |
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146 | } |
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147 | |
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148 | static inline void pci_io_disable(pci_dev_t dev) |
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149 | { |
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150 | pci_modify_cmdsts(dev, PCI_COMMAND_IO, 0); |
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151 | } |
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152 | |
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153 | static inline void pci_master_enable(pci_dev_t dev) |
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154 | { |
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155 | pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, PCI_COMMAND_MASTER); |
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156 | } |
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157 | |
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158 | static inline void pci_master_disable(pci_dev_t dev) |
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159 | { |
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160 | pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, 0); |
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161 | } |
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162 | |
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163 | /* Configuration Space Access Read Routines */ |
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164 | extern int pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *data); |
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165 | extern int pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *data); |
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166 | extern int pci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *data); |
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167 | |
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168 | /* Configuration Space Access Write Routines */ |
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169 | extern int pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t data); |
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170 | extern int pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t data); |
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171 | extern int pci_cfg_w32(pci_dev_t dev, int ofs, uint32_t data); |
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172 | |
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173 | /* Read a register over PCI I/O Space */ |
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174 | extern uint8_t pci_io_r8(uint32_t adr); |
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175 | extern uint16_t pci_io_r16(uint32_t adr); |
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176 | extern uint32_t pci_io_r32(uint32_t adr); |
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177 | |
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178 | /* Write a register over PCI I/O Space */ |
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179 | extern void pci_io_w8(uint32_t adr, uint8_t data); |
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180 | extern void pci_io_w16(uint32_t adr, uint16_t data); |
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181 | extern void pci_io_w32(uint32_t adr, uint32_t data); |
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182 | |
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183 | /* Translate PCI address into CPU accessible address */ |
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184 | static inline int pci_pci2cpu(uint32_t *address, int type) |
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185 | { |
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186 | return pci_access_ops.translate(address, type, 0); |
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187 | } |
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188 | |
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189 | /* Translate CPU accessible address into PCI address (for DMA) */ |
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190 | static inline int pci_cpu2pci(uint32_t *address, int type) |
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191 | { |
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192 | return pci_access_ops.translate(address, type, 1); |
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193 | } |
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194 | |
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195 | /*** Read/Write a register over PCI Memory Space ***/ |
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196 | |
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197 | static inline uint8_t pci_ld8(volatile uint8_t *addr) |
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198 | { |
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199 | return *addr; |
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200 | } |
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201 | |
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202 | static inline void pci_st8(volatile uint8_t *addr, uint8_t val) |
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203 | { |
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204 | *addr = val; |
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205 | } |
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206 | |
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207 | #ifdef BSP_PCI_BIG_ENDIAN |
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208 | |
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209 | /* BSP has decided Big Endian PCI Bus (non-standard) */ |
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210 | |
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211 | static inline uint16_t pci_ld_le16(volatile uint16_t *addr) |
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212 | { |
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213 | return ld_be16(addr); |
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214 | } |
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215 | |
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216 | static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) |
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217 | { |
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218 | st_be16(addr, val); |
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219 | } |
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220 | |
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221 | static inline uint32_t pci_ld_le32(volatile uint32_t *addr) |
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222 | { |
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223 | return ld_be32(addr); |
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224 | } |
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225 | |
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226 | static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) |
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227 | { |
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228 | st_be32(addr, val); |
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229 | } |
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230 | |
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231 | static inline uint16_t pci_ld_be16(volatile uint16_t *addr) |
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232 | { |
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233 | return ld_le16(addr); |
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234 | } |
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235 | |
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236 | static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) |
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237 | { |
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238 | st_le16(addr, val); |
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239 | } |
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240 | |
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241 | static inline uint32_t pci_ld_be32(volatile uint32_t *addr) |
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242 | { |
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243 | return ld_le32(addr); |
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244 | } |
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245 | |
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246 | static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) |
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247 | { |
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248 | st_le32(addr, val); |
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249 | } |
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250 | |
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251 | #else |
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252 | |
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253 | /* Little Endian PCI Bus */ |
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254 | |
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255 | static inline uint16_t pci_ld_le16(volatile uint16_t *addr) |
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256 | { |
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257 | return ld_le16(addr); |
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258 | } |
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259 | |
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260 | static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) |
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261 | { |
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262 | st_le16(addr, val); |
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263 | } |
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264 | |
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265 | static inline uint32_t pci_ld_le32(volatile uint32_t *addr) |
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266 | { |
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267 | return ld_le32(addr); |
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268 | } |
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269 | |
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270 | static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) |
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271 | { |
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272 | st_le32(addr, val); |
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273 | } |
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274 | |
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275 | static inline uint16_t pci_ld_be16(volatile uint16_t *addr) |
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276 | { |
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277 | return ld_be16(addr); |
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278 | } |
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279 | |
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280 | static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) |
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281 | { |
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282 | st_be16(addr, val); |
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283 | } |
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284 | |
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285 | static inline uint32_t pci_ld_be32(volatile uint32_t *addr) |
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286 | { |
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287 | return ld_be32(addr); |
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288 | } |
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289 | |
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290 | static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) |
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291 | { |
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292 | st_be32(addr, val); |
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293 | } |
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294 | |
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295 | #endif |
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296 | |
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297 | /* Registers-over-Memory Space access routines. The routines are not inlined |
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298 | * so it is possible during run-time to select which function implemention |
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299 | * to use. The use of these functions are not recommended since it will have a |
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300 | * performance penalty. |
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301 | * |
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302 | * 8-bit accesses are the same for Little and Big endian PCI buses. |
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303 | */ |
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304 | uint8_t pci_mem_ld8(uint8_t *adr); |
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305 | void pci_mem_st8(uint8_t *adr, uint8_t data); |
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306 | /* Registers-over-Memory Space - Generic Big endian PCI bus definitions */ |
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307 | uint16_t pci_mem_be_ld_le16(uint16_t *adr); |
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308 | uint16_t pci_mem_be_ld_be16(uint16_t *adr); |
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309 | uint32_t pci_mem_be_ld_le32(uint32_t *adr); |
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310 | uint32_t pci_mem_be_ld_be32(uint32_t *adr); |
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311 | void pci_mem_be_st_le16(uint16_t *adr, uint16_t data); |
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312 | void pci_mem_be_st_be16(uint16_t *adr, uint16_t data); |
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313 | void pci_mem_be_st_le32(uint32_t *adr, uint32_t data); |
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314 | void pci_mem_be_st_be32(uint32_t *adr, uint32_t data); |
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315 | /* Registers-over-Memory Space - Generic Little endian PCI bus definitions */ |
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316 | uint16_t pci_mem_le_ld_le16(uint16_t *adr); |
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317 | uint16_t pci_mem_le_ld_be16(uint16_t *adr); |
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318 | uint32_t pci_mem_le_ld_le32(uint32_t *adr); |
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319 | uint32_t pci_mem_le_ld_be32(uint32_t *adr); |
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320 | void pci_mem_le_st_le16(uint16_t *adr, uint16_t data); |
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321 | void pci_mem_le_st_be16(uint16_t *adr, uint16_t data); |
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322 | void pci_mem_le_st_le32(uint32_t *adr, uint32_t data); |
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323 | void pci_mem_le_st_be32(uint32_t *adr, uint32_t data); |
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324 | |
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325 | /* Get Read/Write function for accessing a register over PCI Memory Space |
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326 | * (non-inline functions). |
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327 | * |
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328 | * Arguments |
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329 | * wr 0(Read), 1(Write) |
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330 | * size 1(Byte), 2(Word), 4(Double Word) |
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331 | * func Where function pointer will be stored |
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332 | * endian PCI_LITTLE_ENDIAN or PCI_BIG_ENDIAN |
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333 | * type 1(I/O), 3(REG over MEM), 4(CFG) |
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334 | * |
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335 | * Return |
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336 | * 0 Found function |
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337 | * others No such function defined by host driver or BSP |
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338 | */ |
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339 | extern int pci_access_func(int wr, int size, void **func, int endian, int type); |
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340 | |
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341 | /* Predefined functions for Host drivers or BSPs that define the |
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342 | * register-over-memory space functions operations. |
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343 | */ |
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344 | extern struct pci_memreg_ops pci_mem_le_ops; /* For Little-Endian PCI bus */ |
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345 | extern struct pci_memreg_ops pci_mem_be_ops; /* For Big-Endian PCI bus */ |
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346 | |
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347 | #ifdef __cplusplus |
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348 | } |
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349 | #endif |
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350 | |
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351 | #endif /* !__PCI_ACCESS_H__ */ |
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