source: rtems/cpukit/libpci/pci.h @ a31845f7

4.11
Last change on this file since a31845f7 was a31845f7, checked in by Daniel Hellstrom <daniel@…>, on Nov 28, 2011 at 9:11:10 AM

LIBPCI: added PCI layer to cpukit/libpci

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1/*
2 *
3 *      PCI defines and function prototypes
4 *      Copyright 1994, Drew Eckhardt
5 *      Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
6 *
7 *      New PCI library written from scratch. Defines in this file was reused.
8 *      auto-generated pci_ids.h also reused.
9 *      Copyright 2009, Cobham Gaisler AB
10 *
11 *      For more information, please consult the following manuals (look at
12 *      http://www.pcisig.com/ for how to get them):
13 *
14 *      PCI BIOS Specification
15 *      PCI Local Bus Specification
16 *      PCI to PCI Bridge Specification
17 *      PCI System Design Guide
18 */
19
20#ifndef __PCI_H__
21#define __PCI_H__
22
23#include <pci/ids.h>
24
25/*
26 * Under PCI, each device has 256 bytes of configuration address space,
27 * of which the first 64 bytes are standardized as follows:
28 */
29#define PCI_VENDOR_ID           0x00    /* 16 bits */
30#define PCI_DEVICE_ID           0x02    /* 16 bits */
31#define PCI_COMMAND             0x04    /* 16 bits */
32#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
33#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
34#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
35#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
36#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
37#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
38#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
39#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
40#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
41#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
42
43#define PCI_STATUS              0x06    /* 16 bits */
44#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
45#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features */
46
47#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
48#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
49#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
50#define  PCI_STATUS_DEVSEL_FAST 0x000
51#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
52#define  PCI_STATUS_DEVSEL_SLOW 0x400
53#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
54#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
55#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
56#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
57#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
58
59#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
60                                           revision */
61#define PCI_REVISION_ID         0x08    /* Revision ID */
62#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
63#define PCI_CLASS_DEVICE        0x0a    /* Device class */
64
65#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
66#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
67#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
68#define  PCI_HEADER_TYPE_NORMAL 0
69#define  PCI_HEADER_TYPE_BRIDGE 1
70#define  PCI_HEADER_TYPE_CARDBUS 2
71
72#define PCI_BIST                0x0f    /* 8 bits */
73#define PCI_BIST_CODE_MASK      0x0f    /* Return result */
74#define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
75#define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
76
77/*
78 * Base addresses specify locations in memory or I/O space.
79 * Decoded size can be determined by writing a value of
80 * 0xffffffff to the register, and reading it back. Only
81 * 1 bits are decoded.
82 */
83#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
84#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
85#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
86#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
87#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
88#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
89#define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
90#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
91#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
92#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
93#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
94#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
95#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
96#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
97#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
98#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
99/* bit 1 is reserved if address_space = 1 */
100
101/* Header type 0 (normal devices) */
102#define PCI_CARDBUS_CIS         0x28
103#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
104#define PCI_SUBSYSTEM_ID        0x2e
105#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
106#define  PCI_ROM_ADDRESS_ENABLE 0x01
107#define  PCI_ROM_ADDRESS_MASK   (~0x7ffUL)
108
109/* 0x34 Capabilities Pointer (PCI 2.3) */
110#define PCI_CAP_PTR             0x34    /* 8 bits */
111
112/* 0x35-0x3b are reserved */
113#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
114#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
115#define PCI_MIN_GNT             0x3e    /* 8 bits */
116#define PCI_MAX_LAT             0x3f    /* 8 bits */
117
118/* Header type 1 (PCI-to-PCI bridges) */
119#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
120#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
121#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
122#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
123#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
124#define PCI_IO_LIMIT            0x1d
125#define  PCI_IO_RANGE_TYPE_MASK 0x0f    /* I/O bridging type */
126#define  PCI_IO_RANGE_TYPE_16   0x00
127#define  PCI_IO_RANGE_TYPE_32   0x01
128#define  PCI_IO_RANGE_MASK      (~0x0f)
129#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
130#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
131#define PCI_MEMORY_LIMIT        0x22
132#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
133#define  PCI_MEMORY_RANGE_MASK  (~0x0f)
134#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
135#define PCI_PREF_MEMORY_LIMIT   0x26
136#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
137#define  PCI_PREF_RANGE_TYPE_32 0x00
138#define  PCI_PREF_RANGE_TYPE_64 0x01
139#define  PCI_PREF_RANGE_MASK    (~0x0f)
140#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
141#define PCI_PREF_LIMIT_UPPER32  0x2c
142#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
143#define PCI_IO_LIMIT_UPPER16    0x32
144/* 0x34-0x3b is reserved */
145#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
146/* 0x3c-0x3d are same as for htype 0 */
147#define PCI_BRIDGE_CONTROL      0x3e
148#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
149#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
150#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
151#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
152#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
153#define  PCI_BRIDGE_CTL_BUS_RESET 0x40  /* Secondary bus reset */
154#define  PCI_BRIDGE_CTL_FAST_BACK 0x80  /* Fast Back2Back enabled on secondary interface */
155
156/* Header type 2 (CardBus bridges) */
157/* 0x14-0x15 reserved */
158#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
159#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
160#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
161#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
162#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
163#define PCI_CB_MEMORY_BASE_0    0x1c
164#define PCI_CB_MEMORY_LIMIT_0   0x20
165#define PCI_CB_MEMORY_BASE_1    0x24
166#define PCI_CB_MEMORY_LIMIT_1   0x28
167#define PCI_CB_IO_BASE_0        0x2c
168#define PCI_CB_IO_BASE_0_HI     0x2e
169#define PCI_CB_IO_LIMIT_0       0x30
170#define PCI_CB_IO_LIMIT_0_HI    0x32
171#define PCI_CB_IO_BASE_1        0x34
172#define PCI_CB_IO_BASE_1_HI     0x36
173#define PCI_CB_IO_LIMIT_1       0x38
174#define PCI_CB_IO_LIMIT_1_HI    0x3a
175#define  PCI_CB_IO_RANGE_MASK   (~0x03)
176/* 0x3c-0x3d are same as for htype 0 */
177#define PCI_CB_BRIDGE_CONTROL   0x3e
178#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
179#define  PCI_CB_BRIDGE_CTL_SERR         0x02
180#define  PCI_CB_BRIDGE_CTL_ISA          0x04
181#define  PCI_CB_BRIDGE_CTL_VGA          0x08
182#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
183#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
184#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
185#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
186#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
187#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
188#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
189#define PCI_CB_SUBSYSTEM_ID     0x42
190#define PCI_CB_LEGACY_MODE_BASE 0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
191/* 0x48-0x7f reserved */
192
193/* Device classes and subclasses */
194
195#define PCI_CLASS_NOT_DEFINED           0x0000
196#define PCI_CLASS_NOT_DEFINED_VGA       0x0001
197
198#define PCI_BASE_CLASS_STORAGE          0x01
199#define PCI_CLASS_STORAGE_SCSI          0x0100
200#define PCI_CLASS_STORAGE_IDE           0x0101
201#define PCI_CLASS_STORAGE_FLOPPY        0x0102
202#define PCI_CLASS_STORAGE_IPI           0x0103
203#define PCI_CLASS_STORAGE_RAID          0x0104
204#define PCI_CLASS_STORAGE_OTHER         0x0180
205
206#define PCI_BASE_CLASS_NETWORK          0x02
207#define PCI_CLASS_NETWORK_ETHERNET      0x0200
208#define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
209#define PCI_CLASS_NETWORK_FDDI          0x0202
210#define PCI_CLASS_NETWORK_ATM           0x0203
211#define PCI_CLASS_NETWORK_OTHER         0x0280
212
213#define PCI_BASE_CLASS_DISPLAY          0x03
214#define PCI_CLASS_DISPLAY_VGA           0x0300
215#define PCI_CLASS_DISPLAY_XGA           0x0301
216#define PCI_CLASS_DISPLAY_OTHER         0x0380
217
218#define PCI_BASE_CLASS_MULTIMEDIA       0x04
219#define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
220#define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
221#define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
222
223#define PCI_BASE_CLASS_MEMORY           0x05
224#define  PCI_CLASS_MEMORY_RAM           0x0500
225#define  PCI_CLASS_MEMORY_FLASH         0x0501
226#define  PCI_CLASS_MEMORY_OTHER         0x0580
227
228#define PCI_BASE_CLASS_BRIDGE           0x06
229#define  PCI_CLASS_BRIDGE_HOST          0x0600
230#define  PCI_CLASS_BRIDGE_ISA           0x0601
231#define  PCI_CLASS_BRIDGE_EISA          0x0602
232#define  PCI_CLASS_BRIDGE_MC            0x0603
233#define  PCI_CLASS_BRIDGE_PCI           0x0604
234#define  PCI_CLASS_BRIDGE_PCMCIA        0x0605
235#define  PCI_CLASS_BRIDGE_NUBUS         0x0606
236#define  PCI_CLASS_BRIDGE_CARDBUS       0x0607
237#define  PCI_CLASS_BRIDGE_OTHER         0x0680
238
239#define PCI_BASE_CLASS_COMMUNICATION    0x07
240#define PCI_CLASS_COMMUNICATION_SERIAL  0x0700
241#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
242#define PCI_CLASS_COMMUNICATION_OTHER   0x0780
243
244#define PCI_BASE_CLASS_SYSTEM           0x08
245#define PCI_CLASS_SYSTEM_PIC            0x0800
246#define PCI_CLASS_SYSTEM_DMA            0x0801
247#define PCI_CLASS_SYSTEM_TIMER          0x0802
248#define PCI_CLASS_SYSTEM_RTC            0x0803
249#define PCI_CLASS_SYSTEM_OTHER          0x0880
250
251#define PCI_BASE_CLASS_INPUT            0x09
252#define PCI_CLASS_INPUT_KEYBOARD        0x0900
253#define PCI_CLASS_INPUT_PEN             0x0901
254#define PCI_CLASS_INPUT_MOUSE           0x0902
255#define PCI_CLASS_INPUT_OTHER           0x0980
256
257#define PCI_BASE_CLASS_DOCKING          0x0a
258#define PCI_CLASS_DOCKING_GENERIC       0x0a00
259#define PCI_CLASS_DOCKING_OTHER         0x0a01
260
261#define PCI_BASE_CLASS_PROCESSOR        0x0b
262#define PCI_CLASS_PROCESSOR_386         0x0b00
263#define PCI_CLASS_PROCESSOR_486         0x0b01
264#define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02
265#define PCI_CLASS_PROCESSOR_ALPHA       0x0b10
266#define PCI_CLASS_PROCESSOR_POWERPC     0x0b20
267#define PCI_CLASS_PROCESSOR_CO          0x0b40
268
269#define PCI_BASE_CLASS_SERIAL           0x0c
270#define PCI_CLASS_SERIAL_FIREWIRE       0x0c00
271#define PCI_CLASS_SERIAL_ACCESS         0x0c01
272#define PCI_CLASS_SERIAL_SSA            0x0c02
273#define PCI_CLASS_SERIAL_USB            0x0c03
274#define PCI_CLASS_SERIAL_FIBER          0x0c04
275
276#define PCI_CLASS_OTHERS                0xff
277
278#define PCI_INVALID_VENDORDEVICEID    0xffffffff
279#define PCI_MULTI_FUNCTION            0x80
280
281#define PCI_MAX_DEVICES                 32
282#define PCI_MAX_FUNCTIONS               8
283
284#include <pci/access.h>
285
286#ifdef __cplusplus
287extern "C" {
288#endif
289
290/* The PCI Library have the following build time configuration options. It is
291 * up to the BSP header file (bsp.h) to set options properly.
292 *
293 * BSP_PCI_BIG_ENDIAN    - Access inline routines will be for a big-endian PCI
294 *                         bus, if not defined the routines will assume that
295 *                         PCI is as the standard defines: little-endian.
296 *
297 *                         Note that drivers may be run-time configurable,
298 *                         meaning that they may adopt to either big-endian or
299 *                         little-endian PCI bus, the host driver or BSP may
300 *                         detect endianness during run-time.
301 */
302
303/* Error return values */
304enum {
305        PCISTS_ERR         = -1, /* Undefined Error */
306        PCISTS_OK          = 0,
307        PCISTS_EINVAL      = 1, /* Bad input arguments */
308        PCISTS_MSTABRT     = 2, /* CFG space access error (can be ignored) */
309};
310
311/* PCI System type can be used to determine system for drivers. Normally
312 * the system is Host, but the peripheral configuration library also supports
313 * being PCI peripheral not allowed to access configuration space.
314 *
315 * The active configuration Library set this variable.
316 */
317enum {
318        PCI_SYSTEM_NONE = 0,
319        PCI_SYSTEM_HOST = 1,
320        PCI_SYSTEM_PERIPHERAL = 2,
321};
322extern int pci_system_type;
323
324/* PCI Bus Endianness. The PCI specification is little endian, however on some
325 * embedded systems (AT697-LEON2 for example) the PCI bus is defined as big
326 * endian (non-standard) in order to avoid byte-twisting.
327 */
328enum {
329        PCI_LITTLE_ENDIAN = 0,
330        PCI_BIG_ENDIAN = 1,
331};
332extern int pci_endian;
333
334/* Return the number of PCI busses in the system */
335extern int pci_bus_count(void);
336
337/* Scan the PCI bus and print the PCI device/functions/bridges and their
338 * current resources and size to the system console.
339 */
340extern void pci_print(void);
341
342/* Print current configuration of a single PCI device by reading PCI
343 * configuration space
344 */
345extern void pci_print_dev(pci_dev_t dev);
346extern void pci_print_device(int bus, int slot, int function);
347
348/*** PCI Configuration Space direct access routines ***/
349
350/* Function iterates over all PCI buses/devices/functions and calls
351 * func(PCIDEV,arg) for each present device. The iteration is stopped if
352 * func() returns non-zero result the same result is returned. As long
353 * as func() returns zero the function will keep on iterating, when all
354 * devices has been processed the function return zero.
355 *
356 * The function iterates over all devices/functions on all buses by accessing
357 * configuration space directly (PCI RAM data structures not used). This
358 * function is valid to call after PCI buses have been enumrated.
359 */
360extern int pci_for_each(int (*func)(pci_dev_t, void*), void *arg);
361
362/* Get PCI Configuration space BUS|SLOT|FUNC for a device matching PCI
363 * Vendor, Device and instance number 'index'.
364 *
365 * Return Values
366 * -1  pci_find_dev did not find a device matching the criterion.
367 *  0  device was found, *pdev was updated with the device's BUS|SLOT|FUNC
368 */
369extern int pci_find(uint16_t ven, uint16_t dev, int index, pci_dev_t *pdev);
370
371#ifdef __cplusplus
372}
373#endif
374
375#endif /* __PCI_H__ */
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