| 1 | /* |
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| 2 | * |
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| 3 | * PCI defines and function prototypes |
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| 4 | * Copyright 1994, Drew Eckhardt |
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| 5 | * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> |
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| 6 | * |
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| 7 | * New PCI library written from scratch. Defines in this file was reused. |
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| 8 | * auto-generated pci_ids.h also reused. |
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| 9 | * Copyright 2009, Cobham Gaisler AB |
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| 10 | * |
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| 11 | * For more information, please consult the following manuals (look at |
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| 12 | * http://www.pcisig.com/ for how to get them): |
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| 13 | * |
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| 14 | * PCI BIOS Specification |
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| 15 | * PCI Local Bus Specification |
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| 16 | * PCI to PCI Bridge Specification |
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| 17 | * PCI System Design Guide |
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| 18 | */ |
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| 19 | |
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| 20 | #ifndef __PCI_H__ |
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| 21 | #define __PCI_H__ |
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| 22 | |
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| 23 | #include <pci/ids.h> |
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| 24 | |
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| 25 | /* |
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| 26 | * Under PCI, each device has 256 bytes of configuration address space, |
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| 27 | * of which the first 64 bytes are standardized as follows: |
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| 28 | */ |
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| 29 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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| 30 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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| 31 | #define PCI_COMMAND 0x04 /* 16 bits */ |
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| 32 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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| 33 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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| 34 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
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| 35 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
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| 36 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
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| 37 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
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| 38 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
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| 39 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
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| 40 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
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| 41 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
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| 42 | |
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| 43 | #define PCI_STATUS 0x06 /* 16 bits */ |
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| 44 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
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| 45 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features */ |
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| 46 | |
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| 47 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
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| 48 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
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| 49 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
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| 50 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
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| 51 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
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| 52 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
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| 53 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
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| 54 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
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| 55 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
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| 56 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
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| 57 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
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| 58 | |
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| 59 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
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| 60 | revision */ |
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| 61 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
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| 62 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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| 63 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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| 64 | |
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| 65 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
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| 66 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
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| 67 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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| 68 | #define PCI_HEADER_TYPE_NORMAL 0 |
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| 69 | #define PCI_HEADER_TYPE_BRIDGE 1 |
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| 70 | #define PCI_HEADER_TYPE_CARDBUS 2 |
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| 71 | |
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| 72 | #define PCI_BIST 0x0f /* 8 bits */ |
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| 73 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
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| 74 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
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| 75 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
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| 76 | |
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| 77 | /* |
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| 78 | * Base addresses specify locations in memory or I/O space. |
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| 79 | * Decoded size can be determined by writing a value of |
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| 80 | * 0xffffffff to the register, and reading it back. Only |
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| 81 | * 1 bits are decoded. |
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| 82 | */ |
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| 83 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
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| 84 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
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| 85 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
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| 86 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
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| 87 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
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| 88 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
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| 89 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
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| 90 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
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| 91 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
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| 92 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
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| 93 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
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| 94 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */ |
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| 95 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
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| 96 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
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| 97 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
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| 98 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
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| 99 | /* bit 1 is reserved if address_space = 1 */ |
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| 100 | |
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| 101 | /* Header type 0 (normal devices) */ |
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| 102 | #define PCI_CARDBUS_CIS 0x28 |
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| 103 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
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| 104 | #define PCI_SUBSYSTEM_ID 0x2e |
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| 105 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
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| 106 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
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| 107 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
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| 108 | |
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| 109 | /* 0x34 Capabilities Pointer (PCI 2.3) */ |
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| 110 | #define PCI_CAP_PTR 0x34 /* 8 bits */ |
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| 111 | |
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| 112 | /* 0x35-0x3b are reserved */ |
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| 113 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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| 114 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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| 115 | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
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| 116 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
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| 117 | |
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| 118 | /* Header type 1 (PCI-to-PCI bridges) */ |
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| 119 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
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| 120 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
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| 121 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
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| 122 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ |
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| 123 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
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| 124 | #define PCI_IO_LIMIT 0x1d |
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| 125 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ |
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| 126 | #define PCI_IO_RANGE_TYPE_16 0x00 |
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| 127 | #define PCI_IO_RANGE_TYPE_32 0x01 |
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| 128 | #define PCI_IO_RANGE_MASK (~0x0f) |
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| 129 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
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| 130 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
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| 131 | #define PCI_MEMORY_LIMIT 0x22 |
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| 132 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f |
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| 133 | #define PCI_MEMORY_RANGE_MASK (~0x0f) |
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| 134 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
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| 135 | #define PCI_PREF_MEMORY_LIMIT 0x26 |
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| 136 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f |
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| 137 | #define PCI_PREF_RANGE_TYPE_32 0x00 |
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| 138 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
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| 139 | #define PCI_PREF_RANGE_MASK (~0x0f) |
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| 140 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
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| 141 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
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| 142 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
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| 143 | #define PCI_IO_LIMIT_UPPER16 0x32 |
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| 144 | /* 0x34-0x3b is reserved */ |
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| 145 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
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| 146 | /* 0x3c-0x3d are same as for htype 0 */ |
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| 147 | #define PCI_BRIDGE_CONTROL 0x3e |
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| 148 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
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| 149 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
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| 150 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
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| 151 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
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| 152 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
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| 153 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
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| 154 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
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| 155 | |
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| 156 | /* Header type 2 (CardBus bridges) */ |
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| 157 | /* 0x14-0x15 reserved */ |
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| 158 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ |
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| 159 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ |
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| 160 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ |
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| 161 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ |
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| 162 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
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| 163 | #define PCI_CB_MEMORY_BASE_0 0x1c |
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| 164 | #define PCI_CB_MEMORY_LIMIT_0 0x20 |
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| 165 | #define PCI_CB_MEMORY_BASE_1 0x24 |
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| 166 | #define PCI_CB_MEMORY_LIMIT_1 0x28 |
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| 167 | #define PCI_CB_IO_BASE_0 0x2c |
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| 168 | #define PCI_CB_IO_BASE_0_HI 0x2e |
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| 169 | #define PCI_CB_IO_LIMIT_0 0x30 |
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| 170 | #define PCI_CB_IO_LIMIT_0_HI 0x32 |
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| 171 | #define PCI_CB_IO_BASE_1 0x34 |
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| 172 | #define PCI_CB_IO_BASE_1_HI 0x36 |
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| 173 | #define PCI_CB_IO_LIMIT_1 0x38 |
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| 174 | #define PCI_CB_IO_LIMIT_1_HI 0x3a |
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| 175 | #define PCI_CB_IO_RANGE_MASK (~0x03) |
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| 176 | /* 0x3c-0x3d are same as for htype 0 */ |
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| 177 | #define PCI_CB_BRIDGE_CONTROL 0x3e |
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| 178 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
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| 179 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 |
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| 180 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 |
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| 181 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 |
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| 182 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 |
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| 183 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ |
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| 184 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ |
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| 185 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ |
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| 186 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 |
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| 187 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 |
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| 188 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
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| 189 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
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| 190 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ |
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| 191 | /* 0x48-0x7f reserved */ |
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| 192 | |
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| 193 | /* Device classes and subclasses */ |
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| 194 | |
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| 195 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
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| 196 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
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| 197 | |
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| 198 | #define PCI_BASE_CLASS_STORAGE 0x01 |
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| 199 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
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| 200 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
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| 201 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
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| 202 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
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| 203 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
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| 204 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
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| 205 | |
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| 206 | #define PCI_BASE_CLASS_NETWORK 0x02 |
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| 207 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
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| 208 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
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| 209 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
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| 210 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
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| 211 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
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| 212 | |
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| 213 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
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| 214 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
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| 215 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
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| 216 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
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| 217 | |
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| 218 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
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| 219 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
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| 220 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
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| 221 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
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| 222 | |
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| 223 | #define PCI_BASE_CLASS_MEMORY 0x05 |
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| 224 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
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| 225 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
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| 226 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
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| 227 | |
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| 228 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
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| 229 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
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| 230 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
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| 231 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
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| 232 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
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| 233 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
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| 234 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
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| 235 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
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| 236 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
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| 237 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
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| 238 | |
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| 239 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
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| 240 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
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| 241 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
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| 242 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
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| 243 | |
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| 244 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
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| 245 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
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| 246 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
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| 247 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
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| 248 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
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| 249 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
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| 250 | |
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| 251 | #define PCI_BASE_CLASS_INPUT 0x09 |
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| 252 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
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| 253 | #define PCI_CLASS_INPUT_PEN 0x0901 |
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| 254 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
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| 255 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
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| 256 | |
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| 257 | #define PCI_BASE_CLASS_DOCKING 0x0a |
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| 258 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
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| 259 | #define PCI_CLASS_DOCKING_OTHER 0x0a01 |
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| 260 | |
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| 261 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
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| 262 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
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| 263 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
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| 264 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
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| 265 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
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| 266 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
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| 267 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
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| 268 | |
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| 269 | #define PCI_BASE_CLASS_SERIAL 0x0c |
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| 270 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
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| 271 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
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| 272 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
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| 273 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
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| 274 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
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| 275 | |
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| 276 | #define PCI_CLASS_OTHERS 0xff |
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| 277 | |
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| 278 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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| 279 | #define PCI_MULTI_FUNCTION 0x80 |
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| 280 | |
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| 281 | #define PCI_MAX_DEVICES 32 |
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| 282 | #define PCI_MAX_FUNCTIONS 8 |
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| 283 | |
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| 284 | #include <pci/access.h> |
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| 285 | |
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| 286 | #ifdef __cplusplus |
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| 287 | extern "C" { |
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| 288 | #endif |
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| 289 | |
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| 290 | /* The PCI Library have the following build time configuration options. It is |
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| 291 | * up to the BSP header file (bsp.h) to set options properly. |
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| 292 | * |
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| 293 | * BSP_PCI_BIG_ENDIAN - Access inline routines will be for a big-endian PCI |
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| 294 | * bus, if not defined the routines will assume that |
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| 295 | * PCI is as the standard defines: little-endian. |
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| 296 | * |
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| 297 | * Note that drivers may be run-time configurable, |
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| 298 | * meaning that they may adopt to either big-endian or |
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| 299 | * little-endian PCI bus, the host driver or BSP may |
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| 300 | * detect endianness during run-time. |
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| 301 | */ |
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| 302 | |
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| 303 | /* Error return values */ |
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| 304 | enum { |
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| 305 | PCISTS_ERR = -1, /* Undefined Error */ |
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| 306 | PCISTS_OK = 0, |
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| 307 | PCISTS_EINVAL = 1, /* Bad input arguments */ |
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| 308 | PCISTS_MSTABRT = 2, /* CFG space access error (can be ignored) */ |
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| 309 | }; |
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| 310 | |
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| 311 | /* PCI System type can be used to determine system for drivers. Normally |
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| 312 | * the system is Host, but the peripheral configuration library also supports |
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| 313 | * being PCI peripheral not allowed to access configuration space. |
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| 314 | * |
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| 315 | * The active configuration Library set this variable. |
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| 316 | */ |
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| 317 | enum { |
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| 318 | PCI_SYSTEM_NONE = 0, |
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| 319 | PCI_SYSTEM_HOST = 1, |
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| 320 | PCI_SYSTEM_PERIPHERAL = 2, |
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| 321 | }; |
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| 322 | extern int pci_system_type; |
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| 323 | |
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| 324 | /* PCI Bus Endianness. The PCI specification is little endian, however on some |
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| 325 | * embedded systems (AT697-LEON2 for example) the PCI bus is defined as big |
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| 326 | * endian (non-standard) in order to avoid byte-twisting. |
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| 327 | */ |
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| 328 | enum { |
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| 329 | PCI_LITTLE_ENDIAN = 0, |
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| 330 | PCI_BIG_ENDIAN = 1, |
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| 331 | }; |
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| 332 | extern int pci_endian; |
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| 333 | |
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| 334 | /* Return the number of PCI busses in the system */ |
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| 335 | extern int pci_bus_count(void); |
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| 336 | |
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| 337 | /* Scan the PCI bus and print the PCI device/functions/bridges and their |
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| 338 | * current resources and size to the system console. |
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| 339 | */ |
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| 340 | extern void pci_print(void); |
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| 341 | |
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| 342 | /* Print current configuration of a single PCI device by reading PCI |
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| 343 | * configuration space |
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| 344 | */ |
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| 345 | extern void pci_print_dev(pci_dev_t dev); |
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| 346 | extern void pci_print_device(int bus, int slot, int function); |
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| 347 | |
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| 348 | /*** PCI Configuration Space direct access routines ***/ |
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| 349 | |
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| 350 | /* Function iterates over all PCI buses/devices/functions and calls |
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| 351 | * func(PCIDEV,arg) for each present device. The iteration is stopped if |
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| 352 | * func() returns non-zero result the same result is returned. As long |
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| 353 | * as func() returns zero the function will keep on iterating, when all |
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| 354 | * devices has been processed the function return zero. |
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| 355 | * |
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| 356 | * The function iterates over all devices/functions on all buses by accessing |
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| 357 | * configuration space directly (PCI RAM data structures not used). This |
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| 358 | * function is valid to call after PCI buses have been enumrated. |
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| 359 | */ |
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| 360 | extern int pci_for_each(int (*func)(pci_dev_t, void*), void *arg); |
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| 361 | |
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| 362 | /* Get PCI Configuration space BUS|SLOT|FUNC for a device matching PCI |
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| 363 | * Vendor, Device and instance number 'index'. |
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| 364 | * |
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| 365 | * Return Values |
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| 366 | * -1 pci_find_dev did not find a device matching the criterion. |
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| 367 | * 0 device was found, *pdev was updated with the device's BUS|SLOT|FUNC |
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| 368 | */ |
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| 369 | extern int pci_find(uint16_t ven, uint16_t dev, int index, pci_dev_t *pdev); |
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| 370 | |
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| 371 | #ifdef __cplusplus |
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| 372 | } |
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| 373 | #endif |
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| 374 | |
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| 375 | #endif /* __PCI_H__ */ |
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