1 | /* |
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2 | * Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org>. |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | /* |
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28 | * Debugger for RTEMS. |
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29 | */ |
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30 | |
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31 | #ifndef _RTEMS_DEBUGGER_TARGET_h |
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32 | #define _RTEMS_DEBUGGER_TARGET_h |
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33 | |
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34 | #include <setjmp.h> |
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35 | |
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36 | #include <rtems/rtems-debugger.h> |
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37 | |
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38 | #include "rtems-debugger-threads.h" |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif /* __cplusplus */ |
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43 | |
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44 | /* |
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45 | * Software breakpoint block size. |
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46 | */ |
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47 | #define RTEMS_DEBUGGER_TARGET_SWBREAK_NUM 64 |
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48 | |
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49 | /** |
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50 | * Target capabilities mask. |
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51 | */ |
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52 | #define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK (1 << 0) |
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53 | #define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK (1 << 1) |
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54 | #define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH (1 << 2) |
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55 | /* |
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56 | * This target capability indicates that the target implementation uses a pure |
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57 | * software break implementation which must not allow breakpoints to be |
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58 | * inserted before the actual switch to the thread, be it in interrupt context |
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59 | * or otherwise. Such implementations must necessarily implement a thread |
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60 | * switch hook and interrupt hooks to handle these situations. |
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61 | */ |
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62 | #define RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK (1 << 3) |
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63 | |
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64 | /** |
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65 | * Types of hardware breakpoints. |
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66 | */ |
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67 | typedef enum rtems_debugger_target_watchpoint |
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68 | { |
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69 | rtems_debugger_target_hw_read, |
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70 | rtems_debugger_target_hw_write, |
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71 | rtems_debugger_target_hw_read_write, |
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72 | rtems_debugger_target_hw_execute |
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73 | } rtems_debugger_target_watchpoint; |
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74 | |
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75 | /** |
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76 | * Target exception actions. |
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77 | */ |
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78 | typedef enum rtems_debugger_target_exc_action |
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79 | { |
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80 | rtems_debugger_target_exc_consumed, /*<< The exception has been consumed. */ |
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81 | rtems_debugger_target_exc_cascade, /*<< Cascade to a previous handler. */ |
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82 | rtems_debugger_target_exc_step, /*<< Step an instruction. */ |
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83 | } rtems_debugger_target_exc_action; |
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84 | |
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85 | /** |
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86 | * Memory breakpoint. We use thumb mode BKPT which is 2 bytes. |
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87 | */ |
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88 | #define RTEMS_DEBUGGER_TARGET_SWBREAK_MAX_SIZE (4) |
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89 | typedef struct rtems_debugger_target_swbreak { |
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90 | void* address; |
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91 | uint8_t contents[RTEMS_DEBUGGER_TARGET_SWBREAK_MAX_SIZE]; |
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92 | } rtems_debugger_target_swbreak; |
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93 | |
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94 | /** |
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95 | * The target data. |
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96 | * |
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97 | * reg_offset: Table of size_t offset of a register in the register |
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98 | * table. The table has one more entry than reg_num where |
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99 | * the last entry is the size of the register table. |
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100 | */ |
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101 | typedef struct rtems_debugger_target { |
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102 | int capabilities; /*<< The capabilities to report. */ |
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103 | size_t reg_num; /*<< The number of registers. */ |
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104 | const size_t* reg_offset; /*<< The reg offsettable, len = reg_num + 1. */ |
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105 | const uint8_t* breakpoint; /*<< The breakpoint instruction(s). */ |
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106 | size_t breakpoint_size; /*<< The breakpoint size. */ |
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107 | rtems_debugger_block swbreaks; /*<< The software breakpoint block. */ |
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108 | bool memory_access; /*<< Accessing target memory. */ |
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109 | jmp_buf access_return; /*<< Return from an access fault. */ |
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110 | } rtems_debugger_target; |
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111 | |
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112 | /** |
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113 | * Create the target. |
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114 | */ |
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115 | extern int rtems_debugger_target_create(void); |
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116 | |
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117 | /** |
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118 | * Destroy the target. |
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119 | */ |
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120 | extern int rtems_debugger_target_destroy(void); |
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121 | |
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122 | /** |
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123 | * Configure the target. This is architecture specific. |
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124 | */ |
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125 | extern int rtems_debugger_target_configure(rtems_debugger_target* target); |
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126 | |
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127 | /** |
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128 | * Enable the target. |
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129 | */ |
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130 | extern int rtems_debugger_target_enable(void); |
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131 | |
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132 | /** |
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133 | * Disable the target. |
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134 | */ |
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135 | extern int rtems_debugger_target_disable(void); |
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136 | |
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137 | /** |
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138 | * Return the capabilities mask for the target. |
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139 | */ |
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140 | extern uint32_t rtems_debugger_target_capabilities(void); |
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141 | |
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142 | /** |
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143 | * Return the number of regisers. |
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144 | */ |
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145 | extern size_t rtems_debugger_target_reg_num(void); |
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146 | |
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147 | /** |
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148 | * Return the offset of a register in the register table. |
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149 | */ |
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150 | extern size_t rtems_debugger_target_reg_size(size_t reg); |
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151 | |
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152 | /** |
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153 | * Return the offset of a register in the register table. |
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154 | */ |
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155 | extern size_t rtems_debugger_target_reg_offset(size_t reg); |
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156 | |
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157 | /** |
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158 | * Return the size of register table. |
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159 | */ |
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160 | extern size_t rtems_debugger_target_reg_table_size(void); |
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161 | |
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162 | /** |
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163 | * Read the regosters. |
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164 | */ |
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165 | extern int rtems_debugger_target_read_regs(rtems_debugger_thread* thread); |
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166 | |
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167 | /** |
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168 | * Write the regosters. |
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169 | */ |
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170 | extern int rtems_debugger_target_write_regs(rtems_debugger_thread* thread); |
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171 | |
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172 | /** |
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173 | * Return the thread's program counter (PC). |
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174 | */ |
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175 | extern uintptr_t rtems_debugger_target_reg_pc(rtems_debugger_thread* thread); |
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176 | |
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177 | /** |
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178 | * Return the frame's program counter (PC). |
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179 | */ |
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180 | extern uintptr_t rtems_debugger_target_frame_pc(CPU_Exception_frame* frame); |
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181 | |
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182 | /** |
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183 | * Return the thread's stack pointer (SP). |
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184 | */ |
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185 | extern uintptr_t rtems_debugger_target_reg_sp(rtems_debugger_thread* thread); |
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186 | |
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187 | /** |
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188 | * Return the thread's TCB stack pointer (SP). |
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189 | */ |
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190 | extern uintptr_t rtems_debugger_target_tcb_sp(rtems_debugger_thread* thread); |
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191 | |
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192 | /** |
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193 | * The thread is stepping. Setup the thread to step an instruction. |
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194 | */ |
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195 | extern int rtems_debugger_target_thread_stepping(rtems_debugger_thread* thread); |
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196 | |
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197 | /** |
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198 | * Return the signal for the exception. |
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199 | */ |
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200 | extern int rtems_debugger_target_exception_to_signal(CPU_Exception_frame* frame); |
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201 | |
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202 | /** |
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203 | * Print the target exception registers. |
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204 | */ |
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205 | extern void rtems_debugger_target_exception_print(CPU_Exception_frame* frame); |
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206 | |
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207 | /** |
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208 | * Software breakpoints. These are also referred to as memory breakpoints. |
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209 | */ |
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210 | extern int rtems_debugger_target_swbreak_control(bool insert, |
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211 | uintptr_t addr, |
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212 | DB_UINT kind); |
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213 | |
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214 | /** |
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215 | * Insert software breakpoints into the memory. |
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216 | */ |
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217 | extern int rtems_debugger_target_swbreak_insert(void); |
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218 | |
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219 | /** |
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220 | * Remove software breakpoints from the memory. |
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221 | */ |
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222 | extern int rtems_debugger_target_swbreak_remove(void); |
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223 | |
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224 | /** |
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225 | * Insert hardware breakpoints into the hardware. |
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226 | */ |
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227 | extern int rtems_debugger_target_hwbreak_insert(void); |
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228 | |
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229 | /** |
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230 | * Remove hardware breakpoints from the hardware. |
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231 | */ |
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232 | extern int rtems_debugger_target_hwbreak_remove(void); |
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233 | |
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234 | /** |
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235 | * Hardware breakpoints. |
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236 | */ |
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237 | extern int rtems_debugger_target_hwbreak_control(rtems_debugger_target_watchpoint type, |
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238 | bool insert, |
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239 | uintptr_t addr, |
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240 | DB_UINT kind); |
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241 | |
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242 | /** |
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243 | * Target exception processor. |
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244 | */ |
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245 | extern rtems_debugger_target_exc_action |
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246 | rtems_debugger_target_exception(CPU_Exception_frame* frame); |
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247 | |
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248 | /** |
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249 | * See if the thread is an exception thread. |
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250 | */ |
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251 | extern void rtems_debugger_target_exception_thread(rtems_debugger_thread* thread); |
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252 | |
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253 | /** |
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254 | * If the thread is an exception thread, resume it. |
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255 | */ |
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256 | extern void rtems_debugger_target_exception_thread_resume(rtems_debugger_thread* thread); |
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257 | |
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258 | /** |
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259 | * Target instruction cache sync. This depends on the target but it normally |
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260 | * means a data cache flush and an instruction cache invalidate. |
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261 | */ |
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262 | extern int rtems_debugger_target_cache_sync(rtems_debugger_target_swbreak* swbreak); |
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263 | |
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264 | /** |
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265 | * Start a target memory access. If 0 is return the access can proceed and if |
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266 | * -1 is return the access has failed. |
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267 | */ |
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268 | extern int rtems_debugger_target_start_memory_access(void); |
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269 | |
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270 | /** |
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271 | * End a target memory access. |
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272 | */ |
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273 | extern void rtems_debugger_target_end_memory_access(void); |
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274 | |
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275 | /** |
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276 | * Is this a target memory access? |
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277 | */ |
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278 | extern bool rtems_debugger_target_is_memory_access(void); |
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279 | |
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280 | #ifdef __cplusplus |
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281 | } |
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282 | #endif /* __cplusplus */ |
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283 | |
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284 | |
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285 | #endif |
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