1 | /* |
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2 | * Copyright (c) 2016 Chris Johns <chrisj@rtems.org>. |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #define TARGET_DEBUG 1 |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <errno.h> |
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34 | #include <inttypes.h> |
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35 | #include <stdlib.h> |
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36 | |
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37 | #include <rtems.h> |
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38 | #include <rtems/score/threadimpl.h> |
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39 | |
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40 | #include "rtems-debugger-target.h" |
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41 | #include "rtems-debugger-threads.h" |
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42 | |
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43 | /* |
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44 | * Hardware breakpoints. Limited by hardware |
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45 | */ |
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46 | #define RTEMS_DEBUGGER_HWBREAK_NUM 4 |
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47 | |
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48 | /* |
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49 | * Number of registers. |
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50 | */ |
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51 | #define RTEMS_DEBUGGER_NUMREGS 16 |
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52 | |
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53 | /* |
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54 | * Number of bytes per register. |
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55 | */ |
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56 | #define RTEMS_DEBUGGER_REGBYTES 4 |
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57 | |
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58 | /* |
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59 | * Number of bytes of registers. |
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60 | */ |
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61 | #define RTEMS_DEBUGGER_NUMREGBYTES \ |
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62 | (RTEMS_DEBUGGER_NUMREGS * RTEMS_DEBUGGER_REGBYTES) |
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63 | |
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64 | /* |
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65 | * Debugger registers layout. |
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66 | */ |
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67 | #define REG_EAX 0 |
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68 | #define REG_ECX 1 |
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69 | #define REG_EDX 2 |
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70 | #define REG_EBX 3 |
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71 | #define REG_ESP 4 |
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72 | #define REG_EBP 5 |
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73 | #define REG_ESI 6 |
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74 | #define REG_EDI 7 |
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75 | #define REG_PC 8 |
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76 | #define REG_EIP REG_PC |
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77 | #define REG_PS 9 |
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78 | #define REG_EFLAGS REG_PS |
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79 | #define REG_CS 10 |
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80 | #define REG_SS 11 |
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81 | #define REG_DS 12 |
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82 | #define REG_ES 13 |
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83 | #define REG_FS 14 |
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84 | #define REG_GS 15 |
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85 | |
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86 | /** |
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87 | * The int 3 opcode. |
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88 | */ |
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89 | #define TARGET_BKPT 0xcc |
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90 | |
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91 | static const uint8_t breakpoint[1] = { TARGET_BKPT }; |
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92 | |
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93 | /* |
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94 | * Get a copy of a register. |
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95 | */ |
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96 | #define GET_REG(_r, _v) asm volatile("pushl %%" #_r "; popl %0" : "=rm" (_v)) |
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97 | |
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98 | /* |
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99 | * Get a copy of a segment register. |
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100 | */ |
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101 | #define GET_SEG_REG(_r, _v) \ |
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102 | do { \ |
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103 | int _i; \ |
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104 | GET_REG(_r, _i); \ |
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105 | _v = _i & 0xffff; \ |
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106 | } while (0) |
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107 | |
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108 | /** |
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109 | * Target lock. |
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110 | */ |
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111 | RTEMS_INTERRUPT_LOCK_DEFINE(static, target_lock, "target_lock") |
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112 | |
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113 | /** |
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114 | * The orginal exception handler. |
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115 | */ |
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116 | static void (*orig_currentExcHandler)(CPU_Exception_frame* frame); |
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117 | |
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118 | #if TARGET_DEBUG |
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119 | #include <rtems/bspIo.h> |
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120 | static void target_printk(const char* format, ...) RTEMS_PRINTFLIKE(1, 2); |
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121 | static void |
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122 | target_printk(const char* format, ...) |
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123 | { |
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124 | va_list ap; |
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125 | va_start(ap, format); |
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126 | vprintk(format, ap); |
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127 | va_end(ap); |
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128 | } |
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129 | #else |
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130 | #define target_printk(_fmt, ...) |
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131 | #endif |
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132 | |
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133 | #if TODO |
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134 | /** |
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135 | * Target description. |
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136 | */ |
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137 | static const char* const target_xml = |
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138 | "<?xml version=\"1.0\"> \ |
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139 | <!DOCTYPE target SYSTEM \"gdb-target.dtd\"> \ |
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140 | <target version=\"1.0\"> \ |
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141 | <architecture>i386</architecture> \ |
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142 | <xi:include href=\"32bit-core.xml\"/> \ |
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143 | <xi:include href=\"32bit-sse.xml\"/> \ |
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144 | </target>"; |
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145 | #endif |
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146 | |
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147 | int |
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148 | rtems_debugger_target_configure(rtems_debugger_target* target) |
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149 | { |
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150 | target->capabilities = (RTEMS_DEBUGGER_TARGET_CAP_SWBREAK); |
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151 | target->reg_num = RTEMS_DEBUGGER_NUMREGS; |
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152 | target->reg_size = sizeof(uint32_t); |
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153 | target->breakpoint = &breakpoint[0]; |
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154 | target->breakpoint_size = sizeof(breakpoint); |
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155 | return 0; |
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156 | } |
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157 | |
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158 | static void |
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159 | target_exception(CPU_Exception_frame* frame) |
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160 | { |
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161 | target_printk("[} frame = %08lx sig=%d (%lx)\n", |
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162 | (uint32_t) frame, |
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163 | rtems_debugger_target_exception_to_signal(frame), |
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164 | frame->idtIndex); |
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165 | target_printk("[} EAX = %" PRIx32 " EBX = %" PRIx32 \ |
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166 | " ECX = %" PRIx32 " EDX = %" PRIx32 "\n", |
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167 | frame->eax, frame->ebx, frame->ecx, frame->edx); |
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168 | target_printk("[} ESI = %" PRIx32 " EDI = %" PRIx32 \ |
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169 | " EBP = %" PRIx32 " ESP = %" PRIx32 "\n", |
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170 | frame->esi, frame->edi, frame->ebp, frame->esp0); |
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171 | target_printk("[} EIP = %" PRIx32"\n", frame->eip); |
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172 | |
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173 | frame->eflags &= ~EFLAGS_TRAP; |
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174 | |
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175 | switch (rtems_debugger_target_exception(frame)) { |
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176 | case rtems_debugger_target_exc_consumed: |
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177 | default: |
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178 | break; |
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179 | case rtems_debugger_target_exc_step: |
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180 | frame->eflags |= EFLAGS_TRAP; |
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181 | break; |
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182 | case rtems_debugger_target_exc_cascade: |
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183 | orig_currentExcHandler(frame); |
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184 | break; |
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185 | } |
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186 | } |
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187 | |
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188 | int |
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189 | rtems_debugger_target_enable(void) |
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190 | { |
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191 | rtems_interrupt_lock_context lock_context; |
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192 | rtems_interrupt_lock_acquire(&target_lock, &lock_context); |
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193 | if (orig_currentExcHandler == NULL) { |
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194 | orig_currentExcHandler = _currentExcHandler; |
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195 | _currentExcHandler = target_exception; |
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196 | } |
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197 | rtems_interrupt_lock_release(&target_lock, &lock_context); |
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198 | return 0; |
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199 | } |
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200 | |
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201 | int |
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202 | rtems_debugger_target_disable(void) |
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203 | { |
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204 | rtems_interrupt_lock_context lock_context; |
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205 | rtems_interrupt_lock_acquire(&target_lock, &lock_context); |
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206 | if (orig_currentExcHandler != NULL) |
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207 | _currentExcHandler = orig_currentExcHandler; |
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208 | rtems_interrupt_lock_release(&target_lock, &lock_context); |
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209 | return 0; |
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210 | } |
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211 | |
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212 | int |
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213 | rtems_debugger_target_read_regs(rtems_debugger_thread* thread) |
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214 | { |
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215 | if (!rtems_debugger_thread_flag(thread, |
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216 | RTEMS_DEBUGGER_THREAD_FLAG_REG_VALID)) { |
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217 | uint32_t* regs = &thread->registers[0]; |
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218 | size_t i; |
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219 | |
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220 | for (i = 0; i < rtems_debugger_target_reg_num(); ++i) |
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221 | regs[i] = 0xdeaddead; |
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222 | |
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223 | if (thread->frame) { |
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224 | CPU_Exception_frame* frame = thread->frame; |
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225 | regs[REG_EAX] = frame->eax; |
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226 | regs[REG_ECX] = frame->ecx; |
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227 | regs[REG_EDX] = frame->edx; |
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228 | regs[REG_EBX] = frame->ebx; |
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229 | regs[REG_ESP] = frame->esp0; |
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230 | regs[REG_EBP] = frame->ebp; |
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231 | regs[REG_ESI] = frame->esi; |
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232 | regs[REG_EDI] = frame->edi; |
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233 | regs[REG_EIP] = frame->eip; |
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234 | regs[REG_EFLAGS] = frame->eflags; |
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235 | regs[REG_CS] = frame->cs; |
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236 | |
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237 | /* |
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238 | * Get the signal from the frame. |
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239 | */ |
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240 | thread->signal = rtems_debugger_target_exception_to_signal(frame); |
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241 | } |
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242 | else { |
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243 | regs[REG_EBX] = thread->tcb->Registers.ebx; |
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244 | regs[REG_ESI] = thread->tcb->Registers.esi; |
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245 | regs[REG_EDI] = thread->tcb->Registers.edi; |
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246 | regs[REG_EFLAGS] = thread->tcb->Registers.eflags; |
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247 | regs[REG_ESP] = (intptr_t) thread->tcb->Registers.esp; |
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248 | regs[REG_EBP] = (intptr_t) thread->tcb->Registers.ebp; |
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249 | regs[REG_EIP] = *((DB_UINT*) thread->tcb->Registers.esp); |
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250 | regs[REG_EAX] = (intptr_t) thread; |
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251 | |
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252 | GET_SEG_REG(CS, regs[REG_CS]); |
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253 | |
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254 | /* |
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255 | * Blocked threads have no signal. |
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256 | */ |
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257 | thread->signal = 0; |
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258 | } |
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259 | |
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260 | GET_SEG_REG(SS, regs[REG_SS]); |
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261 | GET_SEG_REG(DS, regs[REG_DS]); |
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262 | GET_SEG_REG(ES, regs[REG_ES]); |
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263 | GET_SEG_REG(FS, regs[REG_FS]); |
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264 | GET_SEG_REG(GS, regs[REG_GS]); |
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265 | |
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266 | thread->flags |= RTEMS_DEBUGGER_THREAD_FLAG_REG_VALID; |
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267 | thread->flags &= ~RTEMS_DEBUGGER_THREAD_FLAG_REG_DIRTY; |
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268 | } |
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269 | |
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270 | return 0; |
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271 | } |
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272 | |
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273 | int |
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274 | rtems_debugger_target_write_regs(rtems_debugger_thread* thread) |
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275 | { |
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276 | if (rtems_debugger_thread_flag(thread, |
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277 | RTEMS_DEBUGGER_THREAD_FLAG_REG_DIRTY)) { |
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278 | uint32_t* regs = &thread->registers[0]; |
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279 | |
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280 | /* |
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281 | * Only write to debugger controlled threads. Do not touch the registers |
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282 | * for threads blocked in the context switcher. |
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283 | */ |
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284 | if (rtems_debugger_thread_flag(thread, |
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285 | RTEMS_DEBUGGER_THREAD_FLAG_EXCEPTION)) { |
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286 | CPU_Exception_frame* frame = thread->frame; |
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287 | frame->eax = regs[REG_EAX]; |
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288 | frame->ecx = regs[REG_ECX]; |
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289 | frame->edx = regs[REG_EDX]; |
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290 | frame->ebx = regs[REG_EBX]; |
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291 | frame->esp0 = regs[REG_ESP]; |
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292 | frame->ebp = regs[REG_EBP]; |
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293 | frame->esi = regs[REG_ESI]; |
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294 | frame->edi = regs[REG_EDI]; |
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295 | frame->eip = regs[REG_EIP]; |
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296 | frame->eflags = regs[REG_EFLAGS]; |
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297 | frame->cs = regs[REG_CS]; |
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298 | } |
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299 | thread->flags &= ~RTEMS_DEBUGGER_THREAD_FLAG_REG_DIRTY; |
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300 | } |
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301 | return 0; |
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302 | } |
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303 | |
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304 | DB_UINT |
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305 | rtems_debugger_target_reg_pc(rtems_debugger_thread* thread) |
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306 | { |
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307 | int r; |
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308 | r = rtems_debugger_target_read_regs(thread); |
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309 | if (r >= 0) { |
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310 | uint32_t* regs = &thread->registers[0]; |
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311 | return regs[REG_EIP]; |
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312 | } |
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313 | return 0; |
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314 | } |
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315 | |
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316 | DB_UINT |
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317 | rtems_debugger_target_frame_pc(CPU_Exception_frame* frame) |
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318 | { |
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319 | return (DB_UINT) frame->eip; |
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320 | } |
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321 | |
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322 | DB_UINT |
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323 | rtems_debugger_target_reg_sp(rtems_debugger_thread* thread) |
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324 | { |
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325 | int r; |
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326 | r = rtems_debugger_target_read_regs(thread); |
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327 | if (r >= 0) { |
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328 | uint32_t* regs = &thread->registers[0]; |
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329 | return regs[REG_ESP]; |
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330 | } |
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331 | return 0; |
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332 | } |
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333 | |
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334 | DB_UINT |
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335 | rtems_debugger_target_tcb_sp(rtems_debugger_thread* thread) |
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336 | { |
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337 | return (DB_UINT) thread->tcb->Registers.esp; |
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338 | } |
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339 | |
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340 | int |
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341 | rtems_debugger_target_thread_stepping(rtems_debugger_thread* thread) |
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342 | { |
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343 | if (rtems_debugger_thread_flag(thread, |
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344 | (RTEMS_DEBUGGER_THREAD_FLAG_STEP | |
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345 | RTEMS_DEBUGGER_THREAD_FLAG_STEPPING))) { |
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346 | CPU_Exception_frame* frame = thread->frame; |
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347 | /* |
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348 | * Single step instructions with interrupts masked to avoid stepping into |
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349 | * an interrupt handler. |
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350 | */ |
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351 | if ((frame->eflags & EFLAGS_INTR_ENABLE) == 0) |
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352 | thread->flags |= RTEMS_DEBUGGER_THREAD_FLAG_INTS_DISABLED; |
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353 | else |
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354 | frame->eflags &= ~EFLAGS_INTR_ENABLE; |
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355 | frame->eflags |= EFLAGS_TRAP; |
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356 | } |
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357 | return 0; |
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358 | } |
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359 | |
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360 | int |
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361 | rtems_debugger_target_exception_to_signal(CPU_Exception_frame* frame) |
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362 | { |
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363 | int sig = RTEMS_DEBUGGER_SIGNAL_HUP; |
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364 | switch (frame->idtIndex) { |
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365 | case 1: /* debug exception */ |
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366 | case 3: /* breakpoint int3 */ |
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367 | sig = RTEMS_DEBUGGER_SIGNAL_TRAP; |
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368 | break; |
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369 | case 4: /* int overflow */ |
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370 | case 5: /* out-of-bounds */ |
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371 | sig = RTEMS_DEBUGGER_SIGNAL_URG; |
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372 | break; |
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373 | case 6: /* invalid opcode */ |
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374 | sig = RTEMS_DEBUGGER_SIGNAL_ILL; |
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375 | break; |
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376 | case 8: /* double fault */ |
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377 | case 16: /* fp error */ |
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378 | sig = RTEMS_DEBUGGER_SIGNAL_EMT; |
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379 | break; |
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380 | case 0: /* divide by zero */ |
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381 | case 7: /* FPU not avail. */ |
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382 | sig = RTEMS_DEBUGGER_SIGNAL_FPE; |
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383 | break; |
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384 | case 9: /* i387 seg overr. */ |
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385 | case 10: /* Invalid TSS */ |
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386 | case 11: /* seg. not pres. */ |
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387 | case 12: /* stack except. */ |
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388 | case 13: /* general prot. */ |
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389 | case 14: /* page fault */ |
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390 | case 17: /* alignment check */ |
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391 | sig = RTEMS_DEBUGGER_SIGNAL_SEGV; |
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392 | break; |
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393 | case 2: /* NMI */ |
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394 | case 18: /* machine check */ |
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395 | sig = RTEMS_DEBUGGER_SIGNAL_BUS; |
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396 | break; |
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397 | default: |
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398 | break; |
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399 | } |
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400 | return sig; |
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401 | } |
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402 | |
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403 | int |
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404 | rtems_debugger_target_hwbreak_insert(void) |
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405 | { |
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406 | /* |
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407 | * Do nothing, load on exit of the exception handler. |
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408 | */ |
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409 | return 0; |
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410 | } |
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411 | |
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412 | int |
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413 | rtems_debugger_target_hwbreak_remove(void) |
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414 | { |
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415 | return 0; |
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416 | } |
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417 | |
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418 | int |
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419 | rtems_debugger_target_hwbreak_control(rtems_debugger_target_watchpoint wp, |
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420 | bool insert, |
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421 | DB_UINT addr, |
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422 | DB_UINT kind) |
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423 | { |
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424 | /* |
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425 | * To do. |
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426 | */ |
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427 | return 0; |
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428 | } |
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429 | |
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430 | int |
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431 | rtems_debugger_target_cache_sync(rtems_debugger_target_swbreak* swbreak) |
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432 | { |
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433 | /* |
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434 | * Nothing to do on an i386. |
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435 | */ |
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436 | return 0; |
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437 | } |
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