4.104.114.84.95
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[4d3017a] | 1 | /** |
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| 2 | * @file rtems/zilog/z8530.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[28a4b1d] | 6 | * This include file defines information related to a Zilog Z8530 |
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| 7 | * SCC Chip. It is a IO mapped part. |
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| 8 | * |
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[08311cc3] | 9 | * COPYRIGHT (c) 1989-1999. |
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[28a4b1d] | 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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[98e4ebf5] | 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[0eae36c7] | 14 | * http://www.rtems.com/license/LICENSE. |
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[28a4b1d] | 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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[7945944] | 19 | #ifndef _RTEMS_ZILOG_Z8530_H |
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| 20 | #define _RTEMS_ZILOG_Z8530_H |
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[28a4b1d] | 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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| 26 | /* macros */ |
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| 27 | |
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[83c5fc1] | 28 | #define VOL8( ptr ) ((volatile uint8_t *)(ptr)) |
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[28a4b1d] | 29 | |
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| 30 | #define Z8x30_STATE0 ( z8530 ) \ |
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| 31 | { char *garbage; \ |
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| 32 | (garbage) = *(VOL8(z8530)) \ |
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| 33 | } |
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| 34 | |
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| 35 | #define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ |
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| 36 | *(VOL8(z8530)) = (reg); \ |
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| 37 | *(VOL8(z8530)) = (data) |
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| 38 | |
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| 39 | #define Z8x30_READ_CONTROL( z8530, reg, data ) \ |
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| 40 | *(VOL8(z8530)) = (reg); \ |
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| 41 | (data) = *(VOL8(z8530)) |
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| 42 | |
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| 43 | #define Z8x30_WRITE_DATA( z8530, data ) \ |
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| 44 | *(VOL8(z8530)) = (data); |
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| 45 | |
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| 46 | #define Z8x30_READ_DATA( z8530, data ) \ |
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| 47 | (data) = *(VOL8(z8530)); |
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| 48 | |
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| 49 | |
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| 50 | /* RR_0 Bit Definitions */ |
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| 51 | |
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| 52 | #define RR_0_TX_BUFFER_EMPTY 0x04 |
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| 53 | #define RR_0_RX_DATA_AVAILABLE 0x01 |
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| 54 | |
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| 55 | /* read registers */ |
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| 56 | |
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| 57 | #define RR_0 0x00 |
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| 58 | #define RR_1 0x01 |
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| 59 | #define RR_2 0x02 |
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| 60 | #define RR_3 0x03 |
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| 61 | #define RR_4 0x04 |
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| 62 | #define RR_5 0x05 |
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| 63 | #define RR_6 0x06 |
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| 64 | #define RR_7 0x07 |
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| 65 | #define RR_8 0x08 |
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| 66 | #define RR_9 0x09 |
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| 67 | #define RR_10 0x0A |
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| 68 | #define RR_11 0x0B |
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| 69 | #define RR_12 0x0C |
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| 70 | #define RR_13 0x0D |
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| 71 | #define RR_14 0x0E |
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| 72 | #define RR_15 0x0F |
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| 73 | |
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| 74 | /* write registers */ |
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| 75 | |
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| 76 | #define WR_0 0x00 |
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| 77 | #define WR_1 0x01 |
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| 78 | #define WR_2 0x02 |
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| 79 | #define WR_3 0x03 |
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| 80 | #define WR_4 0x04 |
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| 81 | #define WR_5 0x05 |
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| 82 | #define WR_6 0x06 |
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| 83 | #define WR_7 0x07 |
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| 84 | #define WR_8 0x08 |
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| 85 | #define WR_9 0x09 |
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| 86 | #define WR_10 0x0A |
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| 87 | #define WR_11 0x0B |
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| 88 | #define WR_12 0x0C |
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| 89 | #define WR_13 0x0D |
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| 90 | #define WR_14 0x0E |
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| 91 | #define WR_15 0x0F |
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| 92 | |
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| 93 | #ifdef __cplusplus |
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| 94 | } |
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| 95 | #endif |
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| 96 | |
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| 97 | #endif |
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