source: rtems/cpukit/libcsupport/include/zilog/z8036.h @ 9ab091e

4.11
Last change on this file since 9ab091e was 9ab091e, checked in by Mathew Kallada <matkallada@…>, on Dec 28, 2012 at 4:35:32 PM

Header File Doxygen Enhancement Task #2

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1/**
2 * @file rtems/zilog/z8036.h
3 *
4 * @brief Zilog Z8036 Counter/Timer/IO Chip
5 *
6 * This include file defines information related to a Zilog Z8036
7 * Counter/Timer/IO Chip.  It is a memory mapped part.
8 *
9 * @note This file shares as much as possible with the include file
10 * for the Z8536 via z8x36.h.
11 */
12
13/*
14 *  COPYRIGHT (c) 1989-2011.
15 *  On-Line Applications Research Corporation (OAR).
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *  http://www.rtems.com/license/LICENSE.
20 */
21
22#ifndef _RTEMS_ZILOG_Z8036_H
23#define _RTEMS_ZILOG_Z8036_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/* macros */
30
31#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr))
32
33#define Z8x36_STATE0 ( z8036 ) \
34  { /*char *garbage = *(Z8036(z8036))->???; */ }
35
36
37#define Z8x36_WRITE( z8036, reg, data ) \
38   (Z8036(z8036))->reg = (data)
39
40
41#define Z8x36_READ( z8036, reg, data ) \
42   (Z8036(z8036))->reg = (data)
43
44/* structures */
45
46struct z8036_map {
47/* MAIN CONTROL REGISTERS (0x00-0x07) */
48  uint8_t   MASTER_INTR;           /* Master Interrupt Ctl Reg */
49  uint8_t   MASTER_CFG;            /* Master Configuration Ctl Reg */
50  uint8_t   PORTA_VECTOR;          /* Port A - Interrupt Vector */
51  uint8_t   PORTB_VECTOR;          /* Port B - Interrupt Vector */
52  uint8_t   CNT_TMR_VECTOR;        /* Counter/Timer Interrupt Vector */
53  uint8_t   PORTC_DATA_POLARITY;   /* Port C - Data Path Polarity */
54  uint8_t   PORTC_DIRECTION;       /* Port C - Data Direction */
55  uint8_t   PORTC_SPECIAL_IO_CTL;  /* Port C - Special IO Control */
56/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */
57  uint8_t   PORTA_CMD_STATUS;      /* Port A - Command Status Reg */
58  uint8_t   PORTB_CMD_STATUS;      /* Port B - Command Status Reg */
59  uint8_t   CT1_CMD_STATUS;        /* Ctr/Timer 1 - Command Status Reg */
60  uint8_t   CT2_CMD_STATUS;        /* Ctr/Timer 2 - Command Status Reg */
61  uint8_t   CT3_CMD_STATUS;        /* Ctr/Timer 3 - Command Status Reg */
62  uint8_t   PORTA_DATA;            /* Port A - Data */
63  uint8_t   PORTB_DATA;            /* Port B - Data */
64  uint8_t   PORTC_DATA;            /* Port C - Data */
65/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */
66  uint8_t   CT1_CUR_CNT_MSB;       /* Ctr/Timer 1 - Current Count (MSB) */
67  uint8_t   CT1_CUR_CNT_LSB;       /* Ctr/Timer 1 - Current Count (LSB) */
68  uint8_t   CT2_CUR_CNT_MSB;       /* Ctr/Timer 2 - Current Count (MSB) */
69  uint8_t   CT2_CUR_CNT_LSB;       /* Ctr/Timer 2 - Current Count (LSB) */
70  uint8_t   CT3_CUR_CNT_MSB;       /* Ctr/Timer 3 - Current Count (MSB) */
71  uint8_t   CT3_CUR_CNT_LSB;       /* Ctr/Timer 3 - Current Count (LSB) */
72  uint8_t   CT1_TIME_CONST_MSB;    /* Ctr/Timer 1 - Time Constant (MSB) */
73  uint8_t   CT1_TIME_CONST_LSB;    /* Ctr/Timer 1 - Time Constant (LSB) */
74  uint8_t   CT2_TIME_CONST_MSB;    /* Ctr/Timer 2 - Time Constant (MSB) */
75  uint8_t   CT2_TIME_CONST_LSB;    /* Ctr/Timer 2 - Time Constant (LSB) */
76  uint8_t   CT3_TIME_CONST_MSB;    /* Ctr/Timer 3 - Time Constant (MSB) */
77  uint8_t   CT3_TIME_CONST_LSB;    /* Ctr/Timer 3 - Time Constant (LSB) */
78  uint8_t   CT1_MODE_SPEC;         /* Ctr/Timer 1 - Mode Specification  */
79  uint8_t   CT2_MODE_SPEC;         /* Ctr/Timer 2 - Mode Specification  */
80  uint8_t   CT3_MODE_SPEC;         /* Ctr/Timer 3 - Mode Specification  */
81  uint8_t   CURRENT_VECTOR;        /* Current Vector */
82/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */
83  uint8_t   PORTA_MODE;            /* Port A - Mode Specification  */
84  uint8_t   PORTA_HANDSHAKE;       /* Port A - Handshake Specification  */
85  uint8_t   PORTA_DATA_POLARITY;   /* Port A - Data Path Polarity */
86  uint8_t   PORTA_DIRECTION;       /* Port A - Data Direction */
87  uint8_t   PORTA_SPECIAL_IO_CTL;  /* Port A - Special IO Control */
88  uint8_t   PORTA_PATT_POLARITY;   /* Port A - Pattern Polarity */
89  uint8_t   PORTA_PATT_TRANS;      /* Port A - Pattern Transition */
90  uint8_t   PORTA_PATT_MASK;       /* Port A - Pattern Mask */
91/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */
92  uint8_t   PORTB_MODE;            /* Port B - Mode Specification  */
93  uint8_t   PORTB_HANDSHAKE;       /* Port B - Handshake Specification  */
94  uint8_t   PORTB_DATA_POLARITY;   /* Port B - Data Path Polarity */
95  uint8_t   PORTB_DIRECTION;       /* Port B - Data Direction */
96  uint8_t   PORTB_SPECIAL_IO_CTL;  /* Port B - Special IO Control */
97  uint8_t   PORTB_PATT_POLARITY;   /* Port B - Pattern Polarity */
98  uint8_t   PORTB_PATT_TRANS;      /* Port B - Pattern Transition */
99  uint8_t   PORTB_PATT_MASK;       /* Port B - Pattern Mask */
100};
101
102#ifdef __cplusplus
103}
104#endif
105
106#endif
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