[4d3017a] | 1 | /** |
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| 2 | * @file rtems/zilog/z8036.h |
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[21242c2] | 3 | * |
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[9ab091e] | 4 | * @brief Zilog Z8036 Counter/Timer/IO Chip |
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| 5 | * |
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[21242c2] | 6 | * This include file defines information related to a Zilog Z8036 |
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| 7 | * Counter/Timer/IO Chip. It is a memory mapped part. |
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| 8 | * |
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| 9 | * @note This file shares as much as possible with the include file |
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| 10 | * for the Z8536 via z8x36.h. |
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[4d3017a] | 11 | */ |
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[33c3b54d] | 12 | |
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[4d3017a] | 13 | /* |
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[21242c2] | 14 | * COPYRIGHT (c) 1989-2011. |
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[28a4b1d] | 15 | * On-Line Applications Research Corporation (OAR). |
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| 16 | * |
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[98e4ebf5] | 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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[0eae36c7] | 19 | * http://www.rtems.com/license/LICENSE. |
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[28a4b1d] | 20 | */ |
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| 21 | |
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[7945944] | 22 | #ifndef _RTEMS_ZILOG_Z8036_H |
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| 23 | #define _RTEMS_ZILOG_Z8036_H |
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[28a4b1d] | 24 | |
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| 25 | #ifdef __cplusplus |
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| 26 | extern "C" { |
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| 27 | #endif |
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| 28 | |
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| 29 | /* macros */ |
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| 30 | |
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| 31 | #define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) |
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| 32 | |
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| 33 | #define Z8x36_STATE0 ( z8036 ) \ |
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| 34 | { /*char *garbage = *(Z8036(z8036))->???; */ } |
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| 35 | |
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| 36 | |
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| 37 | #define Z8x36_WRITE( z8036, reg, data ) \ |
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| 38 | (Z8036(z8036))->reg = (data) |
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| 39 | |
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| 40 | |
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| 41 | #define Z8x36_READ( z8036, reg, data ) \ |
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| 42 | (Z8036(z8036))->reg = (data) |
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| 43 | |
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| 44 | /* structures */ |
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| 45 | |
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| 46 | struct z8036_map { |
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| 47 | /* MAIN CONTROL REGISTERS (0x00-0x07) */ |
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[83c5fc1] | 48 | uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */ |
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| 49 | uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */ |
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| 50 | uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */ |
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| 51 | uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */ |
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| 52 | uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ |
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| 53 | uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ |
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| 54 | uint8_t PORTC_DIRECTION; /* Port C - Data Direction */ |
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| 55 | uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ |
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[28a4b1d] | 56 | /* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ |
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[83c5fc1] | 57 | uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */ |
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| 58 | uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */ |
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| 59 | uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ |
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| 60 | uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ |
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| 61 | uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ |
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| 62 | uint8_t PORTA_DATA; /* Port A - Data */ |
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| 63 | uint8_t PORTB_DATA; /* Port B - Data */ |
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| 64 | uint8_t PORTC_DATA; /* Port C - Data */ |
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[28a4b1d] | 65 | /* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ |
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[83c5fc1] | 66 | uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ |
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| 67 | uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ |
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| 68 | uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ |
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| 69 | uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ |
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| 70 | uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ |
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| 71 | uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ |
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| 72 | uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ |
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| 73 | uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ |
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| 74 | uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ |
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| 75 | uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ |
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| 76 | uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ |
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| 77 | uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ |
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| 78 | uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ |
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| 79 | uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ |
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| 80 | uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ |
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| 81 | uint8_t CURRENT_VECTOR; /* Current Vector */ |
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[28a4b1d] | 82 | /* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ |
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[83c5fc1] | 83 | uint8_t PORTA_MODE; /* Port A - Mode Specification */ |
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| 84 | uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */ |
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| 85 | uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ |
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| 86 | uint8_t PORTA_DIRECTION; /* Port A - Data Direction */ |
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| 87 | uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ |
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| 88 | uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ |
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| 89 | uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */ |
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| 90 | uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */ |
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[28a4b1d] | 91 | /* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ |
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[83c5fc1] | 92 | uint8_t PORTB_MODE; /* Port B - Mode Specification */ |
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| 93 | uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */ |
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| 94 | uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ |
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| 95 | uint8_t PORTB_DIRECTION; /* Port B - Data Direction */ |
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| 96 | uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ |
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| 97 | uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ |
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| 98 | uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */ |
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| 99 | uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */ |
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[28a4b1d] | 100 | }; |
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| 101 | |
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| 102 | #ifdef __cplusplus |
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| 103 | } |
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| 104 | #endif |
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| 105 | |
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| 106 | #endif |
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