source: rtems/cpukit/itron/include/itronsys/sysmgmt.h @ 6df1f64

4.104.114.84.95
Last change on this file since 6df1f64 was 6df1f64, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jan 28, 2005 at 11:07:14 AM

New header guards.

  • Property mode set to 100644
File size: 8.8 KB
Line 
1/**
2 * @file itronsys/sysmgmt.h
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#ifndef _ITRONSYS_SYSMGMT_H
17#define _ITRONSYS_SYSMGMT_H
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  Get Version (get_ver) Structure
25 */
26
27typedef struct t_ver {
28  UH   maker;     /* vendor */
29  UH   id;        /* format number */
30  UH   spver;     /* specification version */
31  UH   prver;     /* product version */
32  UH   prno[4];   /* product control information */
33  UH   cpu;       /* CPU information */
34  UH   var;       /* variation descriptor */
35} T_VER;
36
37/*
38 *  Specific MAKER codes established as of March, 1993 are as follows.
39 *  Due to restrictions on the assignment of CPU codes described below, it is
40 *  necessary to use maker codes in the range 0x000 through 0x00ff for vendors
41 *  developing CPUs.
42 */
43
44/*
45 *  CPU defines XXX need to name the constants
46 */
47
48#if 0
49#define 0x000  /* No version (test systems, etc.) */
50#define 0x001  /* University of Tokyo */
51#define 0x009  /* FUJITSU LIMITED */
52#define 0x00a  /* Hitachi, Ltd. */
53#define 0x00b  /* Matsushita Electric Industrial Co., Ltd. */
54#define 0x00c  /* Mitsubishi Electric Corporation */
55#define 0x00d  /* NEC Corporation */
56#define 0x00e  /* Oki Electric Industry Co., Ltd. */
57#define 0x00f  /* TOSHIBA CORPORATION */
58#endif
59
60/*
61 * The above have been assigned in alphabetical order.
62 */
63
64#if 0
65#define 0x010  /* ALPS ELECTRIC CO., LTD. */
66#define 0x011  /* WACOM Co., Ltd. */
67#define 0x012  /* Personal Media Corporation */
68#define 0x101  /* OMRON CORPORATION */
69#define 0x102  /* SEIKOSHA CO., LTD. */
70#define 0x103  /* SYSTEM ALGO CO., LTD. */
71#define 0x104  /* Tokyo Computer Service Co., Ltd. */
72#define 0x105  /* YAMAHA CORPORATION */
73#define 0x106  /* MORSON JAPAN */
74#define 0x107  /* TOSHIBA INFORMATION SYSTEMS (JAPAN) CORP. */
75#define 0x108  /* Miyazaki System Planning Office */
76#define 0x109  /* Three Ace Computer Corporation */
77#endif
78
79/*
80 *  CPU Codes
81 *
82 *  Figure 47 shows the format of cpu code.  Some processors use the format
83 *  given in Figure 47(1).  The format given in Figure 47(2) is used for all
84 *  other proprietary processors.
85 *
86 *  The code assignment of the CPU1 region in the format given in Figure 47(1)
87 *  is common to ITRON and BTRON specifications.  The same number is used in
88 *  the CPU type of the standard object format of BTRON specification
89 *  operating systems implemented on a TRON-specification chip.
90 *
91 *  When using the format given in Figure 47(2) the code used for MAKER1 is
92 *  assigned by using the lower 8 bits of MAKER described in the previous
93 *  subsection.  The code assignment of CPU2 is left up to each maker.
94 *
95 *
96 *
97 *        +---------------+---------------+---------------+---------------+
98 *    (1) | 0   0   0   0   0   0   0   0 |              CPU1             |
99 *        +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
100 *        +---------------+---------------+---------------+---------------+
101 *    (2) |             MAKER1            |              CPU2             |
102 *        +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
103 *
104 *                   Figure 47 Format of cpu Returned by get_ver
105 *
106 *
107 *  Specific CPU codes established as of March, 1993 are as follows.
108 */
109
110#if 0
111/*
112 * XXX CONVERT THESE to #defines
113 */
114
115
116/*
117 *  Contents of the CPU1 field
118 */
119
120#define (0x0)   CPU unspecified, no CPU information given
121#define (0x1)   TRONCHIP32 shared
122#define (0x2)   reserved
123#define (0x3)   reserved
124#define (0x4)   reserved
125#define (0x5)   reserved (<<L1R>> TRON-specification chip)
126#define (0x6)   reserved (<<L1>> TRON-specification chip)
127#define (0x7)   reserved (TRON-specification chip supporting the
128                             LSID function)
129/* CPU vendors are unspecified for codes B'00000000 through B'00000111. */
130
131#define (0x8)  reserved
132#define (0x9)  GMICRO/100
133#define (0xa)  GMICRO/200
134#define (0xb)  GMICRO/300
135#define (0xc)  reserved
136#define (0xd)  TX1
137#define (0xe)  TX2
138#define (0xf)  reserved
139
140#define (0x10)  reserved
141#define (0x11)  reserved
142#define (0x12)  reserved
143#define (0x13)  O32
144#define (0x14)  reserved
145#define (0x15)  MN10400
146#define (0x16)  reserved
147#define (0x17)  reserved
148
149#define (0x18)  GMICRO/400
150#define (0x19)  GMICRO/500
151#define (0x1a)  reserved
152#define (0x1b-0x3f)
153                            reserved
154          * For GMICRO extended, TX series extended, and TRONCHIP64 chips.
155
156#define (0x40)   Motorola 68000
157#define (0x41)   Motorola 68010
158#define (0x42)   Motorola 68020
159#define (0x43)   Motorola 68030
160#define (0x44)   Motorola 68040
161#define -(0x40-0x4f)
162#define                       Motorola 68000 family
163#define (0x50)   National Semiconductor NS32032
164#define (0x50-0x5f)
165                              National Semiconductor NS32000 family
166#define (0x60)   Intel 8086, 8088
167#define (0x61)   Intel 80186
168#define (0x62)   Intel 80286
169#define (0x63)   Intel 80386
170#define (0x64)   Intel 80486
171#define (0x60-0x6f)
172                              Intel iAPX86 family
173
174#define (0x70-0x7f)
175                              NEC V Series
176
177#define (0x80-0xff)
178                              reserved
179#endif
180
181/*
182 *  Assigning Version Numbers
183 *
184 *  The version numbers of ITRON and uITRON specifications take the following
185 *  form.
186 *
187 *          Ver X.YY.ZZ[.WW]
188 *
189 *  where "X" represents major version number of the ITRON specification to
190 *  distinguish ITRON1, ITRON2 and uITRON 3.0 specifications.  Specific
191 *  assignment is as follows.
192 *
193 *          "X" = 1  ITRON1 specification
194 *              = 2  ITRON2 or uITRON 2.0 specification
195 *              = 3  uITRON 3.0 specification
196 *
197 *  "YY" is a number used to distinguish versions according to changes and
198 *  additions made to the specification.  After the specification is published,
199 *  this number is incremented in order "YY" = 00, 01, 02... according to
200 *  version upgrades.  The first digit of "YY" is 'A', 'B' or 'C' for draft
201 *  standard versions and test versions within the TRON Association before the
202 *  specification have been published.
203 *
204 *  The "X.YY" part of the specification version numbers is returned by spver
205 *  to get_ver system call.  The corresponding hexadecimal value is used when
206 *  "YY" includes 'A', 'B' or 'C'.
207 *
208 *  "ZZ" represents a number used to distinguish versions related to the written
209 *  style of a specification.  This number is incremented in order
210 *  "ZZ" = 00, 01, 02... when there have been changes in specification
211 *  configuration, reordering of chapters or corrections of misprints.
212 *  When a further distinction of the written style of specifications is
213 *  desired, ".WW" may be added optionally after "ZZ".  WW will be assumed
214 *  to be zero if ".WW" is omitted.
215 */
216
217/*
218 *  Reference System (ref_sys) Structure
219 */
220
221typedef struct t_rsys {
222  INT   sysstat;   /* system state */
223  /* additional information may be included depending on the implementation */
224} T_RSYS;
225
226/*
227 *  sysstat
228 */
229
230#define TSS_TSK    0   /* normal state in which dispatching is enabled during
231                          task portion execution */
232#define TSS_DDSP   1   /* state after dis_dsp has been executed during task
233                          portion execution (dispatch disabled) */
234#define TSS_LOC    3   /* state after loc_cpu has been executed during task
235                          portion execution (interrupt and dispatch disabled)
236                          */
237#define TSS_INDP   4   /* state during execution of task-independent portions
238                          (interrupt and timer handlers) */
239
240/*
241 *  Reference Configuration (ref_cfg) Structure
242 */
243
244typedef struct t_rcfg {
245  /* details concerning members are implementation dependent */
246} T_RCFG;
247
248/*
249 *  Define Service (def_svc) Structure
250 */
251
252typedef struct t_dsvc {
253  ATR   svcatr;   /* extended SVC handler attributes */
254  FP    svchdr;   /* extended SVC handler address */
255  /* additional information may be included depending on the implementation */
256} T_DSVC;
257
258/*
259 *  Define Exception (def_exc) Structure
260 */
261
262typedef struct t_dexc {
263  ATR   excatr;   /* exception handler attributes */
264  FP    exchdr;   /* exception handler address */
265  /* additional information may be included depending on the implementation */
266} T_DEXC;
267
268/*
269 *  System Management Functions
270 */
271
272/*
273 *  get_ver - Get Version Information
274 */
275
276ER get_ver(
277  T_VER *pk_ver
278);
279
280/*
281 *  ref_sys - Reference Semaphore Status
282 */
283
284ER ref_sys(
285  T_RSYS *pk_rsys
286);
287
288/*
289 *  ref_cfg - Reference Configuration Information
290 */
291
292ER ref_cfg(
293  T_RCFG *pk_rcfg
294);
295
296/*
297 *  def_svc - Define Extended SVC Handler
298 */
299
300ER def_svc(
301  FN s_fncd,
302  T_DSVC *pk_dsvc
303);
304
305/*
306 *  def_exc - Define Exception Handler
307 */
308
309ER def_exc(
310  UINT exckind,
311  T_DEXC *pk_dexc
312);
313
314
315
316
317#ifdef __cplusplus
318}
319#endif
320
321#endif
322/* end of include file */
Note: See TracBrowser for help on using the repository browser.