source: rtems/cpukit/include/rtems/score/isrlevel.h @ 21275b58

Last change on this file since 21275b58 was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/**
2 *  @file  rtems/score/isrlevel.h
3 *
4 *  @brief ISR Level Type
5 *
6 *  This include file defines the ISR Level type.  It exists to
7 *  simplify include dependencies.  It is part of the ISR Handler.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_ISR_LEVEL_h
20#define _RTEMS_SCORE_ISR_LEVEL_h
21
22#include <rtems/score/cpu.h>
23#include <rtems/score/assert.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/**
30 *  @defgroup ScoreISR ISR Handler
31 *
32 *  @ingroup Score
33 *
34 *  @addtogroup ScoreISR ISR Handler
35 */
36/**@{*/
37
38/**
39 *  The following type defines the control block used to manage
40 *  the interrupt level portion of the status register.
41 */
42typedef uint32_t   ISR_Level;
43
44/**
45 *  @brief Disables interrupts on this processor.
46 *
47 *  This macro disables all interrupts on this processor so that a critical
48 *  section of code is protected from concurrent access by interrupts of this
49 *  processor.  Disabling of interrupts disables thread dispatching on the
50 *  processor as well.
51 *
52 *  On SMP configurations other processors can enter such sections if not
53 *  protected by other means.
54 *
55 *  @param[out] _level The argument @a _level will contain the previous
56 *  interrupt mask level.
57 */
58#define _ISR_Local_disable( _level ) \
59  do { \
60    _CPU_ISR_Disable( _level ); \
61    RTEMS_COMPILER_MEMORY_BARRIER(); \
62  } while (0)
63
64/**
65 *  @brief Enables interrupts on this processor.
66 *
67 *  This macro restores the interrupt status on the processor with the
68 *  interrupt level value obtained by _ISR_Local_disable().  It is used at the end of
69 *  a critical section of code to enable interrupts so they can be processed
70 *  again.
71 *
72 *  @param[in] _level The interrupt level previously obtained by
73 *  _ISR_Local_disable().
74 */
75#define _ISR_Local_enable( _level ) \
76  do { \
77    RTEMS_COMPILER_MEMORY_BARRIER(); \
78    _CPU_ISR_Enable( _level ); \
79  } while (0)
80
81/**
82 *  @brief Temporarily enables interrupts on this processor.
83 *
84 *  This macro temporarily enables interrupts to the previous
85 *  interrupt mask level and then disables all interrupts so that
86 *  the caller can continue into the second part of a critical
87 *  section.
88 *
89 *  This routine is used to temporarily enable interrupts
90 *  during a long critical section.  It is used in long sections of
91 *  critical code when a point is reached at which interrupts can
92 *  be temporarily enabled.  Deciding where to flash interrupts
93 *  in a long critical section is often difficult and the point
94 *  must be selected with care to ensure that the critical section
95 *  properly protects itself.
96 *
97 *  @param[in] _level The interrupt level previously obtained by
98 *  _ISR_Local_disable().
99 */
100#define _ISR_Local_flash( _level ) \
101  do { \
102    RTEMS_COMPILER_MEMORY_BARRIER(); \
103    _CPU_ISR_Flash( _level ); \
104    RTEMS_COMPILER_MEMORY_BARRIER(); \
105  } while (0)
106
107/**
108 * @brief Returns true if interrupts are enabled in the specified interrupt
109 * level, otherwise returns false.
110 *
111 * @param[in] _level The ISR level.
112 *
113 * @retval true Interrupts are enabled in the interrupt level.
114 * @retval false Otherwise.
115 */
116#define _ISR_Is_enabled( _level ) \
117  _CPU_ISR_Is_enabled( _level )
118
119/**
120 *  @brief Return current interrupt level.
121 *
122 *  This routine returns the current interrupt level.
123 *
124 *  LM32 Specific Information:
125 *  XXX document implementation including references if appropriate
126 *
127 *  @retval This method returns the current level.
128 */
129#define _ISR_Get_level() \
130        _CPU_ISR_Get_level()
131
132/**
133 *  @brief Set current interrupt level.
134 *
135 *  This routine sets the current interrupt level to that specified
136 *  by @a _new_level.  The new interrupt level is effective when the
137 *  routine exits.
138 *
139 *  @param[in] _new_level contains the desired interrupt level.
140 */
141#define _ISR_Set_level( _new_level ) \
142  do { \
143    RTEMS_COMPILER_MEMORY_BARRIER();  \
144    _CPU_ISR_Set_level( _new_level ); \
145    RTEMS_COMPILER_MEMORY_BARRIER();  \
146  } while (0)
147
148/**@}*/
149
150#ifdef __cplusplus
151}
152#endif
153#endif
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