1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef _DEV_SERIAL_SC16IS752_H |
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16 | #define _DEV_SERIAL_SC16IS752_H |
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17 | |
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18 | #include <sys/ioccom.h> |
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19 | |
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20 | #include <rtems/termiostypes.h> |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif /* __cplusplus */ |
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25 | |
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26 | /** |
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27 | * @defgroup SC16IS752 SC16IS752 Serial Device Driver |
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28 | * |
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29 | * @ingroup TermiostypesSupport |
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30 | */ |
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31 | |
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32 | typedef enum { |
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33 | SC16IS752_MODE_RS232, |
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34 | |
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35 | /* Enable RS485 mode */ |
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36 | SC16IS752_MODE_RS485, |
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37 | |
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38 | /* Enable RS485 mode, enable the transmitter to control the #RTS pin */ |
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39 | SC16IS752_MODE_RS485_RTS, |
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40 | |
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41 | /* |
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42 | * Enable RS485 mode, enable the transmitter to control the #RTS pin, invert |
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43 | * RTS signal (#RTS = 1 during transmission and #RTS = 0 during reception) |
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44 | */ |
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45 | SC16IS752_MODE_RS485_RTS_INV |
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46 | } sc16is752_mode; |
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47 | |
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48 | typedef struct sc16is752_context sc16is752_context; |
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49 | |
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50 | /** |
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51 | * @brief SC16IS752 device context. |
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52 | */ |
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53 | struct sc16is752_context { |
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54 | rtems_termios_device_context base; |
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55 | |
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56 | /** |
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57 | * @brief Writes a register. |
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58 | * |
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59 | * Internal handler. |
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60 | */ |
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61 | int (*write_reg)( |
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62 | sc16is752_context *ctx, |
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63 | uint8_t addr, |
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64 | const uint8_t *data, |
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65 | size_t len |
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66 | ); |
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67 | |
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68 | /** |
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69 | * @brief Reads a register. |
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70 | * |
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71 | * Internal handler. |
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72 | */ |
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73 | int (*read_reg)( |
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74 | sc16is752_context *ctx, |
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75 | uint8_t addr, |
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76 | uint8_t *data, |
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77 | size_t len |
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78 | ); |
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79 | |
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80 | /** |
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81 | * @brief Reads two registers. |
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82 | * |
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83 | * Internal handler. |
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84 | */ |
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85 | int (*read_2_reg)( |
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86 | sc16is752_context *ctx, |
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87 | uint8_t addr_0, |
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88 | uint8_t addr_1, |
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89 | uint8_t data[2] |
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90 | ); |
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91 | |
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92 | /** |
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93 | * @brief First open. |
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94 | * |
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95 | * Internal handler. |
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96 | */ |
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97 | bool (*first_open)(sc16is752_context *ctx); |
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98 | |
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99 | /** |
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100 | * @brief Last close. |
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101 | * |
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102 | * Internal handler. |
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103 | */ |
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104 | void (*last_close)(sc16is752_context *ctx); |
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105 | |
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106 | /** |
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107 | * @brief Shall install the interrupt handler. |
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108 | * |
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109 | * Must be initialized by the user before the device creation. |
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110 | */ |
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111 | bool (*install_irq)(sc16is752_context *ctx); |
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112 | |
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113 | /** |
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114 | * @brief Shall remove the interrupt handler. |
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115 | * |
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116 | * Must be initialized by the user before the device creation. |
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117 | */ |
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118 | void (*remove_irq)(sc16is752_context *ctx); |
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119 | |
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120 | /** |
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121 | * @brief Device mode. |
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122 | * |
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123 | * Must be initialized by the user before the device creation. |
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124 | */ |
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125 | sc16is752_mode mode; |
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126 | |
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127 | /** |
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128 | * @brief Input frequency in Hertz (dependent on crystal, see XTAL1 and XTAL2 |
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129 | * pins). |
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130 | * |
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131 | * Must be initialized by the user before the device creation. |
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132 | */ |
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133 | uint32_t input_frequency; |
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134 | |
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135 | /** |
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136 | * @brief Corresponding Termios structure. |
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137 | * |
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138 | * Internal variable. |
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139 | */ |
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140 | rtems_termios_tty *tty; |
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141 | |
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142 | /** |
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143 | * @brief Shadow Interrupt Enable Register (IER). |
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144 | * |
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145 | * Internal variable. |
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146 | */ |
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147 | uint8_t ier; |
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148 | |
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149 | /** |
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150 | * @brief Characters placed into transmit FIFO. |
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151 | * |
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152 | * Internal variable. |
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153 | */ |
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154 | uint8_t tx_in_progress; |
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155 | |
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156 | /** |
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157 | * @brief Count of free characters in the transmit FIFO. |
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158 | * |
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159 | * Internal variable. |
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160 | */ |
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161 | uint8_t tx_fifo_free; |
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162 | |
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163 | /** |
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164 | * @brief Shadow Line Control Register (LCR). |
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165 | * |
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166 | * Internal variable. |
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167 | */ |
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168 | uint8_t lcr; |
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169 | |
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170 | /** |
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171 | * @brief Shadow Extra Features Control Register (EFCR). |
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172 | * |
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173 | * Internal variable. |
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174 | */ |
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175 | uint8_t efcr; |
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176 | }; |
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177 | |
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178 | /** |
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179 | * @brief SC16IS752 SPI context. |
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180 | */ |
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181 | typedef struct { |
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182 | sc16is752_context base; |
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183 | |
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184 | /** |
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185 | * @brief The SPI bus device file descriptor. |
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186 | * |
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187 | * Internal variable. |
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188 | */ |
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189 | int fd; |
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190 | |
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191 | /** |
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192 | * @brief The SPI device chip select. |
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193 | * |
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194 | * Must be initialized by the user before the call to sc16is752_spi_create(). |
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195 | */ |
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196 | uint8_t cs; |
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197 | |
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198 | /** |
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199 | * @brief The SPI bus speed in Hertz. |
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200 | * |
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201 | * Must be initialized by the user before the call to sc16is752_spi_create(). |
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202 | */ |
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203 | uint32_t speed_hz; |
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204 | |
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205 | /** |
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206 | * @brief The SPI bus device path. |
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207 | * |
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208 | * Must be initialized by the user before the call to sc16is752_spi_create(). |
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209 | */ |
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210 | const char *spi_path; |
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211 | } sc16is752_spi_context; |
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212 | |
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213 | /** |
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214 | * @brief SC16IS752 I2C context. |
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215 | */ |
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216 | typedef struct { |
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217 | sc16is752_context base; |
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218 | |
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219 | /** |
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220 | * @brief The I2C bus device file descriptor. |
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221 | * |
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222 | * Internal variable. |
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223 | */ |
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224 | int fd; |
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225 | |
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226 | /** |
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227 | * @brief The I2C bus device path. |
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228 | * |
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229 | * Must be initialized before the call to sc16is752_i2c_create(). |
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230 | */ |
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231 | const char *bus_path; |
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232 | } sc16is752_i2c_context; |
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233 | |
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234 | const rtems_termios_device_handler sc16is752_termios_handler; |
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235 | |
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236 | /** |
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237 | * @brief The interrupt handler for receive and transmit operations. |
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238 | * |
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239 | * @param[in] arg The device context. |
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240 | */ |
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241 | void sc16is752_interrupt_handler(void *arg); |
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242 | |
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243 | /** |
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244 | * @brief Creates an SPI connected SC16IS752 device. |
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245 | * |
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246 | * @param[in] ctx The SPI SC16IS752 device context. |
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247 | * @param[in] device_path The device file path for the new device. |
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248 | * |
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249 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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250 | * @retval other See rtems_termios_device_install(). |
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251 | */ |
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252 | rtems_status_code sc16is752_spi_create( |
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253 | sc16is752_spi_context *ctx, |
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254 | const char *device_path |
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255 | ); |
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256 | |
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257 | /** |
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258 | * @brief Enables the sleep mode if non-zero, otherwise disables it. |
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259 | * |
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260 | * The sleep mode is disabled by default. |
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261 | */ |
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262 | #define SC16IS752_SET_SLEEP_MODE _IOW('d', 0, int) |
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263 | |
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264 | /** |
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265 | * @brief Set the I/O Control bits except for the SRESET. |
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266 | * |
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267 | * Note that it will not be possible to set the SRESET. Otherwise the driver |
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268 | * might would have an undefined state. |
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269 | */ |
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270 | #define SC16IS752_SET_IOCONTROL _IOW('d', 1, uint8_t) |
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271 | |
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272 | /** |
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273 | * @brief Set the I/O pins direction register. |
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274 | */ |
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275 | #define SC16IS752_SET_IODIR _IOW('d', 2, uint8_t) |
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276 | |
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277 | /** |
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278 | * @brief Set the I/O pins state register. |
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279 | */ |
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280 | #define SC16IS752_SET_IOSTATE _IOW('d', 3, uint8_t) |
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281 | |
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282 | /** |
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283 | * @brief Set the EFCR register. |
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284 | */ |
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285 | #define SC16IS752_SET_EFCR _IOW('d', 4, uint8_t) |
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286 | |
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287 | /** |
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288 | * @brief Returns non-zero in case the sleep mode is enabled, otherwise zero. |
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289 | */ |
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290 | #define SC16IS752_GET_SLEEP_MODE _IOR('d', 0, int) |
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291 | |
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292 | /** |
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293 | * @brief Read the I/O Control register. |
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294 | */ |
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295 | #define SC16IS752_GET_IOCONTROL _IOR('d', 1, uint8_t) |
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296 | |
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297 | /** |
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298 | * @brief Read the I/O pins direction register. |
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299 | */ |
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300 | #define SC16IS752_GET_IODIR _IOR('d', 2, uint8_t) |
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301 | |
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302 | /** |
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303 | * @brief Read the I/O pins state register. |
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304 | */ |
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305 | #define SC16IS752_GET_IOSTATE _IOR('d', 3, uint8_t) |
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306 | |
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307 | /** |
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308 | * @brief Read the EFCR register. |
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309 | */ |
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310 | #define SC16IS752_GET_EFCR _IOR('d', 4, uint8_t) |
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311 | |
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312 | /** |
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313 | * @brief Bits for the IOCONTROL register. |
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314 | * @{ |
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315 | */ |
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316 | #define SC16IS752_IOCONTROL_SRESET (1u << 3) |
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317 | #define SC16IS752_IOCONTROL_GPIO_3_0_OR_MODEM (1u << 2) |
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318 | #define SC16IS752_IOCONTROL_GPIO_7_4_OR_MODEM (1u << 1) |
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319 | #define SC16IS752_IOCONTROL_IOLATCH (1u << 0) |
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320 | /** |
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321 | * @} |
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322 | */ |
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323 | |
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324 | #ifdef __cplusplus |
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325 | } |
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326 | #endif /* __cplusplus */ |
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327 | |
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328 | #endif /* _DEV_SERIAL_SC16IS752_H */ |
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