1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | |
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16 | #include <dev/serial/sc16is752.h> |
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17 | |
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18 | #include <sys/param.h> |
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19 | |
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20 | #include <assert.h> |
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21 | #include <stdio.h> |
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22 | #include <fcntl.h> |
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23 | |
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24 | #include <rtems/seterr.h> |
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25 | |
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26 | #include "sc16is752-regs.h" |
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27 | |
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28 | static void write_reg( |
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29 | sc16is752_context *ctx, |
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30 | uint8_t addr, |
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31 | const uint8_t *data, |
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32 | size_t len |
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33 | ) |
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34 | { |
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35 | (*ctx->write_reg)(ctx, addr, data, len); |
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36 | } |
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37 | |
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38 | static void read_reg( |
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39 | sc16is752_context *ctx, |
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40 | uint8_t addr, |
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41 | uint8_t *data, |
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42 | size_t len |
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43 | ) |
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44 | { |
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45 | (*ctx->read_reg)(ctx, addr, data, len); |
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46 | } |
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47 | |
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48 | static void read_2_reg( |
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49 | sc16is752_context *ctx, |
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50 | uint8_t addr_0, |
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51 | uint8_t addr_1, |
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52 | uint8_t data[2] |
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53 | ) |
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54 | { |
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55 | (*ctx->read_2_reg)(ctx, addr_0, addr_1, data); |
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56 | } |
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57 | |
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58 | static bool is_sleep_mode_enabled(sc16is752_context *ctx) |
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59 | { |
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60 | return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0; |
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61 | } |
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62 | |
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63 | static void set_sleep_mode(sc16is752_context *ctx, bool enable) |
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64 | { |
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65 | if (enable) { |
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66 | ctx->ier |= SC16IS752_IER_SLEEP_MODE; |
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67 | } else { |
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68 | ctx->ier &= ~SC16IS752_IER_SLEEP_MODE; |
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69 | } |
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70 | |
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71 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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72 | } |
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73 | |
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74 | static void set_mcr_dll_dlh( |
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75 | sc16is752_context *ctx, |
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76 | uint8_t mcr, |
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77 | uint32_t divisor |
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78 | ) |
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79 | { |
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80 | bool sleep_mode = is_sleep_mode_enabled(ctx); |
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81 | uint8_t dll = (uint8_t)divisor; |
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82 | uint8_t dlh = (uint8_t)(divisor >> 8); |
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83 | |
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84 | if (sleep_mode) { |
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85 | set_sleep_mode(ctx, false); |
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86 | } |
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87 | |
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88 | ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR; |
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89 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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90 | |
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91 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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92 | write_reg(ctx, SC16IS752_DLH, &dlh, 1); |
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93 | write_reg(ctx, SC16IS752_DLL, &dll, 1); |
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94 | |
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95 | ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR; |
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96 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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97 | |
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98 | if (sleep_mode) { |
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99 | set_sleep_mode(ctx, true); |
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100 | } |
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101 | } |
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102 | |
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103 | static void set_efr(sc16is752_context *ctx, uint8_t efr) |
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104 | { |
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105 | uint8_t lcr = ctx->lcr; |
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106 | |
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107 | ctx->lcr = 0xbf; |
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108 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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109 | |
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110 | write_reg(ctx, SC16IS752_EFR, &efr, 1); |
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111 | |
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112 | ctx->lcr = lcr; |
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113 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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114 | } |
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115 | |
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116 | static bool set_baud(sc16is752_context *ctx, rtems_termios_baud_t baud) |
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117 | { |
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118 | uint32_t freq = ctx->input_frequency; |
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119 | uint8_t mcr; |
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120 | uint32_t divisor; |
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121 | |
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122 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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123 | |
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124 | divisor = freq / baud / 16; |
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125 | if (divisor > 0xFFFF){ |
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126 | divisor = (freq / (4 * baud)) / 16; |
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127 | if (divisor > 0xFFFF){ |
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128 | return false; |
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129 | } else { |
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130 | mcr |= SC16IS752_MCR_PRESCALE_NEEDED; |
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131 | } |
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132 | } else { |
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133 | mcr &= ~SC16IS752_MCR_PRESCALE_NEEDED; |
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134 | } |
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135 | |
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136 | set_mcr_dll_dlh(ctx, mcr, divisor); |
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137 | return true; |
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138 | } |
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139 | |
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140 | static bool sc16is752_set_attributes( |
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141 | rtems_termios_device_context *base, |
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142 | const struct termios *term |
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143 | ) |
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144 | { |
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145 | sc16is752_context *ctx = (sc16is752_context *)base; |
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146 | bool baud_successful; |
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147 | rtems_termios_baud_t baud; |
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148 | |
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149 | ctx->lcr = 0; |
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150 | |
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151 | baud = rtems_termios_baud_to_number(term->c_ospeed); |
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152 | baud_successful = set_baud(ctx, baud); |
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153 | if (!baud_successful){ |
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154 | return false; |
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155 | } |
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156 | |
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157 | if ((term->c_cflag & CREAD) == 0){ |
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158 | ctx->efcr |= SC16IS752_EFCR_RX_DISABLE; |
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159 | } else { |
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160 | ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE; |
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161 | } |
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162 | |
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163 | write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1); |
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164 | |
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165 | switch (term->c_cflag & CSIZE) { |
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166 | case CS5: |
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167 | ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT; |
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168 | break; |
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169 | case CS6: |
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170 | ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT; |
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171 | break; |
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172 | case CS7: |
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173 | ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT; |
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174 | break; |
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175 | case CS8: |
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176 | ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT; |
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177 | break; |
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178 | } |
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179 | |
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180 | if ((term->c_cflag & PARENB) != 0){ |
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181 | if ((term->c_cflag & PARODD) != 0) { |
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182 | ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY; |
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183 | } else { |
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184 | ctx->lcr |= SC16IS752_LCR_EVEN_PARITY; |
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185 | } |
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186 | } else { |
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187 | ctx->lcr &= ~SC16IS752_LCR_SET_PARITY; |
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188 | } |
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189 | |
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190 | if ((term->c_cflag & CSTOPB) != 0) { |
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191 | ctx->lcr |= SC16IS752_LCR_2_STOP_BIT; |
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192 | } else { |
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193 | ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT; |
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194 | } |
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195 | |
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196 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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197 | return true; |
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198 | } |
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199 | |
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200 | static bool sc16is752_first_open( |
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201 | rtems_termios_tty *tty, |
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202 | rtems_termios_device_context *base, |
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203 | struct termios *term, |
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204 | rtems_libio_open_close_args_t *args |
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205 | ) |
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206 | { |
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207 | bool ok; |
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208 | uint8_t fcr; |
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209 | |
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210 | (void)args; |
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211 | sc16is752_context *ctx = (sc16is752_context *)base; |
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212 | |
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213 | ctx->tty = tty; |
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214 | |
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215 | ok = (*ctx->first_open)(ctx); |
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216 | if (!ok) { |
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217 | return ok; |
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218 | } |
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219 | |
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220 | if (ctx->mode == SC16IS752_MODE_RS485) { |
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221 | ctx->efcr = SC16IS752_EFCR_RS485_ENABLE; |
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222 | } else { |
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223 | ctx->efcr = 0; |
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224 | } |
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225 | |
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226 | write_reg(ctx, SC16IS752_FCR, &ctx->efcr, 1); |
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227 | |
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228 | fcr = SC16IS752_FCR_FIFO_EN |
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229 | | SC16IS752_FCR_RX_FIFO_RST |
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230 | | SC16IS752_FCR_TX_FIFO_RST |
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231 | | SC16IS752_FCR_RX_FIFO_TRG_16 |
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232 | | SC16IS752_FCR_TX_FIFO_TRG_32; |
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233 | write_reg(ctx, SC16IS752_FCR, &fcr, 1); |
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234 | |
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235 | ctx->ier = SC16IS752_IER_RHR; |
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236 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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237 | set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_ENABLE); |
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238 | |
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239 | rtems_termios_set_initial_baud(tty, 115200); |
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240 | ok = sc16is752_set_attributes(base, term); |
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241 | if (!ok) { |
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242 | return ok; |
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243 | } |
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244 | |
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245 | ok = (*ctx->install_irq)(ctx); |
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246 | return ok; |
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247 | } |
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248 | |
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249 | static void sc16is752_last_close( |
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250 | rtems_termios_tty *tty, |
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251 | rtems_termios_device_context *base, |
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252 | rtems_libio_open_close_args_t *args |
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253 | ) |
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254 | { |
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255 | sc16is752_context *ctx = (sc16is752_context *)base; |
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256 | |
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257 | (void)tty; |
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258 | (void)args; |
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259 | (*ctx->last_close)(ctx); |
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260 | } |
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261 | |
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262 | static void sc16is752_write( |
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263 | rtems_termios_device_context *base, |
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264 | const char *buf, |
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265 | size_t len |
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266 | ) |
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267 | { |
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268 | sc16is752_context *ctx = (sc16is752_context *)base; |
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269 | |
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270 | if (len > 0) { |
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271 | ctx->ier |= SC16IS752_IER_THR; |
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272 | len = MIN(len, 32); |
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273 | ctx->tx_in_progress = (uint8_t)len; |
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274 | write_reg(ctx, SC16IS752_THR, (const uint8_t *)&buf[0], len); |
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275 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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276 | } else { |
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277 | ctx->tx_in_progress = 0; |
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278 | ctx->ier &= ~SC16IS752_IER_THR; |
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279 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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280 | } |
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281 | } |
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282 | |
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283 | static void sc16is752_get_modem_bits(sc16is752_context *ctx, int *bits) |
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284 | { |
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285 | *bits = 0; |
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286 | uint8_t msr; |
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287 | uint8_t mcr; |
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288 | |
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289 | read_reg(ctx, SC16IS752_MSR, &msr, 1); |
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290 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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291 | |
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292 | if (msr & SC16IS752_MSR_CTS) { |
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293 | *bits |= TIOCM_CTS; |
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294 | } |
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295 | if (msr & SC16IS752_MSR_DSR) { |
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296 | *bits |= TIOCM_DSR; |
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297 | } |
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298 | if (msr & SC16IS752_MSR_RI) { |
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299 | *bits |= TIOCM_RI; |
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300 | } |
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301 | if (msr & SC16IS752_MSR_CD) { |
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302 | *bits |= TIOCM_CD; |
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303 | } |
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304 | if ((mcr & SC16IS752_MCR_DTR) == 0) { |
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305 | *bits |= TIOCM_DTR; |
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306 | } |
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307 | if ((mcr & SC16IS752_MCR_RTS) == 0) { |
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308 | *bits |= TIOCM_RTS; |
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309 | } |
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310 | } |
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311 | |
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312 | static void sc16is752_set_modem_bits( |
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313 | sc16is752_context *ctx, int *bits, int set, int clear |
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314 | ) |
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315 | { |
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316 | uint8_t mcr; |
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317 | |
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318 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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319 | |
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320 | if (bits != NULL) { |
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321 | if ((*bits & TIOCM_DTR) == 0) { |
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322 | mcr |= SC16IS752_MCR_DTR; |
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323 | } else { |
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324 | mcr &= ~SC16IS752_MCR_DTR; |
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325 | } |
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326 | |
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327 | if ((*bits & TIOCM_RTS) == 0) { |
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328 | mcr |= SC16IS752_MCR_RTS; |
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329 | } else { |
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330 | mcr &= ~SC16IS752_MCR_RTS; |
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331 | } |
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332 | } |
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333 | |
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334 | if ((set & TIOCM_DTR) != 0) { |
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335 | mcr &= ~SC16IS752_MCR_DTR; |
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336 | } |
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337 | if ((set & TIOCM_RTS) != 0) { |
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338 | mcr &= ~SC16IS752_MCR_RTS; |
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339 | } |
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340 | if ((clear & TIOCM_DTR) != 0) { |
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341 | mcr |= SC16IS752_MCR_DTR; |
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342 | } |
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343 | if ((clear & TIOCM_RTS) != 0) { |
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344 | mcr |= SC16IS752_MCR_RTS; |
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345 | } |
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346 | |
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347 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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348 | } |
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349 | |
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350 | static int sc16is752_ioctl( |
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351 | rtems_termios_device_context *base, |
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352 | ioctl_command_t request, |
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353 | void *buffer |
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354 | ) |
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355 | { |
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356 | sc16is752_context *ctx = (sc16is752_context *)base; |
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357 | uint8_t regval; |
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358 | |
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359 | switch (request) { |
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360 | case SC16IS752_SET_SLEEP_MODE: |
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361 | set_sleep_mode(ctx, *(int *)buffer != 0); |
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362 | break; |
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363 | case SC16IS752_GET_SLEEP_MODE: |
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364 | *(int *)buffer = is_sleep_mode_enabled(ctx); |
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365 | break; |
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366 | case SC16IS752_SET_IOCONTROL: |
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367 | regval = (*(uint8_t *)buffer) & ~SC16IS752_IOCONTROL_SRESET; |
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368 | write_reg(ctx, SC16IS752_IOCONTROL, ®val, 1); |
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369 | break; |
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370 | case SC16IS752_GET_IOCONTROL: |
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371 | read_reg(ctx, SC16IS752_IOCONTROL, (uint8_t *)buffer, 1); |
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372 | break; |
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373 | case SC16IS752_SET_IODIR: |
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374 | write_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1); |
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375 | break; |
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376 | case SC16IS752_GET_IODIR: |
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377 | read_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1); |
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378 | break; |
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379 | case SC16IS752_SET_IOSTATE: |
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380 | write_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1); |
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381 | break; |
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382 | case SC16IS752_GET_IOSTATE: |
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383 | read_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1); |
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384 | break; |
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385 | case TIOCMGET: |
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386 | sc16is752_get_modem_bits(ctx, (int *)buffer); |
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387 | break; |
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388 | case TIOCMSET: |
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389 | sc16is752_set_modem_bits(ctx, (int *)buffer, 0, 0); |
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390 | break; |
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391 | case TIOCMBIS: |
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392 | sc16is752_set_modem_bits(ctx, NULL, *(int *)buffer, 0); |
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393 | break; |
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394 | case TIOCMBIC: |
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395 | sc16is752_set_modem_bits(ctx, NULL, 0, *(int *)buffer); |
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396 | break; |
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397 | default: |
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398 | rtems_set_errno_and_return_minus_one(EINVAL); |
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399 | } |
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400 | |
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401 | return 0; |
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402 | } |
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403 | |
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404 | const rtems_termios_device_handler sc16is752_termios_handler = { |
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405 | .first_open = sc16is752_first_open, |
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406 | .last_close = sc16is752_last_close, |
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407 | .write = sc16is752_write, |
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408 | .set_attributes = sc16is752_set_attributes, |
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409 | .ioctl = sc16is752_ioctl, |
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410 | .mode = TERMIOS_IRQ_SERVER_DRIVEN |
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411 | }; |
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412 | |
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413 | void sc16is752_interrupt_handler(void *arg) |
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414 | { |
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415 | sc16is752_context *ctx = (sc16is752_context *)arg; |
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416 | uint8_t data[2]; |
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417 | uint8_t iir; |
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418 | |
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419 | read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data); |
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420 | iir = data[0]; |
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421 | |
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422 | if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) { |
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423 | rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress); |
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424 | } |
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425 | |
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426 | if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) { |
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427 | uint8_t buf[SC16IS752_FIFO_DEPTH]; |
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428 | uint8_t rxlvl = data[1]; |
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429 | |
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430 | rxlvl = MIN(rxlvl, SC16IS752_FIFO_DEPTH); |
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431 | read_reg(ctx, SC16IS752_RHR, &buf[0], rxlvl); |
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432 | rtems_termios_enqueue_raw_characters(ctx->tty, (const char *)&buf[0], rxlvl); |
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433 | } |
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434 | } |
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