source: rtems/cpukit/dev/serial/sc16is752.c @ 8352d41

5
Last change on this file since 8352d41 was dcaea71, checked in by Christian Mauderer <christian.mauderer@…>, on 08/15/18 at 10:26:13

dev/sc16is752: Add name space for field names.

The field names for the registers generated a name collision (MSR_RI on
the power pc). This patch adds a SC16IS752_ prefix for all field names.

Closes #3501.

  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15
16#include <dev/serial/sc16is752.h>
17
18#include <sys/param.h>
19
20#include <assert.h>
21#include <stdio.h>
22#include <fcntl.h>
23
24#include <rtems/seterr.h>
25
26#include "sc16is752-regs.h"
27
28static void write_reg(
29  sc16is752_context *ctx,
30  uint8_t addr,
31  const uint8_t *data,
32  size_t len
33)
34{
35  (*ctx->write_reg)(ctx, addr, data, len);
36}
37
38static void read_reg(
39  sc16is752_context *ctx,
40  uint8_t addr,
41  uint8_t *data,
42  size_t len
43)
44{
45  (*ctx->read_reg)(ctx, addr, data, len);
46}
47
48static void read_2_reg(
49  sc16is752_context *ctx,
50  uint8_t addr_0,
51  uint8_t addr_1,
52  uint8_t data[2]
53)
54{
55  (*ctx->read_2_reg)(ctx, addr_0, addr_1, data);
56}
57
58static bool is_sleep_mode_enabled(sc16is752_context *ctx)
59{
60  return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0;
61}
62
63static void set_sleep_mode(sc16is752_context *ctx, bool enable)
64{
65  if (enable) {
66    ctx->ier |= SC16IS752_IER_SLEEP_MODE;
67  } else {
68    ctx->ier &= ~SC16IS752_IER_SLEEP_MODE;
69  }
70
71  write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
72}
73
74static void set_mcr_dll_dlh(
75  sc16is752_context *ctx,
76  uint8_t mcr,
77  uint32_t divisor
78)
79{
80  bool sleep_mode = is_sleep_mode_enabled(ctx);
81  uint8_t dll = (uint8_t)divisor;
82  uint8_t dlh = (uint8_t)(divisor >> 8);
83
84  if (sleep_mode) {
85    set_sleep_mode(ctx, false);
86  }
87
88  ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR;
89  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
90
91  write_reg(ctx, SC16IS752_MCR, &mcr, 1);
92  write_reg(ctx, SC16IS752_DLH, &dlh, 1);
93  write_reg(ctx, SC16IS752_DLL, &dll, 1);
94
95  ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR;
96  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
97
98  if (sleep_mode) {
99    set_sleep_mode(ctx, true);
100  }
101}
102
103static void set_efr(sc16is752_context *ctx, uint8_t efr)
104{
105  uint8_t lcr = ctx->lcr;
106
107  ctx->lcr = 0xbf;
108  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
109
110  write_reg(ctx, SC16IS752_EFR, &efr, 1);
111
112  ctx->lcr = lcr;
113  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
114}
115
116static bool set_baud(sc16is752_context *ctx, rtems_termios_baud_t baud)
117{
118  uint32_t freq = ctx->input_frequency;
119  uint8_t mcr;
120  uint32_t divisor;
121
122  read_reg(ctx, SC16IS752_MCR, &mcr, 1);
123
124  divisor = freq / baud / 16;
125  if (divisor > 0xFFFF){
126    divisor = (freq / (4 * baud)) / 16;
127    if (divisor > 0xFFFF){
128      return false;
129    } else {
130      mcr |= SC16IS752_MCR_PRESCALE_NEEDED;
131    }
132  } else {
133    mcr &= ~SC16IS752_MCR_PRESCALE_NEEDED;
134  }
135
136  set_mcr_dll_dlh(ctx, mcr, divisor);
137  return true;
138}
139
140static bool sc16is752_set_attributes(
141  rtems_termios_device_context *base,
142  const struct termios *term
143)
144{
145  sc16is752_context *ctx = (sc16is752_context *)base;
146  bool baud_successful;
147  rtems_termios_baud_t baud;
148
149  ctx->lcr = 0;
150
151  baud = rtems_termios_baud_to_number(term->c_ospeed);
152  baud_successful = set_baud(ctx, baud);
153  if (!baud_successful){
154    return false;
155  }
156
157  if ((term->c_cflag & CREAD) == 0){
158    ctx->efcr |= SC16IS752_EFCR_RX_DISABLE;
159  } else {
160    ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE;
161  }
162
163  write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1);
164
165  switch (term->c_cflag & CSIZE) {
166    case CS5:
167      ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT;
168      break;
169    case CS6:
170      ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT;
171      break;
172    case CS7:
173      ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT;
174      break;
175    case CS8:
176      ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT;
177      break;
178  }
179
180  if ((term->c_cflag & PARENB) != 0){
181    if ((term->c_cflag & PARODD) != 0) {
182      ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY;
183    } else {
184      ctx->lcr |= SC16IS752_LCR_EVEN_PARITY;
185    }
186  } else {
187    ctx->lcr &= ~SC16IS752_LCR_SET_PARITY;
188  }
189
190  if ((term->c_cflag & CSTOPB) != 0) {
191    ctx->lcr |= SC16IS752_LCR_2_STOP_BIT;
192  } else {
193    ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT;
194  }
195
196  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
197  return true;
198}
199
200static bool sc16is752_first_open(
201  rtems_termios_tty *tty,
202  rtems_termios_device_context *base,
203  struct termios *term,
204  rtems_libio_open_close_args_t *args
205)
206{
207  bool ok;
208  uint8_t fcr;
209
210  (void)args;
211  sc16is752_context *ctx = (sc16is752_context *)base;
212
213  ctx->tty = tty;
214
215  ok = (*ctx->first_open)(ctx);
216  if (!ok) {
217    return ok;
218  }
219
220  if (ctx->mode == SC16IS752_MODE_RS485) {
221    ctx->efcr = SC16IS752_EFCR_RS485_ENABLE;
222  } else {
223    ctx->efcr = 0;
224  }
225
226  write_reg(ctx, SC16IS752_FCR, &ctx->efcr, 1);
227
228  fcr = SC16IS752_FCR_FIFO_EN
229    | SC16IS752_FCR_RX_FIFO_RST
230    | SC16IS752_FCR_TX_FIFO_RST
231    | SC16IS752_FCR_RX_FIFO_TRG_16
232    | SC16IS752_FCR_TX_FIFO_TRG_32;
233  write_reg(ctx, SC16IS752_FCR, &fcr, 1);
234
235  ctx->ier = SC16IS752_IER_RHR;
236  write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
237  set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_ENABLE);
238
239  rtems_termios_set_initial_baud(tty, 115200);
240  ok = sc16is752_set_attributes(base, term);
241  if (!ok) {
242    return ok;
243  }
244
245  ok = (*ctx->install_irq)(ctx);
246  return ok;
247}
248
249static void sc16is752_last_close(
250  rtems_termios_tty *tty,
251  rtems_termios_device_context *base,
252  rtems_libio_open_close_args_t *args
253)
254{
255  sc16is752_context *ctx = (sc16is752_context *)base;
256
257  (void)tty;
258  (void)args;
259  (*ctx->last_close)(ctx);
260}
261
262static void sc16is752_write(
263  rtems_termios_device_context *base,
264  const char *buf,
265  size_t len
266)
267{
268  sc16is752_context *ctx = (sc16is752_context *)base;
269
270  if (len > 0) {
271    ctx->ier |= SC16IS752_IER_THR;
272    len = MIN(len, 32);
273    ctx->tx_in_progress = (uint8_t)len;
274    write_reg(ctx, SC16IS752_THR, (const uint8_t *)&buf[0], len);
275    write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
276  } else {
277    ctx->tx_in_progress = 0;
278    ctx->ier &= ~SC16IS752_IER_THR;
279    write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
280  }
281}
282
283static void sc16is752_get_modem_bits(sc16is752_context *ctx, int *bits)
284{
285  *bits = 0;
286  uint8_t msr;
287  uint8_t mcr;
288
289  read_reg(ctx, SC16IS752_MSR, &msr, 1);
290  read_reg(ctx, SC16IS752_MCR, &mcr, 1);
291
292  if (msr & SC16IS752_MSR_CTS) {
293    *bits |= TIOCM_CTS;
294  }
295  if (msr & SC16IS752_MSR_DSR) {
296    *bits |= TIOCM_DSR;
297  }
298  if (msr & SC16IS752_MSR_RI) {
299    *bits |= TIOCM_RI;
300  }
301  if (msr & SC16IS752_MSR_CD) {
302    *bits |= TIOCM_CD;
303  }
304  if ((mcr & SC16IS752_MCR_DTR) == 0) {
305    *bits |= TIOCM_DTR;
306  }
307  if ((mcr & SC16IS752_MCR_RTS) == 0) {
308    *bits |= TIOCM_RTS;
309  }
310}
311
312static void sc16is752_set_modem_bits(
313  sc16is752_context *ctx, int *bits, int set, int clear
314)
315{
316  uint8_t mcr;
317
318  read_reg(ctx, SC16IS752_MCR, &mcr, 1);
319
320  if (bits != NULL) {
321    if ((*bits & TIOCM_DTR) == 0) {
322      mcr |= SC16IS752_MCR_DTR;
323    } else {
324      mcr &= ~SC16IS752_MCR_DTR;
325    }
326
327    if ((*bits & TIOCM_RTS) == 0) {
328      mcr |= SC16IS752_MCR_RTS;
329    } else {
330      mcr &= ~SC16IS752_MCR_RTS;
331    }
332  }
333
334  if ((set & TIOCM_DTR) != 0) {
335    mcr &= ~SC16IS752_MCR_DTR;
336  }
337  if ((set & TIOCM_RTS) != 0) {
338    mcr &= ~SC16IS752_MCR_RTS;
339  }
340  if ((clear & TIOCM_DTR) != 0) {
341    mcr |= SC16IS752_MCR_DTR;
342  }
343  if ((clear & TIOCM_RTS) != 0) {
344    mcr |= SC16IS752_MCR_RTS;
345  }
346
347  write_reg(ctx, SC16IS752_MCR, &mcr, 1);
348}
349
350static int sc16is752_ioctl(
351  rtems_termios_device_context *base,
352  ioctl_command_t               request,
353  void                         *buffer
354)
355{
356  sc16is752_context *ctx = (sc16is752_context *)base;
357  uint8_t regval;
358
359  switch (request) {
360    case SC16IS752_SET_SLEEP_MODE:
361      set_sleep_mode(ctx, *(int *)buffer != 0);
362      break;
363    case SC16IS752_GET_SLEEP_MODE:
364      *(int *)buffer = is_sleep_mode_enabled(ctx);
365      break;
366    case SC16IS752_SET_IOCONTROL:
367      regval = (*(uint8_t *)buffer) & ~SC16IS752_IOCONTROL_SRESET;
368      write_reg(ctx, SC16IS752_IOCONTROL, &regval, 1);
369      break;
370    case SC16IS752_GET_IOCONTROL:
371      read_reg(ctx, SC16IS752_IOCONTROL, (uint8_t *)buffer, 1);
372      break;
373    case SC16IS752_SET_IODIR:
374      write_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1);
375      break;
376    case SC16IS752_GET_IODIR:
377      read_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1);
378      break;
379    case SC16IS752_SET_IOSTATE:
380      write_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1);
381      break;
382    case SC16IS752_GET_IOSTATE:
383      read_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1);
384      break;
385    case TIOCMGET:
386      sc16is752_get_modem_bits(ctx, (int *)buffer);
387      break;
388    case TIOCMSET:
389      sc16is752_set_modem_bits(ctx, (int *)buffer, 0, 0);
390      break;
391    case TIOCMBIS:
392      sc16is752_set_modem_bits(ctx, NULL, *(int *)buffer, 0);
393      break;
394    case TIOCMBIC:
395      sc16is752_set_modem_bits(ctx, NULL, 0, *(int *)buffer);
396      break;
397    default:
398      rtems_set_errno_and_return_minus_one(EINVAL);
399  }
400
401  return 0;
402}
403
404const rtems_termios_device_handler sc16is752_termios_handler = {
405  .first_open = sc16is752_first_open,
406  .last_close = sc16is752_last_close,
407  .write = sc16is752_write,
408  .set_attributes = sc16is752_set_attributes,
409  .ioctl = sc16is752_ioctl,
410  .mode = TERMIOS_IRQ_SERVER_DRIVEN
411};
412
413void sc16is752_interrupt_handler(void *arg)
414{
415  sc16is752_context *ctx = (sc16is752_context *)arg;
416  uint8_t data[2];
417  uint8_t iir;
418
419  read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data);
420  iir = data[0];
421
422  if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {
423    rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress);
424  }
425
426  if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) {
427    uint8_t buf[SC16IS752_FIFO_DEPTH];
428    uint8_t rxlvl = data[1];
429
430    rxlvl = MIN(rxlvl, SC16IS752_FIFO_DEPTH);
431    read_reg(ctx, SC16IS752_RHR, &buf[0], rxlvl);
432    rtems_termios_enqueue_raw_characters(ctx->tty, (const char *)&buf[0], rxlvl);
433  }
434}
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