1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | |
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10 | #include <dev/serial/sc16is752.h> |
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11 | |
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12 | #include <sys/param.h> |
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13 | |
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14 | #include <assert.h> |
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15 | #include <stdio.h> |
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16 | #include <fcntl.h> |
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17 | |
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18 | #include <rtems/seterr.h> |
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19 | |
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20 | #include "sc16is752-regs.h" |
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21 | |
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22 | static void write_reg( |
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23 | sc16is752_context *ctx, |
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24 | uint8_t addr, |
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25 | const uint8_t *data, |
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26 | size_t len |
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27 | ) |
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28 | { |
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29 | (*ctx->write_reg)(ctx, addr, data, len); |
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30 | } |
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31 | |
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32 | static void read_reg( |
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33 | sc16is752_context *ctx, |
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34 | uint8_t addr, |
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35 | uint8_t *data, |
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36 | size_t len |
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37 | ) |
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38 | { |
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39 | (*ctx->read_reg)(ctx, addr, data, len); |
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40 | } |
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41 | |
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42 | static void read_2_reg( |
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43 | sc16is752_context *ctx, |
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44 | uint8_t addr_0, |
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45 | uint8_t addr_1, |
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46 | uint8_t data[2] |
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47 | ) |
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48 | { |
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49 | (*ctx->read_2_reg)(ctx, addr_0, addr_1, data); |
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50 | } |
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51 | |
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52 | static bool is_sleep_mode_enabled(sc16is752_context *ctx) |
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53 | { |
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54 | return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0; |
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55 | } |
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56 | |
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57 | static void set_sleep_mode(sc16is752_context *ctx, bool enable) |
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58 | { |
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59 | if (enable) { |
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60 | ctx->ier |= SC16IS752_IER_SLEEP_MODE; |
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61 | } else { |
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62 | ctx->ier &= ~SC16IS752_IER_SLEEP_MODE; |
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63 | } |
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64 | |
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65 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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66 | } |
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67 | |
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68 | static void set_mcr_dll_dlh( |
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69 | sc16is752_context *ctx, |
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70 | uint8_t mcr, |
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71 | uint32_t divisor |
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72 | ) |
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73 | { |
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74 | bool sleep_mode = is_sleep_mode_enabled(ctx); |
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75 | uint8_t dll = (uint8_t)divisor; |
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76 | uint8_t dlh = (uint8_t)(divisor >> 8); |
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77 | |
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78 | if (sleep_mode) { |
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79 | set_sleep_mode(ctx, false); |
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80 | } |
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81 | |
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82 | ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR; |
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83 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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84 | |
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85 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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86 | write_reg(ctx, SC16IS752_DLH, &dlh, 1); |
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87 | write_reg(ctx, SC16IS752_DLL, &dll, 1); |
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88 | |
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89 | ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR; |
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90 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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91 | |
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92 | if (sleep_mode) { |
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93 | set_sleep_mode(ctx, true); |
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94 | } |
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95 | } |
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96 | |
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97 | static void set_efr(sc16is752_context *ctx, uint8_t efr) |
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98 | { |
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99 | uint8_t lcr = ctx->lcr; |
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100 | |
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101 | ctx->lcr = 0xbf; |
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102 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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103 | |
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104 | write_reg(ctx, SC16IS752_EFR, &efr, 1); |
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105 | |
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106 | ctx->lcr = lcr; |
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107 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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108 | } |
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109 | |
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110 | static void set_tlr(sc16is752_context *ctx, uint8_t tlr) |
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111 | { |
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112 | uint8_t mcr; |
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113 | |
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114 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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115 | mcr |= SC16IS752_MCR_TCR_TLR; |
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116 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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117 | write_reg(ctx, SC16IS752_TLR, &tlr, 1); |
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118 | mcr &= ~SC16IS752_MCR_TCR_TLR; |
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119 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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120 | } |
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121 | |
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122 | static bool set_baud(sc16is752_context *ctx, rtems_termios_baud_t baud) |
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123 | { |
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124 | uint32_t freq = ctx->input_frequency; |
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125 | uint8_t mcr; |
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126 | uint32_t divisor; |
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127 | |
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128 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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129 | |
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130 | divisor = freq / baud / 16; |
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131 | if (divisor > 0xFFFF){ |
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132 | divisor = (freq / (4 * baud)) / 16; |
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133 | if (divisor > 0xFFFF){ |
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134 | return false; |
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135 | } else { |
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136 | mcr |= SC16IS752_MCR_PRESCALE_NEEDED; |
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137 | } |
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138 | } else { |
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139 | mcr &= ~SC16IS752_MCR_PRESCALE_NEEDED; |
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140 | } |
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141 | |
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142 | set_mcr_dll_dlh(ctx, mcr, divisor); |
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143 | return true; |
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144 | } |
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145 | |
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146 | static bool sc16is752_set_attributes( |
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147 | rtems_termios_device_context *base, |
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148 | const struct termios *term |
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149 | ) |
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150 | { |
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151 | sc16is752_context *ctx = (sc16is752_context *)base; |
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152 | rtems_termios_baud_t baud; |
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153 | |
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154 | ctx->lcr = 0; |
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155 | |
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156 | baud = rtems_termios_baud_to_number(term->c_ospeed); |
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157 | |
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158 | if (baud > 0) { |
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159 | if (!set_baud(ctx, baud)){ |
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160 | return false; |
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161 | } |
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162 | |
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163 | ctx->efcr &= ~SC16IS752_EFCR_TX_DISABLE; |
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164 | |
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165 | if ((term->c_cflag & CREAD) == 0){ |
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166 | ctx->efcr |= SC16IS752_EFCR_RX_DISABLE; |
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167 | } else { |
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168 | ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE; |
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169 | } |
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170 | } else { |
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171 | ctx->efcr |= SC16IS752_EFCR_RX_DISABLE | SC16IS752_EFCR_TX_DISABLE; |
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172 | } |
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173 | |
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174 | write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1); |
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175 | |
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176 | switch (term->c_cflag & CSIZE) { |
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177 | case CS5: |
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178 | ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT; |
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179 | break; |
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180 | case CS6: |
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181 | ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT; |
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182 | break; |
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183 | case CS7: |
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184 | ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT; |
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185 | break; |
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186 | case CS8: |
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187 | ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT; |
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188 | break; |
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189 | } |
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190 | |
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191 | if ((term->c_cflag & PARENB) != 0){ |
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192 | ctx->lcr |= SC16IS752_LCR_SET_PARITY; |
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193 | if ((term->c_cflag & PARODD) != 0) { |
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194 | ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY; |
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195 | } else { |
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196 | ctx->lcr |= SC16IS752_LCR_EVEN_PARITY; |
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197 | } |
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198 | } else { |
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199 | ctx->lcr &= ~SC16IS752_LCR_SET_PARITY; |
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200 | } |
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201 | |
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202 | if ((term->c_cflag & CSTOPB) != 0) { |
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203 | ctx->lcr |= SC16IS752_LCR_2_STOP_BIT; |
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204 | } else { |
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205 | ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT; |
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206 | } |
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207 | |
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208 | write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); |
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209 | return true; |
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210 | } |
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211 | |
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212 | static bool sc16is752_first_open( |
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213 | rtems_termios_tty *tty, |
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214 | rtems_termios_device_context *base, |
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215 | struct termios *term, |
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216 | rtems_libio_open_close_args_t *args |
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217 | ) |
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218 | { |
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219 | bool ok; |
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220 | uint8_t fcr; |
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221 | uint8_t efcr; |
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222 | |
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223 | (void)args; |
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224 | sc16is752_context *ctx = (sc16is752_context *)base; |
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225 | |
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226 | ctx->tty = tty; |
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227 | |
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228 | ok = (*ctx->first_open)(ctx); |
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229 | if (!ok) { |
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230 | return ok; |
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231 | } |
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232 | |
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233 | set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_ENABLE); |
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234 | |
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235 | efcr = 0; |
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236 | |
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237 | switch (ctx->mode) { |
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238 | case SC16IS752_MODE_RS485_RTS_INV: |
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239 | efcr |= SC16IS752_EFCR_RTSINVER; |
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240 | /* Fall through */ |
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241 | case SC16IS752_MODE_RS485_RTS: |
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242 | efcr |= SC16IS752_EFCR_RTSCON; |
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243 | /* Fall through */ |
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244 | case SC16IS752_MODE_RS485: |
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245 | efcr |= SC16IS752_EFCR_RS485_ENABLE; |
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246 | break; |
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247 | default: |
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248 | break; |
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249 | } |
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250 | |
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251 | ctx->efcr = efcr; |
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252 | write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1); |
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253 | |
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254 | fcr = SC16IS752_FCR_FIFO_EN |
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255 | | SC16IS752_FCR_RX_FIFO_RST |
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256 | | SC16IS752_FCR_TX_FIFO_RST |
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257 | | SC16IS752_FCR_RX_FIFO_TRG_8 |
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258 | | SC16IS752_FCR_TX_FIFO_TRG_32; |
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259 | write_reg(ctx, SC16IS752_FCR, &fcr, 1); |
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260 | |
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261 | fcr = SC16IS752_FCR_FIFO_EN |
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262 | | SC16IS752_FCR_RX_FIFO_TRG_8 |
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263 | | SC16IS752_FCR_TX_FIFO_TRG_32; |
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264 | write_reg(ctx, SC16IS752_FCR, &fcr, 1); |
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265 | |
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266 | set_tlr(ctx, 0); |
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267 | |
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268 | ctx->ier = SC16IS752_IER_RHR; |
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269 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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270 | |
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271 | rtems_termios_set_initial_baud(tty, 115200); |
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272 | ok = sc16is752_set_attributes(base, term); |
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273 | if (!ok) { |
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274 | return ok; |
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275 | } |
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276 | |
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277 | ok = (*ctx->install_irq)(ctx); |
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278 | return ok; |
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279 | } |
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280 | |
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281 | static void sc16is752_last_close( |
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282 | rtems_termios_tty *tty, |
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283 | rtems_termios_device_context *base, |
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284 | rtems_libio_open_close_args_t *args |
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285 | ) |
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286 | { |
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287 | sc16is752_context *ctx = (sc16is752_context *)base; |
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288 | |
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289 | (void)tty; |
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290 | (void)args; |
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291 | (*ctx->last_close)(ctx); |
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292 | } |
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293 | |
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294 | static void sc16is752_write( |
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295 | rtems_termios_device_context *base, |
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296 | const char *buf, |
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297 | size_t len |
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298 | ) |
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299 | { |
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300 | sc16is752_context *ctx = (sc16is752_context *)base; |
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301 | |
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302 | if (len > 0) { |
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303 | ctx->ier |= SC16IS752_IER_THR; |
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304 | len = MIN(len, 32); |
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305 | ctx->tx_in_progress = (uint8_t)len; |
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306 | write_reg(ctx, SC16IS752_THR, (const uint8_t *)&buf[0], len); |
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307 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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308 | } else { |
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309 | ctx->tx_in_progress = 0; |
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310 | ctx->ier &= ~SC16IS752_IER_THR; |
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311 | write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); |
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312 | } |
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313 | } |
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314 | |
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315 | static void sc16is752_get_modem_bits(sc16is752_context *ctx, int *bits) |
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316 | { |
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317 | *bits = 0; |
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318 | uint8_t msr; |
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319 | uint8_t mcr; |
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320 | |
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321 | read_reg(ctx, SC16IS752_MSR, &msr, 1); |
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322 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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323 | |
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324 | if (msr & SC16IS752_MSR_CTS) { |
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325 | *bits |= TIOCM_CTS; |
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326 | } |
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327 | if (msr & SC16IS752_MSR_DSR) { |
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328 | *bits |= TIOCM_DSR; |
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329 | } |
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330 | if (msr & SC16IS752_MSR_RI) { |
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331 | *bits |= TIOCM_RI; |
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332 | } |
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333 | if (msr & SC16IS752_MSR_CD) { |
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334 | *bits |= TIOCM_CD; |
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335 | } |
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336 | if ((mcr & SC16IS752_MCR_DTR) == 0) { |
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337 | *bits |= TIOCM_DTR; |
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338 | } |
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339 | if ((mcr & SC16IS752_MCR_RTS) == 0) { |
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340 | *bits |= TIOCM_RTS; |
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341 | } |
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342 | } |
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343 | |
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344 | static void sc16is752_set_modem_bits( |
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345 | sc16is752_context *ctx, int *bits, int set, int clear |
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346 | ) |
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347 | { |
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348 | uint8_t mcr; |
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349 | |
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350 | read_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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351 | |
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352 | if (bits != NULL) { |
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353 | if ((*bits & TIOCM_DTR) == 0) { |
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354 | mcr |= SC16IS752_MCR_DTR; |
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355 | } else { |
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356 | mcr &= ~SC16IS752_MCR_DTR; |
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357 | } |
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358 | |
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359 | if ((*bits & TIOCM_RTS) == 0) { |
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360 | mcr |= SC16IS752_MCR_RTS; |
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361 | } else { |
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362 | mcr &= ~SC16IS752_MCR_RTS; |
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363 | } |
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364 | } |
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365 | |
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366 | if ((set & TIOCM_DTR) != 0) { |
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367 | mcr &= ~SC16IS752_MCR_DTR; |
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368 | } |
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369 | if ((set & TIOCM_RTS) != 0) { |
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370 | mcr &= ~SC16IS752_MCR_RTS; |
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371 | } |
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372 | if ((clear & TIOCM_DTR) != 0) { |
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373 | mcr |= SC16IS752_MCR_DTR; |
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374 | } |
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375 | if ((clear & TIOCM_RTS) != 0) { |
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376 | mcr |= SC16IS752_MCR_RTS; |
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377 | } |
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378 | |
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379 | write_reg(ctx, SC16IS752_MCR, &mcr, 1); |
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380 | } |
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381 | |
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382 | static int sc16is752_ioctl( |
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383 | rtems_termios_device_context *base, |
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384 | ioctl_command_t request, |
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385 | void *buffer |
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386 | ) |
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387 | { |
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388 | sc16is752_context *ctx = (sc16is752_context *)base; |
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389 | uint8_t regval; |
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390 | |
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391 | switch (request) { |
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392 | case SC16IS752_SET_SLEEP_MODE: |
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393 | set_sleep_mode(ctx, *(int *)buffer != 0); |
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394 | break; |
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395 | case SC16IS752_GET_SLEEP_MODE: |
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396 | *(int *)buffer = is_sleep_mode_enabled(ctx); |
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397 | break; |
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398 | case SC16IS752_SET_IOCONTROL: |
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399 | regval = (*(uint8_t *)buffer) & ~SC16IS752_IOCONTROL_SRESET; |
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400 | write_reg(ctx, SC16IS752_IOCONTROL, ®val, 1); |
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401 | break; |
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402 | case SC16IS752_GET_IOCONTROL: |
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403 | read_reg(ctx, SC16IS752_IOCONTROL, (uint8_t *)buffer, 1); |
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404 | break; |
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405 | case SC16IS752_SET_IODIR: |
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406 | write_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1); |
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407 | break; |
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408 | case SC16IS752_GET_IODIR: |
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409 | read_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1); |
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410 | break; |
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411 | case SC16IS752_SET_IOSTATE: |
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412 | write_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1); |
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413 | break; |
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414 | case SC16IS752_GET_IOSTATE: |
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415 | read_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1); |
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416 | break; |
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417 | case SC16IS752_SET_EFCR: |
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418 | write_reg(ctx, SC16IS752_EFCR, (uint8_t *)buffer, 1); |
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419 | break; |
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420 | case SC16IS752_GET_EFCR: |
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421 | read_reg(ctx, SC16IS752_EFCR, (uint8_t *)buffer, 1); |
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422 | break; |
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423 | case TIOCMGET: |
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424 | sc16is752_get_modem_bits(ctx, (int *)buffer); |
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425 | break; |
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426 | case TIOCMSET: |
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427 | sc16is752_set_modem_bits(ctx, (int *)buffer, 0, 0); |
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428 | break; |
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429 | case TIOCMBIS: |
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430 | sc16is752_set_modem_bits(ctx, NULL, *(int *)buffer, 0); |
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431 | break; |
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432 | case TIOCMBIC: |
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433 | sc16is752_set_modem_bits(ctx, NULL, 0, *(int *)buffer); |
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434 | break; |
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435 | default: |
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436 | rtems_set_errno_and_return_minus_one(EINVAL); |
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437 | } |
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438 | |
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439 | return 0; |
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440 | } |
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441 | |
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442 | const rtems_termios_device_handler sc16is752_termios_handler = { |
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443 | .first_open = sc16is752_first_open, |
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444 | .last_close = sc16is752_last_close, |
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445 | .write = sc16is752_write, |
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446 | .set_attributes = sc16is752_set_attributes, |
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447 | .ioctl = sc16is752_ioctl, |
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448 | .mode = TERMIOS_IRQ_SERVER_DRIVEN |
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449 | }; |
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450 | |
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451 | void sc16is752_interrupt_handler(void *arg) |
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452 | { |
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453 | sc16is752_context *ctx = (sc16is752_context *)arg; |
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454 | uint8_t data[2]; |
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455 | uint8_t iir; |
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456 | |
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457 | read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data); |
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458 | iir = data[0]; |
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459 | |
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460 | if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) { |
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461 | rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress); |
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462 | } |
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463 | |
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464 | if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) { |
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465 | uint8_t buf[SC16IS752_FIFO_DEPTH]; |
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466 | uint8_t rxlvl = data[1]; |
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467 | |
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468 | rxlvl = MIN(rxlvl, SC16IS752_FIFO_DEPTH); |
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469 | read_reg(ctx, SC16IS752_RHR, &buf[0], rxlvl); |
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470 | rtems_termios_enqueue_raw_characters(ctx->tty, (const char *)&buf[0], rxlvl); |
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471 | } |
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472 | } |
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