source: rtems/cpukit/dev/serial/sc16is752-regs.h @ dcaea71

5
Last change on this file since dcaea71 was dcaea71, checked in by Christian Mauderer <christian.mauderer@…>, on 08/15/18 at 10:26:13

dev/sc16is752: Add name space for field names.

The field names for the registers generated a name collision (MSR_RI on
the power pc). This patch adds a SC16IS752_ prefix for all field names.

Closes #3501.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_ATSAM_SC16IS752_H
16#define LIBBSP_ARM_ATSAM_SC16IS752_H
17
18#ifdef __cplusplus
19extern "C" {
20#endif /* __cplusplus */
21
22/* General register set */
23#define SC16IS752_RHR 0x0
24#define SC16IS752_THR 0x0
25#define SC16IS752_IER 0x1
26#define SC16IS752_FCR 0x2
27#define SC16IS752_IIR 0x2
28#define SC16IS752_LCR 0x3
29#define SC16IS752_MCR 0x4
30#define SC16IS752_LSR 0x5
31#define SC16IS752_MSR 0x6
32#define SC16IS752_TCR 0x6
33#define SC16IS752_SPR 0x7
34#define SC16IS752_TLR 0x7
35#define SC16IS752_TXLVL 0x8
36#define SC16IS752_RXLVL 0x9
37#define SC16IS752_IODIR 0xA
38#define SC16IS752_IOSTATE 0xB
39#define SC16IS752_IOINTENA 0xC
40#define SC16IS752_IOCONTROL 0xE
41#define SC16IS752_EFCR 0xF
42
43/* Special register set */
44#define SC16IS752_DLL 0x0
45#define SC16IS752_DLH 0x1
46
47/* Enhanced register set */
48#define SC16IS752_EFR 0x2
49#define SC16IS752_XON1 0x4
50#define SC16IS752_XON2 0x5
51#define SC16IS752_XOFF1 0x6
52#define SC16IS752_XOFF2 0x7
53
54/* FCR */
55#define SC16IS752_FCR_FIFO_EN        0x01
56#define SC16IS752_FCR_RX_FIFO_RST    0x02
57#define SC16IS752_FCR_TX_FIFO_RST    0x04
58#define SC16IS752_FCR_TX_FIFO_TRG_8  0x00
59#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10
60#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20
61#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30
62#define SC16IS752_FCR_RX_FIFO_TRG_8  0x00
63#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40
64#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80
65#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0
66
67/* EFCR */
68#define SC16IS752_EFCR_RS485_ENABLE (1u << 0)
69#define SC16IS752_EFCR_RX_DISABLE (1u << 1)
70#define SC16IS752_EFCR_TX_DISABLE (1u << 2)
71
72/* IER */
73#define SC16IS752_IER_RHR (1u << 0)
74#define SC16IS752_IER_THR (1u << 1)
75#define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2)
76#define SC16IS752_IER_MODEM_STATUS (1u << 3)
77#define SC16IS752_IER_SLEEP_MODE (1u << 4)
78#define SC16IS752_IER_XOFF (1u << 5)
79#define SC16IS752_IER_RTS (1u << 6)
80#define SC16IS752_IER_CTS (1u << 7)
81
82/* IIR */
83#define SC16IS752_IIR_TX_INTERRUPT (1u << 1)
84#define SC16IS752_IIR_RX_INTERRUPT (1u << 2)
85
86/* LCR */
87#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
88#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
89#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
90#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
91#define SC16IS752_LCR_2_STOP_BIT (1u << 2)
92#define SC16IS752_LCR_SET_PARITY (1u << 3)
93#define SC16IS752_LCR_EVEN_PARITY (1u << 4)
94#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)
95
96/* LSR */
97#define SC16IS752_LSR_TXEMPTY (1u << 5)
98#define SC16IS752_LSR_RXRDY (1u << 0)
99#define SC16IS752_LSR_ERROR_BITS (7u << 2)
100
101/* MCR */
102#define SC16IS752_MCR_DTR             (1u << 0)
103#define SC16IS752_MCR_RTS             (1u << 1)
104#define SC16IS752_MCR_TCR_TLR         (1u << 2)
105#define SC16IS752_MCR_LOOPBACK        (1u << 4)
106#define SC16IS752_MCR_XON_ANY         (1u << 5)
107#define SC16IS752_MCR_IRDA_ENABLE     (1u << 6)
108#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)
109
110/* MSR */
111#define SC16IS752_MSR_dCTS (1u << 0)
112#define SC16IS752_MSR_dDSR (1u << 1)
113#define SC16IS752_MSR_dRI  (1u << 2)
114#define SC16IS752_MSR_dCD  (1u << 3)
115#define SC16IS752_MSR_CTS  (1u << 4)
116#define SC16IS752_MSR_DSR  (1u << 5)
117#define SC16IS752_MSR_RI   (1u << 6)
118#define SC16IS752_MSR_CD   (1u << 7)
119
120/* EFR */
121#define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4)
122#define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5)
123#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)
124#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)
125
126/* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */
127
128#define SC16IS752_FIFO_DEPTH 64
129
130#ifdef __cplusplus
131}
132#endif /* __cplusplus */
133
134#endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */
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