[9edc7301] | 1 | /* |
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| 2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.org/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef LIBBSP_ARM_ATSAM_SC16IS752_H |
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| 16 | #define LIBBSP_ARM_ATSAM_SC16IS752_H |
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| 17 | |
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| 18 | #ifdef __cplusplus |
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| 19 | extern "C" { |
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| 20 | #endif /* __cplusplus */ |
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| 21 | |
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| 22 | /* General register set */ |
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| 23 | #define SC16IS752_RHR 0x0 |
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| 24 | #define SC16IS752_THR 0x0 |
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| 25 | #define SC16IS752_IER 0x1 |
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| 26 | #define SC16IS752_FCR 0x2 |
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| 27 | #define SC16IS752_IIR 0x2 |
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| 28 | #define SC16IS752_LCR 0x3 |
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| 29 | #define SC16IS752_MCR 0x4 |
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| 30 | #define SC16IS752_LSR 0x5 |
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| 31 | #define SC16IS752_MSR 0x6 |
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| 32 | #define SC16IS752_TCR 0x6 |
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| 33 | #define SC16IS752_SPR 0x7 |
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| 34 | #define SC16IS752_TLR 0x7 |
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| 35 | #define SC16IS752_TXLVL 0x8 |
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| 36 | #define SC16IS752_RXLVL 0x9 |
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| 37 | #define SC16IS752_IODIR 0xA |
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| 38 | #define SC16IS752_IOSTATE 0xB |
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| 39 | #define SC16IS752_IOINTENA 0xC |
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| 40 | #define SC16IS752_IOCONTROL 0xE |
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| 41 | #define SC16IS752_EFCR 0xF |
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| 42 | |
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| 43 | /* Special register set */ |
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| 44 | #define SC16IS752_DLL 0x0 |
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| 45 | #define SC16IS752_DLH 0x1 |
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| 46 | |
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| 47 | /* Enhanced register set */ |
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| 48 | #define SC16IS752_EFR 0x2 |
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| 49 | #define SC16IS752_XON1 0x4 |
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| 50 | #define SC16IS752_XON2 0x5 |
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| 51 | #define SC16IS752_XOFF1 0x6 |
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| 52 | #define SC16IS752_XOFF2 0x7 |
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| 53 | |
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| 54 | /* FCR */ |
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| 55 | #define FCR_FIFO_EN 0x01 |
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| 56 | #define FCR_RX_FIFO_RST 0x02 |
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| 57 | #define FCR_TX_FIFO_RST 0x04 |
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| 58 | #define FCR_TX_FIFO_TRG_8 0x00 |
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| 59 | #define FCR_TX_FIFO_TRG_16 0x10 |
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| 60 | #define FCR_TX_FIFO_TRG_32 0x20 |
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| 61 | #define FCR_TX_FIFO_TRG_56 0x30 |
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| 62 | #define FCR_RX_FIFO_TRG_8 0x00 |
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| 63 | #define FCR_RX_FIFO_TRG_16 0x40 |
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| 64 | #define FCR_RX_FIFO_TRG_56 0x80 |
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| 65 | #define FCR_RX_FIFO_TRG_60 0xc0 |
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| 66 | |
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| 67 | /* EFCR */ |
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| 68 | #define EFCR_RS485_ENABLE (1u << 0) |
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| 69 | #define EFCR_RX_DISABLE (1u << 1) |
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| 70 | #define EFCR_TX_DISABLE (1u << 2) |
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| 71 | |
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| 72 | /* IER */ |
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| 73 | #define IER_RHR (1u << 0) |
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| 74 | #define IER_THR (1u << 1) |
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| 75 | #define IER_RECEIVE_LINE_STATUS (1u << 2) |
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| 76 | #define IER_MODEM_STATUS (1u << 3) |
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| 77 | #define IER_SLEEP_MODE (1u << 4) |
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| 78 | #define IER_XOFF (1u << 5) |
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| 79 | #define IER_RTS (1u << 6) |
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| 80 | #define IER_CTS (1u << 7) |
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| 81 | |
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| 82 | /* IIR */ |
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| 83 | #define IIR_TX_INTERRUPT (1u << 1) |
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| 84 | #define IIR_RX_INTERRUPT (1u << 2) |
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| 85 | |
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| 86 | /* LCR */ |
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| 87 | #define LCR_CHRL_5_BIT (0u << 1) | (0u << 0) |
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| 88 | #define LCR_CHRL_6_BIT (0u << 1) | (1u << 0) |
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| 89 | #define LCR_CHRL_7_BIT (1u << 1) | (0u << 0) |
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| 90 | #define LCR_CHRL_8_BIT (1u << 1) | (1u << 0) |
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| 91 | #define LCR_2_STOP_BIT (1u << 2) |
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| 92 | #define LCR_SET_PARITY (1u << 3) |
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| 93 | #define LCR_EVEN_PARITY (1u << 4) |
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| 94 | #define LCR_ENABLE_DIVISOR (1u << 7) |
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| 95 | |
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| 96 | /* LSR */ |
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| 97 | #define LSR_TXEMPTY (1u << 5) |
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| 98 | #define LSR_RXRDY (1u << 0) |
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| 99 | #define LSR_ERROR_BITS (7u << 2) |
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| 100 | |
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| 101 | /* MCR */ |
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| 102 | #define MCR_PRESCALE_NEEDED (1u << 0) |
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| 103 | |
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| 104 | /* EFR */ |
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| 105 | #define EFR_ENHANCED_FUNC_ENABLE (1u << 4) |
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| 106 | #define EFR_SPECIAL_CHAR_DETECT (1u << 5) |
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| 107 | #define EFR_RTS_FLOW_CTRL_EN (1u << 6) |
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| 108 | #define EFR_CTS_FLOW_CTRL_EN (1u << 7) |
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| 109 | |
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[bf70702] | 110 | /* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */ |
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| 111 | |
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[9edc7301] | 112 | #define SC16IS752_FIFO_DEPTH 64 |
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| 113 | |
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| 114 | #ifdef __cplusplus |
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| 115 | } |
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| 116 | #endif /* __cplusplus */ |
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| 117 | |
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| 118 | #endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */ |
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