1 | /* |
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2 | * Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org> All rights reserved. |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Xilinx AXI IIC Interface v2.0. See PG090.pdf. |
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11 | * |
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12 | * Note, only master support is provided and no dynamic mode by design. |
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13 | * |
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14 | * The clock set up is to be handled by the IP integrator. There are too many |
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15 | * factors handling this in software. |
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16 | */ |
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17 | |
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18 | |
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19 | #ifndef XILINX_AXI_I2C_H |
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20 | #define XILINX_AXI_I2C_H |
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21 | |
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22 | #include <dev/i2c/i2c.h> |
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23 | |
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24 | /* |
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25 | * The PL integrator controls the timing. This interface allows software to |
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26 | * override those settings. It pays to check the timing with ChipScope. |
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27 | * |
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28 | * If you set the AXI bus frequency you can use the clock speed ioctl call to |
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29 | * change the speed dymanically. The ioctl call overrides the defaults passed |
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30 | * in. |
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31 | * |
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32 | * Set the valid mask to the values that are to be set. |
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33 | */ |
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34 | #define XILINX_AIX_I2C_AXI_CLOCK (1 << 0) |
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35 | #define XILINX_AIX_I2C_TSUSTA (1 << 1) |
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36 | #define XILINX_AIX_I2C_TSUSTO (1 << 2) |
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37 | #define XILINX_AIX_I2C_THDSTA (1 << 3) |
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38 | #define XILINX_AIX_I2C_TSUDAT (1 << 4) |
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39 | #define XILINX_AIX_I2C_TBUF (1 << 5) |
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40 | #define XILINX_AIX_I2C_THIGH (1 << 6) |
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41 | #define XILINX_AIX_I2C_TLOW (1 << 7) |
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42 | #define XILINX_AIX_I2C_THDDAT (1 << 8) |
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43 | #define XILINX_AIX_I2C_ALL_REGS (XILINX_AIX_I2C_TSUSTA | \ |
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44 | XILINX_AIX_I2C_TSUSTO | \ |
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45 | XILINX_AIX_I2C_THDSTA | \ |
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46 | XILINX_AIX_I2C_TSUDAT | \ |
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47 | XILINX_AIX_I2C_TBUF | \ |
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48 | XILINX_AIX_I2C_THIGH | \ |
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49 | XILINX_AIX_I2C_TLOW | \ |
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50 | XILINX_AIX_I2C_THDDAT) |
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51 | typedef struct |
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52 | { |
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53 | uint32_t valid_mask; |
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54 | uint32_t AXI_CLOCK; |
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55 | uint32_t SCL_INERTIAL_DELAY; |
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56 | uint32_t TSUSTA; |
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57 | uint32_t TSUSTO; |
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58 | uint32_t THDSTA; |
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59 | uint32_t TSUDAT; |
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60 | uint32_t TBUF; |
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61 | uint32_t THIGH; |
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62 | uint32_t TLOW; |
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63 | uint32_t THDDAT; |
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64 | } xilinx_aix_i2c_timing; |
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65 | |
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66 | /* |
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67 | * Register the driver. |
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68 | * |
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69 | * The driver can multipex a number of I2C buses (in master mode only) using |
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70 | * the GPO port. The PL designer can use the output pins to select a bus. This |
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71 | * is useful if connecting a number of slave devices that have limit selectable |
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72 | * addresses. |
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73 | * |
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74 | * @param bus_path The driver's device path. |
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75 | * @param register_base AXI base address. |
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76 | * @param irq AXI FPGA interrupt. |
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77 | * @param gpio_address Bits 12:15 of a slave address it written to the GPO. |
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78 | * @param timing Override the default timing. NULL means no changes. |
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79 | */ |
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80 | int i2c_bus_register_xilinx_aix_i2c(const char* bus_path, |
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81 | uintptr_t register_base, |
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82 | rtems_vector_number irq, |
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83 | bool ten_gpio, |
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84 | const xilinx_aix_i2c_timing* timing); |
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85 | |
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86 | #endif |
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