source:
rtems/contrib/crossrpms/patches/gcc-core-4.4.6-rtems4.10-20110420.diff
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7c2d5b4
Last change on this file since 7c2d5b4 was 7c2d5b4, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/20/11 at 15:35:22 | |
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ChangeLog.rtems
diff -Naur gcc-4.4.6.orig/ChangeLog.rtems gcc-4.4.6/ChangeLog.rtems
old new 1 2011-04-20 Ralf Corsépius <ralf.corsepius@rtems.org> 2 3 * configure, configure.ac (PPL): Merge gcc-4.6.0's ppl detection 4 (Work-around build breakdown on fedora 15). 5 6 Ralf Corsépius <ralf.corsepius@rtems.org> 7 8 * configure, configure.ac (skipdirs): Add target-libiberty. 9 -
configure
diff -Naur gcc-4.4.6.orig/configure gcc-4.4.6/configure
old new 935 935 --enable-gold use gold instead of ld 936 936 --enable-libada build libada directory 937 937 --enable-libssp build libssp directory 938 --disable-ppl-version-check disable check for PPL version 938 --disable-ppl-version-check 939 disable check for PPL version 939 940 --disable-cloog-version-check disable check for CLooG version 940 941 --enable-stage1-languages[=all] choose additional languages to build during 941 942 stage1. Mostly useful for compiler development. … … 971 972 --with-gmp-lib=PATH specify directory for the installed GMP library 972 973 --with-host-libstdcxx=L Use linker arguments L to link with libstdc++ 973 974 when linking with PPL 974 --with-ppl=PATH Specify prefix directory for the installed PPL package 975 Equivalent to --with-ppl-include=PATH/include 976 plus --with-ppl-lib=PATH/lib 977 --with-ppl-include=PATH Specify directory for installed PPL include files 978 --with-ppl-lib=PATH Specify the directory for the installed PPL library 975 --with-ppl=PATH specify prefix directory for the installed PPL 976 package. Equivalent to 977 --with-ppl-include=PATH/include plus 978 --with-ppl-lib=PATH/lib 979 --with-ppl-include=PATH specify directory for installed PPL include files 980 --with-ppl-lib=PATH specify directory for the installed PPL library 979 981 --with-cloog=PATH Specify prefix directory for the installed CLooG-PPL package 980 982 Equivalent to --with-cloog-include=PATH/include 981 983 plus --with-cloog-lib=PATH/lib … … 2267 2269 noconfigdirs="$noconfigdirs target-newlib target-libiberty target-libgloss ${libgcj} target-libmudflap" 2268 2270 ;; 2269 2271 *-*-rtems*) 2272 skipdirs="$skipdirs target-libiberty" 2270 2273 noconfigdirs="$noconfigdirs target-libgloss ${libgcj}" 2271 2274 ;; 2272 2275 # The tpf target doesn't support gdb yet. … … 4829 4832 esac 4830 4833 4831 4834 # Check for PPL 4832 ppl_major_version=0 4833 ppl_minor_version=10 4834 ppllibs=" -lppl_c -lppl -lgmpxx $with_host_libstdcxx " 4835 ppllibs= 4835 4836 pplinc= 4837 pwllib= 4836 4838 4837 4839 4838 4840 # Check whether --with-ppl or --without-ppl was given. … … 4841 4843 4842 4844 fi; 4843 4845 4844 # Check whether --with-ppl _include or --without-ppl_include was given.4846 # Check whether --with-ppl-include or --without-ppl-include was given. 4845 4847 if test "${with_ppl_include+set}" = set; then 4846 4848 withval="$with_ppl_include" 4847 4849 4848 4850 fi; 4849 4851 4850 # Check whether --with-ppl _lib or --without-ppl_lib was given.4852 # Check whether --with-ppl-lib or --without-ppl-lib was given. 4851 4853 if test "${with_ppl_lib+set}" = set; then 4852 4854 withval="$with_ppl_lib" 4853 4855 4854 4856 fi; 4855 4857 4858 # Check whether --enable-ppl-version-check or --disable-ppl-version-check was given. 4859 if test "${enable_ppl_version_check+set}" = set; then 4860 enableval="$enable_ppl_version_check" 4861 4862 fi; 4863 4856 4864 case $with_ppl in 4857 no) 4858 ppllibs= 4865 yes | no | "") 4859 4866 ;; 4860 4867 *) 4861 ppllibs="-L$with_ppl/lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"4868 ppllibs="-L$with_ppl/lib" 4862 4869 pplinc="-I$with_ppl/include $pplinc" 4863 LIBS="$ppllibs $LIBS" 4870 if test -d "$with_ppl/lib" && test -d "$with_ppl/include"; then 4871 with_ppl=yes 4872 else 4873 { { echo "$as_me:$LINENO: error: cannot find directories \"$with_ppl/lib\" or \"$with_ppl/include\"" >&5 4874 echo "$as_me: error: cannot find directories \"$with_ppl/lib\" or \"$with_ppl/include\"" >&2;} 4875 { (exit 1); exit 1; }; } 4876 fi 4864 4877 ;; 4865 4878 esac 4866 if test "x$with_ppl_include" != x; then 4879 4880 if test x"$with_ppl_include" != x; then 4867 4881 pplinc="-I$with_ppl_include $pplinc" 4882 with_ppl=yes 4868 4883 fi 4884 4869 4885 if test "x$with_ppl_lib" != x; then 4870 ppllibs="-L$with_ppl_lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"4871 LIBS="$ppllibs $LIBS"4886 ppllibs="-L$with_ppl_lib" 4887 with_ppl=yes 4872 4888 fi 4873 if test "x$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then 4874 ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/.libs -L$$r/$(HOST_SUBDIR)/ppl/_libs -lppl_c -lppl -lgmpxx '"$with_host_libstdcxx " 4875 pplinc='-I$$r/$(HOST_SUBDIR)/ppl/include -I$$s/ppl/include ' 4876 LIBS="$ppllibs $LIBS" 4889 4890 if test x"$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then 4891 if test x"$enable_watchdog" = xyes; then 4892 pwllib="-lpwl" 4893 fi 4894 ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/interfaces/C/'"$lt_cv_objdir"' -L$$r/$(HOST_SUBDIR)/ppl/src/'"$lt_cv_objdir" 4895 pplinc='-I$$r/$(HOST_SUBDIR)/ppl/src -I$$r/$(HOST_SUBDIR)/ppl/interfaces/C ' 4896 enable_ppl_version_check=no 4897 with_ppl=yes 4877 4898 fi 4878 4899 4879 # Check whether --enable-ppl-version-check or --disable-ppl-version-check was given. 4880 if test "${enable_ppl_version_check+set}" = set; then 4881 enableval="$enable_ppl_version_check" 4882 ENABLE_PPL_CHECK=$enableval 4900 if test "x$with_ppl" != xno; then 4901 if test "x$pwllib" = x; then 4902 saved_LDFLAGS="$LDFLAGS" 4903 LDFLAGS="$LDFLAGS $ppllibs" 4904 echo "$as_me:$LINENO: checking for PWL_handle_timeout in -lpwl" >&5 4905 echo $ECHO_N "checking for PWL_handle_timeout in -lpwl... $ECHO_C" >&6 4906 if test "${ac_cv_lib_pwl_PWL_handle_timeout+set}" = set; then 4907 echo $ECHO_N "(cached) $ECHO_C" >&6 4883 4908 else 4884 ENABLE_PPL_CHECK=yes 4885 fi; 4909 ac_check_lib_save_LIBS=$LIBS 4910 LIBS="-lpwl $LIBS" 4911 cat >conftest.$ac_ext <<_ACEOF 4912 /* confdefs.h. */ 4913 _ACEOF 4914 cat confdefs.h >>conftest.$ac_ext 4915 cat >>conftest.$ac_ext <<_ACEOF 4916 /* end confdefs.h. */ 4886 4917 4887 if test "${ENABLE_PPL_CHECK}" = "yes"; then 4888 saved_CFLAGS="$CFLAGS" 4889 CFLAGS="$CFLAGS $pplinc $gmpinc" 4890 echo "$as_me:$LINENO: checking for version $ppl_major_version.$ppl_minor_version of PPL" >&5 4891 echo $ECHO_N "checking for version $ppl_major_version.$ppl_minor_version of PPL... $ECHO_C" >&6 4892 cat >conftest.$ac_ext <<_ACEOF 4918 /* Override any gcc2 internal prototype to avoid an error. */ 4919 #ifdef __cplusplus 4920 extern "C" 4921 #endif 4922 /* We use char because int might match the return type of a gcc2 4923 builtin and then its argument prototype would still apply. */ 4924 char PWL_handle_timeout (); 4925 int 4926 main () 4927 { 4928 PWL_handle_timeout (); 4929 ; 4930 return 0; 4931 } 4932 _ACEOF 4933 rm -f conftest.$ac_objext conftest$ac_exeext 4934 if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 4935 (eval $ac_link) 2>conftest.er1 4936 ac_status=$? 4937 grep -v '^ *+' conftest.er1 >conftest.err 4938 rm -f conftest.er1 4939 cat conftest.err >&5 4940 echo "$as_me:$LINENO: \$? = $ac_status" >&5 4941 (exit $ac_status); } && 4942 { ac_try='test -z "$ac_c_werror_flag" 4943 || test ! -s conftest.err' 4944 { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 4945 (eval $ac_try) 2>&5 4946 ac_status=$? 4947 echo "$as_me:$LINENO: \$? = $ac_status" >&5 4948 (exit $ac_status); }; } && 4949 { ac_try='test -s conftest$ac_exeext' 4950 { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 4951 (eval $ac_try) 2>&5 4952 ac_status=$? 4953 echo "$as_me:$LINENO: \$? = $ac_status" >&5 4954 (exit $ac_status); }; }; then 4955 ac_cv_lib_pwl_PWL_handle_timeout=yes 4956 else 4957 echo "$as_me: failed program was:" >&5 4958 sed 's/^/| /' conftest.$ac_ext >&5 4959 4960 ac_cv_lib_pwl_PWL_handle_timeout=no 4961 fi 4962 rm -f conftest.err conftest.$ac_objext \ 4963 conftest$ac_exeext conftest.$ac_ext 4964 LIBS=$ac_check_lib_save_LIBS 4965 fi 4966 echo "$as_me:$LINENO: result: $ac_cv_lib_pwl_PWL_handle_timeout" >&5 4967 echo "${ECHO_T}$ac_cv_lib_pwl_PWL_handle_timeout" >&6 4968 if test $ac_cv_lib_pwl_PWL_handle_timeout = yes; then 4969 pwllib="-lpwl" 4970 fi 4971 4972 LDFLAGS="$saved_LDFLAGS" 4973 fi 4974 4975 ppllibs="$ppllibs -lppl_c -lppl $pwllib -lgmpxx" 4976 4977 if test "$enable_ppl_version_check" != no; then 4978 saved_CFLAGS="$CFLAGS" 4979 CFLAGS="$CFLAGS $pplinc $gmpinc" 4980 echo "$as_me:$LINENO: checking for version 0.10 (revision 0 or later) of PPL" >&5 4981 echo $ECHO_N "checking for version 0.10 (revision 0 or later) of PPL... $ECHO_C" >&6 4982 cat >conftest.$ac_ext <<_ACEOF 4893 4983 /* confdefs.h. */ 4894 4984 _ACEOF 4895 4985 cat confdefs.h >>conftest.$ac_ext … … 4900 4990 main () 4901 4991 { 4902 4992 4903 #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version4904 choke me4905 #endif4993 #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10 4994 choke me 4995 #endif 4906 4996 4907 4997 ; 4908 4998 return 0; … … 4937 5027 sed 's/^/| /' conftest.$ac_ext >&5 4938 5028 4939 5029 echo "$as_me:$LINENO: result: no" >&5 4940 echo "${ECHO_T}no" >&6; ppllibs= ; pplinc= 5030 echo "${ECHO_T}no" >&6; ppllibs= ; pplinc= ; with_ppl=no 4941 5031 fi 4942 5032 rm -f conftest.err conftest.$ac_objext conftest.$ac_ext 4943 CFLAGS="$saved_CFLAGS" 5033 CFLAGS="$saved_CFLAGS" 5034 fi 4944 5035 fi 4945 5036 4946 5037 # Flags needed for PPL … … 6259 6350 # to it. This is right: we don't want to search that directory 6260 6351 # for binaries, but we want the header files in there, so add 6261 6352 # them explicitly. 6262 FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include '6353 FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include -isystem $$r/$(HOST_SUBDIR)/gcc/include-fixed' 6263 6354 6264 6355 # Someone might think of using the pre-installed headers on 6265 6356 # Canadian crosses, in case the installed compiler is not fully -
configure.ac
diff -Naur gcc-4.4.6.orig/configure.ac gcc-4.4.6/configure.ac
old new 502 502 noconfigdirs="$noconfigdirs target-newlib target-libiberty target-libgloss ${libgcj} target-libmudflap" 503 503 ;; 504 504 *-*-rtems*) 505 skipdirs="$skipdirs target-libiberty" 505 506 noconfigdirs="$noconfigdirs target-libgloss ${libgcj}" 506 507 ;; 507 508 # The tpf target doesn't support gdb yet. … … 1328 1329 esac 1329 1330 1330 1331 # Check for PPL 1331 ppl_major_version=0 1332 ppl_minor_version=10 1333 ppllibs=" -lppl_c -lppl -lgmpxx $with_host_libstdcxx " 1332 ppllibs= 1334 1333 pplinc= 1334 pwllib= 1335 1335 1336 AC_ARG_WITH(ppl, [ --with-ppl=PATH Specify prefix directory for the installed PPL package 1337 Equivalent to --with-ppl-include=PATH/include 1338 plus --with-ppl-lib=PATH/lib]) 1339 AC_ARG_WITH(ppl_include, [ --with-ppl-include=PATH Specify directory for installed PPL include files]) 1340 AC_ARG_WITH(ppl_lib, [ --with-ppl-lib=PATH Specify the directory for the installed PPL library]) 1336 AC_ARG_WITH(ppl, 1337 [AS_HELP_STRING([--with-ppl=PATH], 1338 [specify prefix directory for the installed PPL package. 1339 Equivalent to --with-ppl-include=PATH/include 1340 plus --with-ppl-lib=PATH/lib])]) 1341 AC_ARG_WITH(ppl-include, 1342 [AS_HELP_STRING([--with-ppl-include=PATH], 1343 [specify directory for installed PPL include files])]) 1344 AC_ARG_WITH(ppl-lib, 1345 [AS_HELP_STRING([--with-ppl-lib=PATH], 1346 [specify directory for the installed PPL library])]) 1341 1347 1342 case $with_ppl in 1343 no) 1344 ppllibs= 1348 AC_ARG_ENABLE(ppl-version-check, 1349 [AS_HELP_STRING([--disable-ppl-version-check], 1350 [disable check for PPL version])]) 1351 1352 case $with_ppl in 1353 yes | no | "") 1345 1354 ;; 1346 1355 *) 1347 ppllibs="-L$with_ppl/lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"1356 ppllibs="-L$with_ppl/lib" 1348 1357 pplinc="-I$with_ppl/include $pplinc" 1349 LIBS="$ppllibs $LIBS" 1358 if test -d "$with_ppl/lib" && test -d "$with_ppl/include"; then 1359 with_ppl=yes 1360 else 1361 AC_MSG_ERROR([cannot find directories "$with_ppl/lib" or "$with_ppl/include"]) 1362 fi 1350 1363 ;; 1351 1364 esac 1352 if test "x$with_ppl_include" != x; then 1365 1366 if test x"$with_ppl_include" != x; then 1353 1367 pplinc="-I$with_ppl_include $pplinc" 1368 with_ppl=yes 1354 1369 fi 1370 1355 1371 if test "x$with_ppl_lib" != x; then 1356 ppllibs="-L$with_ppl_lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"1357 LIBS="$ppllibs $LIBS"1372 ppllibs="-L$with_ppl_lib" 1373 with_ppl=yes 1358 1374 fi 1359 if test "x$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then 1360 ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/.libs -L$$r/$(HOST_SUBDIR)/ppl/_libs -lppl_c -lppl -lgmpxx '"$with_host_libstdcxx " 1361 pplinc='-I$$r/$(HOST_SUBDIR)/ppl/include -I$$s/ppl/include ' 1362 LIBS="$ppllibs $LIBS" 1375 1376 if test x"$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then 1377 if test x"$enable_watchdog" = xyes; then 1378 pwllib="-lpwl" 1379 fi 1380 ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/interfaces/C/'"$lt_cv_objdir"' -L$$r/$(HOST_SUBDIR)/ppl/src/'"$lt_cv_objdir" 1381 pplinc='-I$$r/$(HOST_SUBDIR)/ppl/src -I$$r/$(HOST_SUBDIR)/ppl/interfaces/C ' 1382 enable_ppl_version_check=no 1383 with_ppl=yes 1363 1384 fi 1364 1385 1365 AC_ARG_ENABLE(ppl-version-check, 1366 [ --disable-ppl-version-check disable check for PPL version], 1367 ENABLE_PPL_CHECK=$enableval, 1368 ENABLE_PPL_CHECK=yes) 1386 if test "x$with_ppl" != xno; then 1387 if test "x$pwllib" = x; then 1388 saved_LDFLAGS="$LDFLAGS" 1389 LDFLAGS="$LDFLAGS $ppllibs" 1390 AC_CHECK_LIB(pwl,PWL_handle_timeout,[pwllib="-lpwl"]) 1391 LDFLAGS="$saved_LDFLAGS" 1392 fi 1369 1393 1370 if test "${ENABLE_PPL_CHECK}" = "yes"; then 1371 saved_CFLAGS="$CFLAGS" 1372 CFLAGS="$CFLAGS $pplinc $gmpinc" 1373 AC_MSG_CHECKING([for version $ppl_major_version.$ppl_minor_version of PPL]) 1374 AC_TRY_COMPILE([#include "ppl_c.h"],[ 1375 #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version 1376 choke me 1377 #endif 1378 ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ]) 1379 CFLAGS="$saved_CFLAGS" 1394 ppllibs="$ppllibs -lppl_c -lppl $pwllib -lgmpxx" 1395 1396 if test "$enable_ppl_version_check" != no; then 1397 saved_CFLAGS="$CFLAGS" 1398 CFLAGS="$CFLAGS $pplinc $gmpinc" 1399 AC_MSG_CHECKING([for version 0.10 (revision 0 or later) of PPL]) 1400 AC_TRY_COMPILE([#include "ppl_c.h"],[ 1401 #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10 1402 choke me 1403 #endif 1404 ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ; with_ppl=no ]) 1405 CFLAGS="$saved_CFLAGS" 1406 fi 1380 1407 fi 1381 1408 1382 1409 # Flags needed for PPL … … 2560 2587 # to it. This is right: we don't want to search that directory 2561 2588 # for binaries, but we want the header files in there, so add 2562 2589 # them explicitly. 2563 FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include '2590 FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include -isystem $$r/$(HOST_SUBDIR)/gcc/include-fixed' 2564 2591 2565 2592 # Someone might think of using the pre-installed headers on 2566 2593 # Canadian crosses, in case the installed compiler is not fully -
gcc/ChangeLog.rtems
diff -Naur gcc-4.4.6.orig/gcc/ChangeLog.rtems gcc-4.4.6/gcc/ChangeLog.rtems
old new 1 2011-02-20 Ralf Corsépius <ralf.corsepius@rtems.org> 2 3 * config/rs6000/t-rtems: Remove -mcpu=601 multilib. 4 * config/rs6000/t-rtems: Remove -Dmpc8260 multilib. 5 6 2010-03-15 Ralf Corsépius <ralf.corsepius@rtems.org> 7 8 Patch from Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>: 9 * config/arm/rtems-elf.h, config/arm/t-rtems: Add optional support 10 for vfp FPU model 11 12 2010-02-10 Ralf Corsépius <ralf.corsepius@rtems.org> 13 14 * config/rtems.h: Abandon -qrtems_debug. 15 16 2009-12-01 Ralf Corsépius <ralf.corsepius@rtems.org> 17 18 * config/avr/avr.h (LINK_SPEC): Pass -m avrN to ld for -mmcu=avrN. 19 20 2009-11-04 Ralf Corsépius <ralf.corsepius@rtems.org> 21 22 * config/m32c/rtems.h, config/m68k/rtemself.h, 23 config/m68k/rtemself.h, config/sh/rtemself.h, 24 config/sparc/rtemself.h: Undef WCHAR_TYPE_SIZE, WCHAR_TYPE. 25 (Resets WCHAR_TYPE's to defaults. Prevents broken GCC tm_files 26 to interfere and cause wchar_t/wint_t incompatibilities). 27 28 2009-10-15 Ralf Corsépius <ralf.corsepius@rtems.org> 29 30 * config/avr/t-rtems: Don't build _exit. 31 32 Jon Beniston <jon@beniston.com> 33 34 * config/lm32/arithmetic.c, config/lm32/crti.S, 35 config/lm32/crtn.S, config/lm32/lib1funcs.S, 36 config/lm32/lm32.c, config/lm32/lm32.h, 37 config/lm32/lm32.md, config/lm32/lm32.opt, 38 config/lm32/lm32-protos.h, config/lm32/predicates.md, 39 config/lm32/rtems.h, config/lm32/sfp-machine.h, 40 config/lm32/t-fprules-softfp, config/lm32/t-lm32, 41 config/lm32/uclinux-elf.h: New (lm32 port). 42 * config.gcc: Add lm32* targets. 43 * doc/contrib.texi, doc/invoke.texi: Add lm32. 44 45 Ralf Corsépius <ralf.corsepius@rtems.org> 46 47 * config/rs6000/rtems.h: Support for custom RTEMS multilibs. 48 Support TARGET_E500. 49 * config/rs6000/t-rtems: Custom RTEMS multilibs. 50 51 Ralf Corsépius <ralf.corsepius@rtems.org> 52 53 * config/mips/elf.h: Remove NO_IMPLICIT_EXTERN_C. 54 55 No newline at end of file -
gcc/config/arm/rtems-elf.h
diff -Naur gcc-4.4.6.orig/gcc/config/arm/rtems-elf.h gcc-4.4.6/gcc/config/arm/rtems-elf.h
old new 36 36 */ 37 37 #undef SUBTARGET_EXTRA_ASM_SPEC 38 38 #define SUBTARGET_EXTRA_ASM_SPEC "\ 39 %{!mhard-float: %{!m soft-float:-mfpu=softfpa}}"39 %{!mhard-float: %{!mfpu=vfp: %{!msoft-float:-mfpu=softfpa}}}" 40 40 41 41 /* 42 42 * The default includes --start-group and --end-group which conflicts -
gcc/config/arm/t-rtems
diff -Naur gcc-4.4.6.orig/gcc/config/arm/t-rtems gcc-4.4.6/gcc/config/arm/t-rtems
old new 5 5 MULTILIB_EXCEPTIONS = 6 6 MULTILIB_MATCHES = marm=mno-thumb 7 7 8 MULTILIB_OPTIONS += msoft-float/mhard-float 9 MULTILIB_DIRNAMES += soft fpu 10 MULTILIB_EXCEPTIONS += *mthumb/*mhard-float* 8 MULTILIB_OPTIONS += mhard-float/mfloat-abi=softfp 9 MULTILIB_DIRNAMES += fpu softfp 10 MULTILIB_EXCEPTIONS += *mthumb*/*mhard-float* *mthumb*/*mfloat-abi=softfp* 11 MULTILIB_MATCHES = 12 13 MULTILIB_OPTIONS += mfpu=vfp 14 MULTILIB_DIRNAMES += vfp 15 MULTILIB_EXCEPTIONS += *mhard-float*/*mfpu=vfp* *marm*/*mfloat-abi=softfp*/*mfpu=fpa* 16 MULTILIB_EXCLUSIONS += !mthumb/mfloat-abi=softfp/!mfpu=vfp 17 18 # default float model is fpa, so don't create a explicit copy of it 19 MULTILIB_EXCEPTIONS += *marm*/*mfpa* 20 21 # permutations of the options which are useful (+) or make no sense (-), 22 # defaults are in brackets: 23 # + (arm/soft/fpa) 24 # + (arm/soft)/vfp 25 # - (arm)/softfp(/fpa) 26 # + (arm)/softfp/vfp 27 # + (arm)/hard-float(/fpa) 28 # - (arm)/hard-float/vfp 29 # + thumb/(soft/fpa) 30 # + thumb/(soft/)vfp 31 # - thumb/softfp/fpa 32 # - thumb/softfp/vfp 33 # - thumb/hard-float/fpa 34 # - thumb/hard-float/vfp 35 36 # subdirs to be used for multilibs and their respective options: 37 #/thumb/vfp -> thumb/soft/vfp 38 #/thumb/fpa -> thumb/soft/fpa 39 #/thumb -> thumb/soft/fpa 40 #/vfp -> arm/soft/vfp 41 #/softfp/vfp -> arm/softfp/cfp 42 #/fpu/fpa -> arm/hard/fpa 43 #/fpu -> arm/hard/fpa 44 #/fpa -> arm/soft/fpa 45 #. -> arm/soft/fpa -
gcc/config/avr/avr.h
diff -Naur gcc-4.4.6.orig/gcc/config/avr/avr.h gcc-4.4.6/gcc/config/avr/avr.h
old new 811 811 mmcu=at90can64*|\ 812 812 mmcu=at90usb64*:--pmem-wrap-around=64k}}}\ 813 813 %{!mmcu*: -m avr2}\ 814 %{mmcu=at90s1200|\ 814 %{mmcu=avr1|\ 815 mmcu=at90s1200|\ 815 816 mmcu=attiny11|\ 816 817 mmcu=attiny12|\ 817 818 mmcu=attiny15|\ 818 819 mmcu=attiny28: -m avr1}\ 819 %{mmcu=attiny22|\ 820 %{mmcu=avr2|\ 821 mmcu=avr25|\ 822 mmcu=attiny22|\ 820 823 mmcu=attiny26|\ 821 824 mmcu=at90s2*|\ 822 825 mmcu=at90s4*|\ … … 831 834 mmcu=attiny261|\ 832 835 mmcu=attiny4*|\ 833 836 mmcu=attiny8*: -m avr2}\ 834 %{mmcu=atmega103|\ 837 %{mmcu=avr3|\ 838 mmcu=avr31|\ 839 mmcu=avr35|\ 840 mmcu=atmega103|\ 835 841 mmcu=at43*|\ 836 842 mmcu=at76*|\ 837 843 mmcu=at90usb82|\ 838 844 mmcu=at90usb162|\ 839 845 mmcu=attiny16*|\ 840 846 mmcu=attiny32*: -m avr3}\ 841 %{mmcu=atmega8*|\ 847 %{mmcu=avr4|\ 848 mmcu=atmega8*|\ 842 849 mmcu=atmega4*|\ 843 850 mmcu=at90pwm1|\ 844 851 mmcu=at90pwm2|\ … … 846 853 mmcu=at90pwm3|\ 847 854 mmcu=at90pwm3b|\ 848 855 mmcu=at90pwm81: -m avr4}\ 849 %{mmcu=atmega16*|\ 856 %{mmcu=avr5|\ 857 mmcu=avr51|\ 858 mmcu=atmega16*|\ 850 859 mmcu=atmega32*|\ 851 860 mmcu=atmega406|\ 852 861 mmcu=atmega64*|\ … … 860 869 mmcu=at94k|\ 861 870 mmcu=m3000*|\ 862 871 mmcu=m3001*: -m avr5}\ 863 %{mmcu=atmega256*:-m avr6}\ 872 %{mmcu=avr6|\ 873 mmcu=atmega256*:-m avr6}\ 864 874 %{mmcu=atmega324*|\ 865 875 mmcu=atmega325*|\ 866 876 mmcu=atmega328p|\ -
gcc/config/avr/t-rtems
diff -Naur gcc-4.4.6.orig/gcc/config/avr/t-rtems gcc-4.4.6/gcc/config/avr/t-rtems
old new 1 1 # Multilibs for avr RTEMS targets. 2 2 3 # ATM, this is just a stub 3 # RTEMS uses _exit from newlib 4 LIB1ASMFUNCS := $(filter-out _exit,$(LIB1ASMFUNCS)) -
gcc/config/lm32/arithmetic.c
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/arithmetic.c gcc-4.4.6/gcc/config/lm32/arithmetic.c
old new 1 /* Fixed-point arithmetic for Lattice Mico32. 2 Contributed by Jon Beniston <jon@beniston.com> 3 4 Copyright (C) 2008 Free Software Foundation, Inc. 5 6 This file is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2, or (at your option) any 9 later version. 10 11 In addition to the permissions in the GNU General Public License, the 12 Free Software Foundation gives you unlimited permission to link the 13 compiled version of this file into combinations with other programs, 14 and to distribute those combinations without any restriction coming 15 from the use of this file. (The General Public License restrictions 16 do apply in other respects; for example, they cover modification of 17 the file, and distribution when not linked into a combine 18 executable.) 19 20 This file is distributed in the hope that it will be useful, but 21 WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with this program; see the file COPYING. If not, write to 27 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 28 Boston, MA 02110-1301, USA. */ 29 30 typedef unsigned long UQItype __attribute__ ((mode (QI))); 31 typedef long SItype __attribute__ ((mode (SI))); 32 typedef unsigned long USItype __attribute__ ((mode (SI))); 33 34 /* Prototypes */ 35 36 USItype __mulsi3 (USItype a, USItype b); 37 38 USItype __udivmodsi4 (USItype num, USItype den, int modwanted); 39 SItype __divsi3 (SItype a, SItype b); 40 SItype __modsi3 (SItype a, SItype b); 41 USItype __udivsi3 (USItype a, USItype b); 42 USItype __umodsi3 (USItype a, USItype b); 43 44 SItype __ashlsi3 (SItype a, SItype b); 45 SItype __ashrsi3 (SItype a, SItype b); 46 USItype __lshrsi3 (USItype a, USItype b); 47 48 /* Multiplication */ 49 50 #ifdef L_mulsi3 51 USItype 52 __mulsi3 (USItype a, USItype b) 53 { 54 USItype result; 55 56 result = 0; 57 58 if (a==0) 59 return 0; 60 61 while (b!=0) 62 { 63 if (b & 1) 64 result += a; 65 a <<= 1; 66 b >>= 1; 67 } 68 69 return result; 70 } 71 #endif 72 73 /* Division */ 74 75 #ifdef L_udivmodsi4 76 USItype 77 __udivmodsi4 (USItype num, USItype den, int modwanted) 78 { 79 USItype bit = 1; 80 USItype res = 0; 81 82 while (den < num && bit && !(den & (1L<<31))) 83 { 84 den <<=1; 85 bit <<=1; 86 } 87 while (bit) 88 { 89 if (num >= den) 90 { 91 num -= den; 92 res |= bit; 93 } 94 bit >>=1; 95 den >>=1; 96 } 97 if (modwanted) 98 return num; 99 return res; 100 } 101 #endif 102 103 #ifdef L_divsi3 104 105 static const UQItype __divsi3_table[] = { 106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 107 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109 0, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 110 0, 4, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 111 0, 5, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 112 0, 6, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 113 0, 7, 3, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 114 0, 8, 4, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 115 0, 9, 4, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 116 0, 10, 5, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 117 0, 11, 5, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 118 0, 12, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 119 0, 13, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 120 0, 14, 7, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 121 0, 15, 7, 5, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 122 }; 123 124 SItype 125 __divsi3 (SItype a, SItype b) 126 { 127 int neg = 0; 128 SItype res; 129 int cfg; 130 131 if (b == 0) 132 { 133 /* Raise divide by zero exception */ 134 int eba; 135 __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba)); 136 eba += 32 * 5; 137 __asm__ __volatile__ ("mv ea, ra"); 138 __asm__ __volatile__ ("b %0" : : "r" (eba)); 139 } 140 141 if (((USItype)(a | b)) < 16) 142 { 143 res = __divsi3_table[(a << 4) + b]; 144 } 145 else 146 { 147 148 if (a < 0) 149 { 150 a = -a; 151 neg = !neg; 152 } 153 154 if (b < 0) 155 { 156 b = -b; 157 neg = !neg; 158 } 159 160 __asm__ ("rcsr %0, CFG" : "=r" (cfg)); 161 if (cfg & 2) 162 __asm__ ("divu %0, %1, %2" : "=r" (res) : "r" (a), "r" (b)); 163 else 164 res = __udivmodsi4 (a, b, 0); 165 166 if (neg) 167 res = -res; 168 } 169 170 return res; 171 } 172 #endif 173 174 #ifdef L_modsi3 175 SItype 176 __modsi3 (SItype a, SItype b) 177 { 178 int neg = 0; 179 SItype res; 180 int cfg; 181 182 if (b == 0) 183 { 184 /* Raise divide by zero exception */ 185 int eba, sr; 186 /* Save interrupt enable */ 187 __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr)); 188 sr = (sr & 1) << 1; 189 __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr)); 190 /* Branch to exception handler */ 191 __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba)); 192 eba += 32 * 5; 193 __asm__ __volatile__ ("mv ea, ra"); 194 __asm__ __volatile__ ("b %0" : : "r" (eba)); 195 } 196 197 if (a < 0) 198 { 199 a = -a; 200 neg = 1; 201 } 202 203 if (b < 0) 204 b = -b; 205 206 __asm__ ("rcsr %0, CFG" : "=r" (cfg)); 207 if (cfg & 2) 208 __asm__ ("modu %0, %1, %2" : "=r" (res) : "r" (a), "r" (b)); 209 else 210 res = __udivmodsi4 (a, b, 1); 211 212 if (neg) 213 res = -res; 214 215 return res; 216 } 217 #endif 218 219 #ifdef L_udivsi3 220 USItype 221 __udivsi3 (USItype a, USItype b) 222 { 223 if (b == 0) 224 { 225 /* Raise divide by zero exception */ 226 int eba, sr; 227 /* Save interrupt enable */ 228 __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr)); 229 sr = (sr & 1) << 1; 230 __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr)); 231 /* Branch to exception handler */ 232 __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba)); 233 eba += 32 * 5; 234 __asm__ __volatile__ ("mv ea, ra"); 235 __asm__ __volatile__ ("b %0" : : "r" (eba)); 236 } 237 238 return __udivmodsi4 (a, b, 0); 239 } 240 #endif 241 242 #ifdef L_umodsi3 243 USItype 244 __umodsi3 (USItype a, USItype b) 245 { 246 if (b == 0) 247 { 248 /* Raise divide by zero exception */ 249 int eba, sr; 250 /* Save interrupt enable */ 251 __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr)); 252 sr = (sr & 1) << 1; 253 __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr)); 254 /* Branch to exception handler */ 255 __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba)); 256 eba += 32 * 5; 257 __asm__ __volatile__ ("mv ea, ra"); 258 __asm__ __volatile__ ("b %0" : : "r" (eba)); 259 } 260 261 return __udivmodsi4 (a, b, 1); 262 } 263 #endif 264 265 #if 0 266 267 /* Shifts - Optimized versions implemented in assembly. Use these if code space is preferred to performance. */ 268 269 #ifdef L_ashlsi3 270 SItype 271 __ashlsi3 (SItype a, SItype b) 272 { 273 int i; 274 275 for (i = (b & 0x1f); i > 0; --i) 276 a += a; 277 return a; 278 } 279 #endif 280 281 #ifdef L_ashrsi3 282 SItype 283 __ashrsi3 (SItype a, SItype b) 284 { 285 int i; 286 287 for (i = (b & 0x1f); i > 0; --i) 288 __asm__ ("sri %0, %0, 1" : "=r" (a) : "0" (a)); 289 return a; 290 } 291 #endif 292 293 #ifdef L_lshrsi3 294 USItype 295 __lshrsi3 (USItype a, USItype b) 296 { 297 int i; 298 299 for (i = (b & 0x1f); i > 0; --i) 300 __asm__ ("srui %0, %0, 1" : "=r" (a) : "0" (a)); 301 return a; 302 } 303 #endif 304 305 #endif -
gcc/config/lm32/crti.S
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/crti.S gcc-4.4.6/gcc/config/lm32/crti.S
old new 1 # crti.S for Lattice Mico32 2 # Contributed by Jon Beniston <jon@beniston.com> 3 # 4 # Copyright (C) 2008 Free Software Foundation, Inc. 5 # 6 # This file is free software; you can redistribute it and/or modify it 7 # under the terms of the GNU General Public License as published by the 8 # Free Software Foundation; either version 2, or (at your option) any 9 # later version. 10 # 11 # In addition to the permissions in the GNU General Public License, the 12 # Free Software Foundation gives you unlimited permission to link the 13 # compiled version of this file into combinations with other programs, 14 # and to distribute those combinations without any restriction coming 15 # from the use of this file. (The General Public License restrictions 16 # do apply in other respects; for example, they cover modification of 17 # the file, and distribution when not linked into a combine 18 # executable.) 19 # 20 # This file is distributed in the hope that it will be useful, but 21 # WITHOUT ANY WARRANTY; without even the implied warranty of 22 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 # General Public License for more details. 24 # 25 # You should have received a copy of the GNU General Public License 26 # along with this program; see the file COPYING. If not, write to 27 # the Free Software Foundation, 51 Franklin Street, Fifth Floor, 28 # Boston, MA 02110-1301, USA. 29 # 30 31 .section .init 32 .global _init 33 .type _init,@function 34 .align 4 35 _init: 36 addi sp, sp, -4 37 sw (sp+4), ra 38 39 .section .fini 40 .global _fini 41 .type _fini,@function 42 .align 4 43 _fini: 44 addi sp, sp, -4 45 sw (sp+4), ra -
gcc/config/lm32/crtn.S
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/crtn.S gcc-4.4.6/gcc/config/lm32/crtn.S
old new 1 # crtn.S for Lattice Mico32 2 # Contributed by Jon Beniston <jon@beniston.com> 3 # 4 # Copyright (C) 2008 Free Software Foundation, Inc. 5 # 6 # This file is free software; you can redistribute it and/or modify it 7 # under the terms of the GNU General Public License as published by the 8 # Free Software Foundation; either version 2, or (at your option) any 9 # later version. 10 # 11 # In addition to the permissions in the GNU General Public License, the 12 # Free Software Foundation gives you unlimited permission to link the 13 # compiled version of this file into combinations with other programs, 14 # and to distribute those combinations without any restriction coming 15 # from the use of this file. (The General Public License restrictions 16 # do apply in other respects; for example, they cover modification of 17 # the file, and distribution when not linked into a combine 18 # executable.) 19 # 20 # This file is distributed in the hope that it will be useful, but 21 # WITHOUT ANY WARRANTY; without even the implied warranty of 22 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 # General Public License for more details. 24 # 25 # You should have received a copy of the GNU General Public License 26 # along with this program; see the file COPYING. If not, write to 27 # the Free Software Foundation, 51 Franklin Street, Fifth Floor, 28 # Boston, MA 02110-1301, USA. 29 # 30 31 .section .init 32 33 lw ra, (sp+4) 34 addi sp, sp, 4 35 ret 36 37 .section .fini 38 39 lw ra, (sp+4) 40 addi sp, sp, 4 41 ret 42 -
gcc/config/lm32/lib1funcs.S
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lib1funcs.S gcc-4.4.6/gcc/config/lm32/lib1funcs.S
old new 1 # lib1funcs.S for Lattice Mico32 2 # Contributed by Jon Beniston <jon@beniston.com> 3 # 4 # Copyright (C) 2008 Free Software Foundation, Inc. 5 # 6 # This file is free software; you can redistribute it and/or modify it 7 # under the terms of the GNU General Public License as published by the 8 # Free Software Foundation; either version 2, or (at your option) any 9 # later version. 10 # 11 # In addition to the permissions in the GNU General Public License, the 12 # Free Software Foundation gives you unlimited permission to link the 13 # compiled version of this file into combinations with other programs, 14 # and to distribute those combinations without any restriction coming 15 # from the use of this file. (The General Public License restrictions 16 # do apply in other respects; for example, they cover modification of 17 # the file, and distribution when not linked into a combine 18 # executable.) 19 # 20 # This file is distributed in the hope that it will be useful, but 21 # WITHOUT ANY WARRANTY; without even the implied warranty of 22 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 # General Public License for more details. 24 # 25 # You should have received a copy of the GNU General Public License 26 # along with this program; see the file COPYING. If not, write to 27 # the Free Software Foundation, 51 Franklin Street, Fifth Floor, 28 # Boston, MA 02110-1301, USA. 29 # 30 31 /* Arithmetic left shift */ 32 33 .text 34 35 .global __ashlsi3 36 .type __ashlsi3,@function 37 .align 4 38 39 __ashlsi3: 40 /* Only use 5 LSBs, as that's all the h/w shifter uses */ 41 andi r2, r2, 0x1f 42 /* Get address of offset into unrolled shift loop to jump to */ 43 #ifdef __PIC__ 44 orhi r3, r0, gotoffhi16(__ashlsi3_table) 45 addi r3, r3, gotofflo16(__ashlsi3_table) 46 add r3, r3, gp 47 #else 48 mvhi r3, hi(__ashlsi3_table) 49 ori r3, r3, lo(__ashlsi3_table) 50 #endif 51 add r2, r2, r2 52 add r2, r2, r2 53 add r3, r3, r2 54 lw r3, (r3+0) 55 b r3 56 57 __ashlsi3_31: 58 add r1, r1, r1 59 __ashlsi3_30: 60 add r1, r1, r1 61 __ashlsi3_29: 62 add r1, r1, r1 63 __ashlsi3_28: 64 add r1, r1, r1 65 __ashlsi3_27: 66 add r1, r1, r1 67 __ashlsi3_26: 68 add r1, r1, r1 69 __ashlsi3_25: 70 add r1, r1, r1 71 __ashlsi3_24: 72 add r1, r1, r1 73 __ashlsi3_23: 74 add r1, r1, r1 75 __ashlsi3_22: 76 add r1, r1, r1 77 __ashlsi3_21: 78 add r1, r1, r1 79 __ashlsi3_20: 80 add r1, r1, r1 81 __ashlsi3_19: 82 add r1, r1, r1 83 __ashlsi3_18: 84 add r1, r1, r1 85 __ashlsi3_17: 86 add r1, r1, r1 87 __ashlsi3_16: 88 add r1, r1, r1 89 __ashlsi3_15: 90 add r1, r1, r1 91 __ashlsi3_14: 92 add r1, r1, r1 93 __ashlsi3_13: 94 add r1, r1, r1 95 __ashlsi3_12: 96 add r1, r1, r1 97 __ashlsi3_11: 98 add r1, r1, r1 99 __ashlsi3_10: 100 add r1, r1, r1 101 __ashlsi3_9: 102 add r1, r1, r1 103 __ashlsi3_8: 104 add r1, r1, r1 105 __ashlsi3_7: 106 add r1, r1, r1 107 __ashlsi3_6: 108 add r1, r1, r1 109 __ashlsi3_5: 110 add r1, r1, r1 111 __ashlsi3_4: 112 add r1, r1, r1 113 __ashlsi3_3: 114 add r1, r1, r1 115 __ashlsi3_2: 116 add r1, r1, r1 117 __ashlsi3_1: 118 add r1, r1, r1 119 __ashlsi3_0: 120 ret 121 122 #ifdef __PIC__ 123 .section .data 124 #else 125 .section .rodata 126 #endif 127 128 .align 4 129 130 __ashlsi3_table: 131 .word __ashlsi3_0 132 .word __ashlsi3_1 133 .word __ashlsi3_2 134 .word __ashlsi3_3 135 .word __ashlsi3_4 136 .word __ashlsi3_5 137 .word __ashlsi3_6 138 .word __ashlsi3_7 139 .word __ashlsi3_8 140 .word __ashlsi3_9 141 .word __ashlsi3_10 142 .word __ashlsi3_11 143 .word __ashlsi3_12 144 .word __ashlsi3_13 145 .word __ashlsi3_14 146 .word __ashlsi3_15 147 .word __ashlsi3_16 148 .word __ashlsi3_17 149 .word __ashlsi3_18 150 .word __ashlsi3_19 151 .word __ashlsi3_20 152 .word __ashlsi3_21 153 .word __ashlsi3_22 154 .word __ashlsi3_23 155 .word __ashlsi3_24 156 .word __ashlsi3_25 157 .word __ashlsi3_26 158 .word __ashlsi3_27 159 .word __ashlsi3_28 160 .word __ashlsi3_29 161 .word __ashlsi3_30 162 .word __ashlsi3_31 163 164 /* Logical right shift */ 165 166 .text 167 168 .global __lshrsi3 169 .type __lshrsi3,@function 170 .align 4 171 172 __lshrsi3: 173 /* Only use 5 LSBs, as that's all the h/w shifter uses */ 174 andi r2, r2, 0x1f 175 /* Get address of offset into unrolled shift loop to jump to */ 176 #ifdef __PIC__ 177 orhi r3, r0, gotoffhi16(__lshrsi3_table) 178 addi r3, r3, gotofflo16(__lshrsi3_table) 179 add r3, r3, gp 180 #else 181 mvhi r3, hi(__lshrsi3_table) 182 ori r3, r3, lo(__lshrsi3_table) 183 #endif 184 add r2, r2, r2 185 add r2, r2, r2 186 add r3, r3, r2 187 lw r3, (r3+0) 188 b r3 189 190 __lshrsi3_31: 191 srui r1, r1, 1 192 __lshrsi3_30: 193 srui r1, r1, 1 194 __lshrsi3_29: 195 srui r1, r1, 1 196 __lshrsi3_28: 197 srui r1, r1, 1 198 __lshrsi3_27: 199 srui r1, r1, 1 200 __lshrsi3_26: 201 srui r1, r1, 1 202 __lshrsi3_25: 203 srui r1, r1, 1 204 __lshrsi3_24: 205 srui r1, r1, 1 206 __lshrsi3_23: 207 srui r1, r1, 1 208 __lshrsi3_22: 209 srui r1, r1, 1 210 __lshrsi3_21: 211 srui r1, r1, 1 212 __lshrsi3_20: 213 srui r1, r1, 1 214 __lshrsi3_19: 215 srui r1, r1, 1 216 __lshrsi3_18: 217 srui r1, r1, 1 218 __lshrsi3_17: 219 srui r1, r1, 1 220 __lshrsi3_16: 221 srui r1, r1, 1 222 __lshrsi3_15: 223 srui r1, r1, 1 224 __lshrsi3_14: 225 srui r1, r1, 1 226 __lshrsi3_13: 227 srui r1, r1, 1 228 __lshrsi3_12: 229 srui r1, r1, 1 230 __lshrsi3_11: 231 srui r1, r1, 1 232 __lshrsi3_10: 233 srui r1, r1, 1 234 __lshrsi3_9: 235 srui r1, r1, 1 236 __lshrsi3_8: 237 srui r1, r1, 1 238 __lshrsi3_7: 239 srui r1, r1, 1 240 __lshrsi3_6: 241 srui r1, r1, 1 242 __lshrsi3_5: 243 srui r1, r1, 1 244 __lshrsi3_4: 245 srui r1, r1, 1 246 __lshrsi3_3: 247 srui r1, r1, 1 248 __lshrsi3_2: 249 srui r1, r1, 1 250 __lshrsi3_1: 251 srui r1, r1, 1 252 __lshrsi3_0: 253 ret 254 255 #ifdef __PIC__ 256 .section .data 257 #else 258 .section .rodata 259 #endif 260 261 .align 4 262 263 __lshrsi3_table: 264 .word __lshrsi3_0 265 .word __lshrsi3_1 266 .word __lshrsi3_2 267 .word __lshrsi3_3 268 .word __lshrsi3_4 269 .word __lshrsi3_5 270 .word __lshrsi3_6 271 .word __lshrsi3_7 272 .word __lshrsi3_8 273 .word __lshrsi3_9 274 .word __lshrsi3_10 275 .word __lshrsi3_11 276 .word __lshrsi3_12 277 .word __lshrsi3_13 278 .word __lshrsi3_14 279 .word __lshrsi3_15 280 .word __lshrsi3_16 281 .word __lshrsi3_17 282 .word __lshrsi3_18 283 .word __lshrsi3_19 284 .word __lshrsi3_20 285 .word __lshrsi3_21 286 .word __lshrsi3_22 287 .word __lshrsi3_23 288 .word __lshrsi3_24 289 .word __lshrsi3_25 290 .word __lshrsi3_26 291 .word __lshrsi3_27 292 .word __lshrsi3_28 293 .word __lshrsi3_29 294 .word __lshrsi3_30 295 .word __lshrsi3_31 296 297 /* Arithmetic right shift */ 298 299 .text 300 301 .global __ashrsi3 302 .type __ashrsi3,@function 303 .align 4 304 305 __ashrsi3: 306 /* Only use 5 LSBs, as that's all the h/w shifter uses */ 307 andi r2, r2, 0x1f 308 /* Get address of offset into unrolled shift loop to jump to */ 309 #ifdef __PIC__ 310 orhi r3, r0, gotoffhi16(__ashrsi3_table) 311 addi r3, r3, gotofflo16(__ashrsi3_table) 312 add r3, r3, gp 313 #else 314 mvhi r3, hi(__ashrsi3_table) 315 ori r3, r3, lo(__ashrsi3_table) 316 #endif 317 add r2, r2, r2 318 add r2, r2, r2 319 add r3, r3, r2 320 lw r3, (r3+0) 321 b r3 322 323 __ashrsi3_31: 324 sri r1, r1, 1 325 __ashrsi3_30: 326 sri r1, r1, 1 327 __ashrsi3_29: 328 sri r1, r1, 1 329 __ashrsi3_28: 330 sri r1, r1, 1 331 __ashrsi3_27: 332 sri r1, r1, 1 333 __ashrsi3_26: 334 sri r1, r1, 1 335 __ashrsi3_25: 336 sri r1, r1, 1 337 __ashrsi3_24: 338 sri r1, r1, 1 339 __ashrsi3_23: 340 sri r1, r1, 1 341 __ashrsi3_22: 342 sri r1, r1, 1 343 __ashrsi3_21: 344 sri r1, r1, 1 345 __ashrsi3_20: 346 sri r1, r1, 1 347 __ashrsi3_19: 348 sri r1, r1, 1 349 __ashrsi3_18: 350 sri r1, r1, 1 351 __ashrsi3_17: 352 sri r1, r1, 1 353 __ashrsi3_16: 354 sri r1, r1, 1 355 __ashrsi3_15: 356 sri r1, r1, 1 357 __ashrsi3_14: 358 sri r1, r1, 1 359 __ashrsi3_13: 360 sri r1, r1, 1 361 __ashrsi3_12: 362 sri r1, r1, 1 363 __ashrsi3_11: 364 sri r1, r1, 1 365 __ashrsi3_10: 366 sri r1, r1, 1 367 __ashrsi3_9: 368 sri r1, r1, 1 369 __ashrsi3_8: 370 sri r1, r1, 1 371 __ashrsi3_7: 372 sri r1, r1, 1 373 __ashrsi3_6: 374 sri r1, r1, 1 375 __ashrsi3_5: 376 sri r1, r1, 1 377 __ashrsi3_4: 378 sri r1, r1, 1 379 __ashrsi3_3: 380 sri r1, r1, 1 381 __ashrsi3_2: 382 sri r1, r1, 1 383 __ashrsi3_1: 384 sri r1, r1, 1 385 __ashrsi3_0: 386 ret 387 388 #ifdef __PIC__ 389 .section .data 390 #else 391 .section .rodata 392 #endif 393 394 .align 4 395 396 __ashrsi3_table: 397 .word __ashrsi3_0 398 .word __ashrsi3_1 399 .word __ashrsi3_2 400 .word __ashrsi3_3 401 .word __ashrsi3_4 402 .word __ashrsi3_5 403 .word __ashrsi3_6 404 .word __ashrsi3_7 405 .word __ashrsi3_8 406 .word __ashrsi3_9 407 .word __ashrsi3_10 408 .word __ashrsi3_11 409 .word __ashrsi3_12 410 .word __ashrsi3_13 411 .word __ashrsi3_14 412 .word __ashrsi3_15 413 .word __ashrsi3_16 414 .word __ashrsi3_17 415 .word __ashrsi3_18 416 .word __ashrsi3_19 417 .word __ashrsi3_20 418 .word __ashrsi3_21 419 .word __ashrsi3_22 420 .word __ashrsi3_23 421 .word __ashrsi3_24 422 .word __ashrsi3_25 423 .word __ashrsi3_26 424 .word __ashrsi3_27 425 .word __ashrsi3_28 426 .word __ashrsi3_29 427 .word __ashrsi3_30 428 .word __ashrsi3_31 429 -
gcc/config/lm32/lm32.c
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.c gcc-4.4.6/gcc/config/lm32/lm32.c
old new 1 /* Subroutines used for code generation on the Lattice Mico32 architecture. 2 Contributed by Jon Beniston <jon@beniston.com> 3 4 Copyright (C) 2008 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #include "config.h" 23 #include "system.h" 24 #include "coretypes.h" 25 #include "tm.h" 26 #include "rtl.h" 27 #include "regs.h" 28 #include "hard-reg-set.h" 29 #include "basic-block.h" 30 #include "real.h" 31 #include "insn-config.h" 32 #include "conditions.h" 33 #include "insn-flags.h" 34 #include "insn-attr.h" 35 #include "insn-codes.h" 36 #include "recog.h" 37 #include "output.h" 38 #include "tree.h" 39 #include "expr.h" 40 #include "flags.h" 41 #include "reload.h" 42 #include "tm_p.h" 43 #include "function.h" 44 #include "toplev.h" 45 #include "optabs.h" 46 #include "libfuncs.h" 47 #include "ggc.h" 48 #include "target.h" 49 #include "target-def.h" 50 #include "langhooks.h" 51 #include "tm-constrs.h" 52 #include "df.h" 53 54 struct lm32_frame_info 55 { 56 HOST_WIDE_INT total_size; /* number of bytes that the entire frame takes up. */ 57 HOST_WIDE_INT callee_size; /* number of bytes to save callee save registers */ 58 HOST_WIDE_INT pretend_size; /* number of bytes we push and pretend caller did. */ 59 HOST_WIDE_INT args_size; /* number of bytes that outgoing arguments take up. */ 60 HOST_WIDE_INT locals_size; /* number of bytes that local variables take up. */ 61 unsigned int reg_save_mask; /* mask of saved registers. */ 62 }; 63 64 /* Prototypes for static functions */ 65 static rtx emit_add (rtx dest, rtx src0, rtx src1); 66 static void expand_save_restore (struct lm32_frame_info *info, int op); 67 static void abort_with_insn (rtx insn, const char *reason); 68 static void stack_adjust (HOST_WIDE_INT amount); 69 static bool lm32_in_small_data_p (const_tree); 70 static void lm32_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 71 tree type, int *pretend_size, int no_rtl); 72 73 /* Detemines if given constant can be used as a displacement */ 74 #define OFFSET_INT(X) (((X) > -32768) && ((X) < 32768)) 75 76 #undef TARGET_ADDRESS_COST 77 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 78 #undef TARGET_IN_SMALL_DATA_P 79 #define TARGET_IN_SMALL_DATA_P lm32_in_small_data_p 80 #undef TARGET_PROMOTE_FUNCTION_ARGS 81 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true 82 #undef TARGET_PROMOTE_FUNCTION_RETURN 83 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true 84 #undef TARGET_SETUP_INCOMING_VARARGS 85 #define TARGET_SETUP_INCOMING_VARARGS lm32_setup_incoming_varargs 86 #undef TARGET_PROMOTE_PROTOTYPES 87 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true 88 89 struct gcc_target targetm = TARGET_INITIALIZER; 90 91 /* Current frame information calculated by lm32_compute_frame_size. */ 92 static struct lm32_frame_info current_frame_info; 93 94 rtx lm32_compare_op0; 95 rtx lm32_compare_op1; 96 97 /* Return non-zero if the specified return type should be returned in memory */ 98 int 99 lm32_return_in_memory (tree type) 100 { 101 HOST_WIDE_INT size; 102 103 if (!AGGREGATE_TYPE_P (type)) 104 { 105 /* All simple types are returned in registers. */ 106 return 0; 107 } 108 109 size = int_size_in_bytes (type); 110 if (size >=0 && size <= UNITS_PER_WORD) 111 { 112 /* If it can fit in one register */ 113 return 0; 114 } 115 116 return 1; 117 } 118 119 /* Determine if given constant can be used as a register displacement */ 120 int 121 const_ok_for_base_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 122 { 123 int val; 124 125 val = INTVAL (op); 126 return OFFSET_INT (val); 127 } 128 129 /* Generate an emit a word sized add instruction */ 130 static rtx 131 emit_add (rtx dest, rtx src0, rtx src1) 132 { 133 rtx insn; 134 insn = emit_insn (gen_addsi3 (dest, src0, src1)); 135 return insn; 136 } 137 138 /* Generate the code to compare (and possibly branch) two integer values 139 TEST_CODE is the comparison code we are trying to emulate 140 (or implement directly) 141 RESULT is where to store the result of the comparison, 142 or null to emit a branch 143 CMP0 CMP1 are the two comparison operands 144 DESTINATION is the destination of the branch, or null to only compare 145 */ 146 147 void 148 gen_int_relational (enum rtx_code code, /* relational test (EQ, etc) */ 149 rtx result, /* result to store comp. or 0 if branch */ 150 rtx cmp0, /* first operand to compare */ 151 rtx cmp1, /* second operand to compare */ 152 rtx destination) /* destination of the branch, or 0 if compare */ 153 { 154 enum machine_mode mode; 155 int branch_p; 156 157 mode = GET_MODE (cmp0); 158 if (mode == VOIDmode) 159 mode = GET_MODE (cmp1); 160 161 /* Is this a branch or compare */ 162 branch_p = (destination != 0); 163 164 /* Instruction set doesn't support LE or LT, so swap operands and use GE, GT */ 165 switch (code) 166 { 167 case LE: 168 case LT: 169 case LEU: 170 case LTU: 171 code = swap_condition (code); 172 rtx temp = cmp0; 173 cmp0 = cmp1; 174 cmp1 = temp; 175 break; 176 default: 177 break; 178 } 179 180 if (branch_p) 181 { 182 rtx insn; 183 184 /* Operands must be in registers */ 185 if (!register_operand (cmp0, mode)) 186 cmp0 = force_reg (mode, cmp0); 187 if (!register_operand (cmp1, mode)) 188 cmp1 = force_reg (mode, cmp1); 189 190 /* Generate conditional branch instruction */ 191 rtx cond = gen_rtx_fmt_ee (code, mode, cmp0, cmp1); 192 rtx label = gen_rtx_LABEL_REF (VOIDmode, destination); 193 insn = gen_rtx_SET (VOIDmode, pc_rtx, 194 gen_rtx_IF_THEN_ELSE (VOIDmode, 195 cond, label, pc_rtx)); 196 emit_jump_insn (insn); 197 } 198 else 199 { 200 /* We can't have const_ints in cmp0, other than 0 */ 201 if ((GET_CODE (cmp0) == CONST_INT) && (INTVAL (cmp0) != 0)) 202 cmp0 = force_reg (mode, cmp0); 203 204 /* If the comparison is against an int not in legal range 205 move it into a register */ 206 if (GET_CODE (cmp1) == CONST_INT) 207 { 208 HOST_WIDE_INT value = INTVAL (cmp1); 209 switch (code) 210 { 211 case EQ: case NE: case LE: case LT: case GE: case GT: 212 if (!MEDIUM_INT(value)) 213 cmp1 = force_reg (mode, cmp1); 214 break; 215 case LEU: case LTU: case GEU: case GTU: 216 if (!MEDIUM_UINT(value)) 217 cmp1 = force_reg (mode, cmp1); 218 break; 219 default: 220 abort (); 221 } 222 } 223 224 /* Generate compare instruction */ 225 emit_move_insn (result, gen_rtx_fmt_ee (code, mode, cmp0, cmp1)); 226 } 227 } 228 229 /* Generate and emit RTL to save or restore callee save registers */ 230 static void 231 expand_save_restore (struct lm32_frame_info *info, int op) 232 { 233 unsigned int reg_save_mask = info->reg_save_mask; 234 int regno; 235 HOST_WIDE_INT offset; 236 rtx insn; 237 238 /* Callee saves are below locals and above outgoing arguments */ 239 offset = info->args_size + info->callee_size; 240 for (regno = 0; regno <= 31; regno++) 241 { 242 if ((reg_save_mask & (1 << regno)) != 0) 243 { 244 if (op == 0) 245 { 246 insn = emit_move_insn (gen_rtx_MEM (word_mode, 247 gen_rtx_PLUS (Pmode, 248 stack_pointer_rtx, 249 GEN_INT (offset))), 250 gen_rtx_REG (word_mode, regno)); 251 } 252 else 253 { 254 insn = emit_move_insn (gen_rtx_REG (word_mode, regno), 255 gen_rtx_MEM (word_mode, 256 gen_rtx_PLUS (Pmode, 257 stack_pointer_rtx, 258 GEN_INT (offset)))); 259 } 260 261 /* only prologue instructions which set the sp fp or save a 262 register should be marked as frame related */ 263 if (op==0) 264 RTX_FRAME_RELATED_P (insn) = 1; 265 offset -= UNITS_PER_WORD; 266 } 267 } 268 } 269 270 static void 271 stack_adjust (HOST_WIDE_INT amount) 272 { 273 rtx insn; 274 275 if (!MEDIUM_INT (amount)) 276 { 277 /* r10 is caller saved so it can be used as a temp reg */ 278 rtx r10; 279 r10 = gen_rtx_REG (word_mode, 10); 280 insn = emit_move_insn (r10, GEN_INT (amount)); 281 if (amount < 0) 282 RTX_FRAME_RELATED_P (insn) = 1; 283 insn = emit_add (stack_pointer_rtx, stack_pointer_rtx, r10); 284 if (amount < 0) 285 RTX_FRAME_RELATED_P (insn) = 1; 286 } 287 else 288 { 289 insn = emit_add (stack_pointer_rtx, 290 stack_pointer_rtx, 291 GEN_INT (amount)); 292 if (amount < 0) 293 RTX_FRAME_RELATED_P (insn) = 1; 294 } 295 } 296 297 298 /* Create and emit instructions for a functions prologue */ 299 void 300 lm32_expand_prologue (void) 301 { 302 rtx insn; 303 304 lm32_compute_frame_size (get_frame_size ()); 305 306 if (current_frame_info.total_size > 0) 307 { 308 /* Add space on stack new frame */ 309 stack_adjust (-current_frame_info.total_size); 310 311 /* Save callee save registers */ 312 if (current_frame_info.reg_save_mask != 0) 313 expand_save_restore (¤t_frame_info, 0); 314 315 /* Setup frame pointer if it's needed */ 316 if (frame_pointer_needed == 1) 317 { 318 /* Load offset - Don't use total_size, as that includes pretend_size, which isn't part of this frame? */ 319 insn = emit_move_insn (frame_pointer_rtx, GEN_INT ( current_frame_info.args_size 320 + current_frame_info.callee_size 321 + current_frame_info.locals_size)); 322 RTX_FRAME_RELATED_P (insn) = 1; 323 324 /* Add in sp */ 325 insn = emit_add (frame_pointer_rtx, 326 frame_pointer_rtx, 327 stack_pointer_rtx); 328 RTX_FRAME_RELATED_P (insn) = 1; 329 } 330 331 /* Prevent prologue from being scheduled into function body */ 332 emit_insn (gen_blockage ()); 333 } 334 } 335 336 /* Create an emit instructions for a functions epilogue */ 337 void 338 lm32_expand_epilogue (void) 339 { 340 rtx ra_rtx = gen_rtx_REG (Pmode, RA_REGNUM); 341 342 lm32_compute_frame_size (get_frame_size ()); 343 344 if (current_frame_info.total_size > 0) 345 { 346 /* Prevent stack code from being reordered */ 347 emit_insn (gen_blockage ()); 348 349 /* Restore callee save registers */ 350 if (current_frame_info.reg_save_mask != 0) 351 expand_save_restore (¤t_frame_info, 1); 352 353 /* Deallocate stack */ 354 stack_adjust (current_frame_info.total_size); 355 356 /* Return to calling function */ 357 emit_jump_insn (gen_return_internalsi (ra_rtx)); 358 } 359 else 360 { 361 /* Return to calling function */ 362 emit_jump_insn (gen_return_internalsi (ra_rtx)); 363 } 364 } 365 366 /* Return the bytes needed to compute the frame pointer from the current 367 stack pointer. */ 368 HOST_WIDE_INT 369 lm32_compute_frame_size (int size) 370 { 371 int regno; 372 HOST_WIDE_INT total_size, locals_size, args_size, pretend_size, callee_size; 373 unsigned int reg_save_mask; 374 375 locals_size = size; 376 args_size = crtl->outgoing_args_size; 377 pretend_size = crtl->args.pretend_args_size; 378 callee_size = 0; 379 reg_save_mask = 0; 380 381 /* Build mask that actually determines which regsiters we save 382 and calculate size required to store them in the stack. */ 383 for (regno = 1; regno < SP_REGNUM; regno++) 384 { 385 if (df_regs_ever_live_p(regno) && !call_used_regs[regno]) 386 { 387 reg_save_mask |= 1 << regno; 388 callee_size += UNITS_PER_WORD; 389 } 390 } 391 if (df_regs_ever_live_p(RA_REGNUM) || !current_function_is_leaf || !optimize) 392 { 393 reg_save_mask |= 1 << RA_REGNUM; 394 callee_size += UNITS_PER_WORD; 395 } 396 if (!(reg_save_mask & (1 << FP_REGNUM)) && frame_pointer_needed) 397 { 398 reg_save_mask |= 1 << FP_REGNUM; 399 callee_size += UNITS_PER_WORD; 400 } 401 402 /* Compute total frame size */ 403 total_size = pretend_size + args_size + locals_size + callee_size; 404 405 /* Align frame to appropriate boundary */ 406 total_size = (total_size+3) & ~3; 407 408 /* Save computed information. */ 409 current_frame_info.total_size = total_size; 410 current_frame_info.callee_size = callee_size; 411 current_frame_info.pretend_size = pretend_size; 412 current_frame_info.locals_size = locals_size; 413 current_frame_info.args_size = args_size; 414 current_frame_info.reg_save_mask = reg_save_mask; 415 416 return total_size; 417 } 418 419 void 420 lm32_print_operand (FILE *file, rtx op, int letter) 421 { 422 register enum rtx_code code; 423 424 if (! op) 425 { 426 error ("PRINT_OPERAND null pointer"); 427 abort (); 428 } 429 430 code = GET_CODE (op); 431 432 if (code == SIGN_EXTEND) 433 op = XEXP (op, 0), code = GET_CODE (op); 434 else if (code == REG || code == SUBREG) 435 { 436 int regnum; 437 438 if (code == REG) 439 regnum = REGNO (op); 440 else 441 regnum = true_regnum (op); 442 443 if ( (letter == 'H' && !WORDS_BIG_ENDIAN) 444 || (letter == 'L' && WORDS_BIG_ENDIAN)) 445 { 446 abort(); 447 regnum++; 448 } 449 450 fprintf (file, "%s", reg_names[regnum]); 451 } 452 else if (code == MEM) 453 output_address (XEXP (op, 0)); 454 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0) 455 fprintf (file, "%s", reg_names[0]); 456 else if (GET_CODE (op) == CONST_DOUBLE) 457 { 458 if ((CONST_DOUBLE_LOW (op) != 0) || (CONST_DOUBLE_HIGH (op) != 0)) 459 output_operand_lossage ("Only 0.0 can be loaded as an immediate"); 460 else 461 fprintf (file, "0"); 462 } 463 else if (code == EQ) 464 fprintf (file, "e "); 465 else if (code == NE) 466 fprintf (file, "ne "); 467 else if (code == GT) 468 fprintf (file, "g "); 469 else if (code == GTU) 470 fprintf (file, "gu "); 471 else if (code == LT) 472 fprintf (file, "l "); 473 else if (code == LTU) 474 fprintf (file, "lu "); 475 else if (code == GE) 476 fprintf (file, "ge "); 477 else if (code == GEU) 478 fprintf (file, "geu"); 479 else if (code == LE) 480 fprintf (file, "le "); 481 else if (code == LEU) 482 fprintf (file, "leu"); 483 else 484 output_addr_const (file, op); 485 } 486 487 /* A C compound statement to output to stdio stream STREAM the 488 assembler syntax for an instruction operand that is a memory 489 reference whose address is ADDR. ADDR is an RTL expression. 490 491 On some machines, the syntax for a symbolic address depends on 492 the section that the address refers to. On these machines, 493 define the macro `ENCODE_SECTION_INFO' to store the information 494 into the `symbol_ref', and then check for it here. */ 495 496 void 497 lm32_print_operand_address (FILE *file, rtx addr) 498 { 499 switch (GET_CODE (addr)) 500 { 501 case REG: 502 fprintf (file, "(%s+0)", reg_names [REGNO (addr)]); 503 break; 504 505 case MEM: 506 output_address (XEXP (addr, 0)); 507 break; 508 509 case PLUS: 510 { 511 rtx arg0 = XEXP (addr, 0); 512 rtx arg1 = XEXP (addr, 1); 513 514 if (GET_CODE (arg0) == REG && CONSTANT_P (arg1)) 515 { 516 if (GET_CODE(arg1) == CONST_INT) 517 fprintf (file, "(%s+%ld)", reg_names [REGNO (arg0)], INTVAL (arg1)); 518 else 519 { 520 fprintf (file, "(%s+", reg_names [REGNO (arg0)]); 521 output_addr_const (file, arg1); 522 fprintf (file, ")"); 523 } 524 } 525 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1)) 526 output_addr_const (file, addr); 527 else 528 abort_with_insn (addr, "bad operand"); 529 } 530 break; 531 532 case SYMBOL_REF: 533 if (SYMBOL_REF_SMALL_P (addr)) 534 { 535 fprintf (file, "gp("); 536 output_addr_const (file, addr); 537 fprintf (file, ")"); 538 } 539 else 540 abort_with_insn (addr, "can't use non gp relative absolute address"); 541 break; 542 543 default: 544 abort_with_insn (addr, "invalid addressing mode"); 545 break; 546 } 547 } 548 549 /* Determine where to put an argument to a function. 550 Value is zero to push the argument on the stack, 551 or a hard register in which to store the argument. 552 553 MODE is the argument's machine mode. 554 TYPE is the data type of the argument (as a tree). 555 This is null for libcalls where that information may 556 not be available. 557 CUM is a variable of type CUMULATIVE_ARGS which gives info about 558 the preceding args and about the function being called. 559 NAMED is nonzero if this argument is a named parameter 560 (otherwise it is an extra parameter matching an ellipsis). */ 561 562 rtx 563 lm32_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, 564 tree type, int named) 565 { 566 if (mode == VOIDmode) 567 /* Compute operand 2 of the call insn. */ 568 return GEN_INT (0); 569 570 if (targetm.calls.must_pass_in_stack (mode, type)) 571 return NULL_RTX; 572 573 if (!named || (cum + LM32_NUM_REGS2(mode, type) > LM32_NUM_ARG_REGS)) 574 return NULL_RTX; 575 576 return gen_rtx_REG (mode, cum + LM32_FIRST_ARG_REG); 577 } 578 579 HOST_WIDE_INT 580 lm32_compute_initial_elimination_offset (int from, int to) 581 { 582 HOST_WIDE_INT offset = 0; 583 584 switch (from) 585 { 586 /*case FRAME_POINTER_REGNUM: - Same as ARG_POINTER_REGNUM */ 587 case ARG_POINTER_REGNUM: 588 switch (to) 589 { 590 case FRAME_POINTER_REGNUM: 591 offset = 0; 592 break; 593 case STACK_POINTER_REGNUM: 594 offset = lm32_compute_frame_size (get_frame_size ()) - current_frame_info.pretend_size; 595 break; 596 default: 597 abort (); 598 } 599 break; 600 default: 601 abort (); 602 } 603 604 return offset; 605 } 606 607 static void 608 lm32_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 609 tree type, int *pretend_size, int no_rtl) 610 { 611 int first_anon_arg; 612 tree fntype; 613 int stdarg_p; 614 615 fntype = TREE_TYPE (current_function_decl); 616 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 617 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) 618 != void_type_node)); 619 620 if (stdarg_p) 621 first_anon_arg = *cum + LM32_FIRST_ARG_REG; 622 else 623 { 624 /* this is the common case, we have been passed details setup 625 for the last named argument, we want to skip over the 626 registers, if any used in passing this named paramter in 627 order to determine which is the first registers used to pass 628 anonymous arguments */ 629 int size; 630 631 if (mode==BLKmode) 632 size = int_size_in_bytes (type); 633 else 634 size = GET_MODE_SIZE (mode); 635 636 first_anon_arg = *cum + LM32_FIRST_ARG_REG + ((size + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 637 } 638 639 if ((first_anon_arg < (LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS)) && !no_rtl) 640 { 641 int first_reg_offset = first_anon_arg; 642 int size = LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS - first_anon_arg; 643 rtx regblock; 644 645 regblock = gen_rtx_MEM (BLKmode, 646 plus_constant (arg_pointer_rtx, 647 FIRST_PARM_OFFSET (0))); 648 move_block_from_reg (first_reg_offset, regblock, size); 649 650 *pretend_size = size * UNITS_PER_WORD; 651 } 652 } 653 654 /* Abort after printing out a specific insn. */ 655 static void 656 abort_with_insn (rtx insn, const char *reason) 657 { 658 error (reason); 659 debug_rtx (insn); 660 abort (); 661 } 662 663 /* Override command line options */ 664 void 665 lm32_override_options (void) 666 { 667 /* We must have sign-extend enabled if barrel-shift isn't */ 668 if (!MASK_BARREL_SHIFT_ENABLED) 669 { 670 warning (0, "neither -mbarrel-shift-enabled nor -msign-extend-enabled specified. Assuming -msign-extend-enabled"); 671 target_flags |= MASK_SIGN_EXTEND_ENABLED; 672 } 673 } 674 675 /* Return nonzero if this function is known to have a null epilogue. 676 This allows the optimizer to omit jumps to jumps if no stack 677 was created. */ 678 int 679 lm32_can_use_return (void) 680 { 681 if (!reload_completed) 682 return 0; 683 684 if (df_regs_ever_live_p(RA_REGNUM) || crtl->profile) 685 return 0; 686 687 if (lm32_compute_frame_size (get_frame_size ()) != 0) 688 return 0; 689 690 return 1; 691 } 692 693 /* Support function to determine the return address of the function 694 'count' frames back up the stack. */ 695 rtx 696 lm32_return_addr_rtx (int count, rtx frame) 697 { 698 rtx r; 699 if (count == 0) 700 { 701 /* *mjs* This test originally used leaf_function_p (), we now use 702 the regs_ever_live test which I *think* is more accurate. */ 703 if (!df_regs_ever_live_p(RA_REGNUM)) 704 { 705 r = gen_rtx_REG (Pmode, RA_REGNUM); 706 } 707 else 708 { 709 r = gen_rtx_MEM (Pmode, 710 gen_rtx_PLUS (Pmode, frame, 711 GEN_INT(- 2 * UNITS_PER_WORD))); 712 set_mem_alias_set (r, get_frame_alias_set ()); 713 } 714 } 715 else if (flag_omit_frame_pointer) 716 r = NULL_RTX; 717 else 718 { 719 r = gen_rtx_MEM (Pmode, 720 gen_rtx_PLUS (Pmode, frame, 721 GEN_INT(- 2 * UNITS_PER_WORD))); 722 set_mem_alias_set (r, get_frame_alias_set ()); 723 } 724 return r; 725 } 726 727 /* Return true if EXP should be placed in the small data section. */ 728 729 static bool 730 lm32_in_small_data_p (const_tree exp) 731 { 732 /* We want to merge strings, so we never consider them small data. */ 733 if (TREE_CODE (exp) == STRING_CST) 734 return false; 735 736 /* Functions are never in the small data area. Duh. */ 737 if (TREE_CODE (exp) == FUNCTION_DECL) 738 return false; 739 740 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) 741 { 742 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); 743 if (strcmp (section, ".sdata") == 0 744 || strcmp (section, ".sbss") == 0) 745 return true; 746 } 747 else 748 { 749 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); 750 751 /* If this is an incomplete type with size 0, then we can't put it 752 in sdata because it might be too big when completed. */ 753 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) 754 return true; 755 } 756 757 return false; 758 } 759 760 /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 761 Assume that the areas do not overlap. */ 762 763 static void 764 lm32_block_move_inline (rtx dest, rtx src, HOST_WIDE_INT length, HOST_WIDE_INT alignment) 765 { 766 HOST_WIDE_INT offset, delta; 767 unsigned HOST_WIDE_INT bits; 768 int i; 769 enum machine_mode mode; 770 rtx *regs; 771 772 /* Work out how many bits to move at a time. */ 773 switch (alignment) 774 { 775 case 1: 776 bits = 8; 777 break; 778 case 2: 779 bits = 16; 780 break; 781 case 4: 782 bits = 32; 783 break; 784 default: 785 abort (); 786 } 787 788 mode = mode_for_size (bits, MODE_INT, 0); 789 delta = bits / BITS_PER_UNIT; 790 791 /* Allocate a buffer for the temporary registers. */ 792 regs = alloca (sizeof (rtx) * length / delta); 793 794 /* Load as many BITS-sized chunks as possible. */ 795 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 796 { 797 regs[i] = gen_reg_rtx (mode); 798 emit_move_insn (regs[i], adjust_address (src, mode, offset)); 799 } 800 801 /* Copy the chunks to the destination. */ 802 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 803 emit_move_insn (adjust_address (dest, mode, offset), regs[i]); 804 805 /* Mop up any left-over bytes. */ 806 if (offset < length) 807 { 808 src = adjust_address (src, BLKmode, offset); 809 dest = adjust_address (dest, BLKmode, offset); 810 move_by_pieces (dest, src, length - offset, 811 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); 812 } 813 } 814 815 /* Expand string/block move operations. 816 817 operands[0] is the pointer to the destination. 818 operands[1] is the pointer to the source. 819 operands[2] is the number of bytes to move. 820 operands[3] is the alignment. */ 821 822 int 823 lm32_expand_block_move (rtx *operands) 824 { 825 if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) <= 32)) 826 { 827 lm32_block_move_inline (operands[0], operands[1], INTVAL (operands[2]), INTVAL (operands[3])); 828 return 1; 829 } 830 return 0; 831 } 832 833 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol 834 isn't protected by a PIC unspec. */ 835 int 836 nonpic_symbol_mentioned_p (rtx x) 837 { 838 register const char *fmt; 839 register int i; 840 841 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF 842 || GET_CODE (x) == PC) 843 return 1; 844 845 /* We don't want to look into the possible MEM location of a 846 CONST_DOUBLE, since we're not going to use it, in general. */ 847 if (GET_CODE (x) == CONST_DOUBLE) 848 return 0; 849 850 if (GET_CODE (x) == UNSPEC) 851 return 0; 852 853 fmt = GET_RTX_FORMAT (GET_CODE (x)); 854 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 855 { 856 if (fmt[i] == 'E') 857 { 858 register int j; 859 860 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 861 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j))) 862 return 1; 863 } 864 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i))) 865 return 1; 866 } 867 868 return 0; 869 } -
gcc/config/lm32/lm32.h
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.h gcc-4.4.6/gcc/config/lm32/lm32.h
old new 1 /* Definitions of target machine for GNU compiler, Lattice Mico32 architecture. 2 Contributed by Jon Beniston <jon@beniston.com> 3 4 Copyright (C) 2008 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /*-------------------------------*/ 23 /* Run-time Target Specification */ 24 /*-------------------------------*/ 25 26 /* Print subsidiary information on the compiler version in use. */ 27 #ifndef TARGET_VERSION 28 #define TARGET_VERSION fprintf (stderr, " (LatticeMico32)") 29 #endif 30 31 /* Target CPU builtins. */ 32 #define TARGET_CPU_CPP_BUILTINS() \ 33 do \ 34 { \ 35 builtin_define ("__lm32__"); \ 36 builtin_define_std ("lm32"); \ 37 builtin_assert ("cpu=lm32"); \ 38 builtin_assert ("machine=lm32"); \ 39 } \ 40 while (0) 41 42 #define CPP_SPEC "\ 43 %{mmultiply-enabled:-D__multiply_enabled__} \ 44 %{mdivide-enabled:-D__divide_enabled__} \ 45 %{mbarrel-shift-enabled:-D__barrel_shift_enabled__} \ 46 %{msign-extend-enabled:-D__sign_extend_enabled__} \ 47 %{muser-enabled:-D__user_enabled__} \ 48 " 49 50 #undef ASM_SPEC 51 #define ASM_SPEC "\ 52 %{mmultiply-enabled} \ 53 %{mdivide-enabled} \ 54 %{mbarrel-shift-enabled} \ 55 %{msign-extend-enabled} \ 56 %{muser-extend-enabled} \ 57 %{v} \ 58 " 59 60 /* Let link script define all link options. 61 Default to using simulator link script. */ 62 63 #undef STARTFILE_SPEC 64 #define STARTFILE_SPEC "" 65 #undef ENDFILE_SPEC 66 #define ENDFILE_SPEC "" 67 #undef LIB_SPEC 68 #define LIB_SPEC "%{!T*:-T sim.ld}" 69 70 #define OVERRIDE_OPTIONS lm32_override_options() 71 72 extern int target_flags; 73 74 /* Add -G xx support. */ 75 76 #undef SWITCH_TAKES_ARG 77 #define SWITCH_TAKES_ARG(CHAR) \ 78 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 79 80 #undef CC1_SPEC 81 #define CC1_SPEC "%{G*}" 82 83 extern struct rtx_def *lm32_compare_op0; 84 extern struct rtx_def *lm32_compare_op1; 85 86 /*---------------------------------*/ 87 /* Target machine storage layout. */ 88 /*---------------------------------*/ 89 90 #define BITS_BIG_ENDIAN 0 91 #define BYTES_BIG_ENDIAN 1 92 #define WORDS_BIG_ENDIAN 1 93 #define LIBGCC2_WORDS_BIG_ENDIAN 1 94 95 #define BITS_PER_UNIT 8 96 #define BITS_PER_WORD 32 97 #define UNITS_PER_WORD 4 98 99 #define POINTER_SIZE 32 100 101 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 102 do { \ 103 if (GET_MODE_CLASS (MODE) == MODE_INT \ 104 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 105 (MODE) = word_mode; \ 106 } while (0) 107 108 #define PARM_BOUNDARY 32 109 110 #define STACK_BOUNDARY 32 111 112 #define BIGGEST_ALIGNMENT 64 113 114 #define FUNCTION_BOUNDARY 32 115 116 #define EMPTY_FIELD_BOUNDARY 32 117 118 #define STRICT_ALIGNMENT 1 119 120 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 121 122 /* Make strings word-aligned so strcpy from constants will be faster. */ 123 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 124 (TREE_CODE (EXP) == STRING_CST \ 125 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 126 127 /* Make arrays and structures word-aligned to allow faster copying etc. */ 128 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 129 ((((ALIGN) < BITS_PER_WORD) \ 130 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 131 || TREE_CODE (TYPE) == UNION_TYPE \ 132 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 133 134 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 135 character arrays to be word-aligned so that `strcpy' calls that copy 136 constants to character arrays can be done inline, and 'strcmp' can be 137 optimised to use word loads. */ 138 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 139 DATA_ALIGNMENT (TYPE, ALIGN) 140 141 /*----------------------------------------*/ 142 /* Layout of source language data types. */ 143 /*----------------------------------------*/ 144 145 #define INT_TYPE_SIZE 32 146 #define SHORT_TYPE_SIZE 16 147 #define LONG_TYPE_SIZE 32 148 #define LONG_LONG_TYPE_SIZE 64 149 150 #define FLOAT_TYPE_SIZE 32 151 #define DOUBLE_TYPE_SIZE 64 152 #define LONG_DOUBLE_TYPE_SIZE 64 153 154 #define DEFAULT_SIGNED_CHAR 0 155 156 #define SIZE_TYPE "unsigned int" 157 158 #define PTRDIFF_TYPE "int" 159 160 /*---------------------------*/ 161 /* Standard register usage. */ 162 /*---------------------------*/ 163 164 #define FIRST_PSEUDO_REGISTER 32 165 166 #define RV_REGNUM 1 167 #define GP_REGNUM 26 168 #define FP_REGNUM 27 169 #define SP_REGNUM 28 170 #define RA_REGNUM 29 171 172 #define G_REG_P(X) ((X)<32) 173 #define PSEUDO_REG_P(X) ((X)>=FIRST_PSEUDO_REGISTER) 174 175 #define FIXED_REGISTERS \ 176 { 1, 0, 0, 0, 0, 0, 0, 0, \ 177 0, 0, 0, 0, 0, 0, 0, 0, \ 178 0, 0, 0, 0, 0, 0, 0, 0, \ 179 0, 0, 1, 0, 1, 0, 1, 1} 180 181 #define CALL_USED_REGISTERS \ 182 { 1, 1, 1, 1, 1, 1, 1, 1, \ 183 1, 1, 1, 0, 0, 0, 0, 0, \ 184 0, 0, 0, 0, 0, 0, 0, 0, \ 185 0, 0, 1, 0, 1, 0, 1, 1} 186 187 #define HARD_REGNO_NREGS(REGNO, MODE) \ 188 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 189 190 #define HARD_REGNO_MODE_OK(REGNO, MODE) G_REG_P(REGNO) 191 192 #define MODES_TIEABLE_P(MODE1, MODE2) \ 193 ( GET_MODE_CLASS (MODE1) == MODE_INT \ 194 && GET_MODE_CLASS (MODE2) == MODE_INT \ 195 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 196 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 197 198 #define AVOID_CCMODE_COPIES 199 200 /*----------------------------------*/ 201 /* Register classes and constants. */ 202 /*----------------------------------*/ 203 204 enum reg_class { 205 NO_REGS, 206 GENERAL_REGS, 207 ALL_REGS, 208 LIM_REG_CLASSES 209 }; 210 211 #define N_REG_CLASSES (int) LIM_REG_CLASSES 212 213 #define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" } 214 215 #define REG_CLASS_CONTENTS \ 216 { {0x00000000}, \ 217 {0xffffffff}, \ 218 {0xffffffff} \ 219 } 220 221 #define REGNO_REG_CLASS(REGNO) \ 222 (G_REG_P(REGNO) ? GENERAL_REGS : NO_REGS) 223 224 #define CLASS_MAX_NREGS(CLASS, MODE) \ 225 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 226 227 #define INDEX_REG_CLASS NO_REGS 228 229 #define BASE_REG_CLASS GENERAL_REGS 230 231 #define REG_CLASS_FROM_LETTER(C) NO_REGS 232 233 #ifdef REG_OK_STRICT 234 #define REGNO_OK_FOR_BASE_P(REGNO) \ 235 (G_REG_P (REGNO) || G_REG_P (reg_renumber[REGNO])) 236 #else 237 #define REGNO_OK_FOR_BASE_P(REGNO) \ 238 (G_REG_P (REGNO) || PSEUDO_REG_P (REGNO)) 239 #endif 240 241 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 242 243 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) 244 245 /* The letters I, J, K, L, M, N, O, P in a register constraint string 246 can be used to stand for particular ranges of immediate operands. 247 This macro defines what the ranges are. 248 C is the letter, and VALUE is a constant value. 249 Return 1 if VALUE is in the range specified by C. 250 251 Lattice usage: 252 253 J - 0 254 K - 16-bit signed 255 L - 16-bit unsigned 256 M - 32-bit signed 257 */ 258 #define MEDIUM_INT(X) ((((HOST_WIDE_INT)(X)) >= -32768) && (((HOST_WIDE_INT)(X)) < 32768)) 259 #define MEDIUM_UINT(X) (((unsigned HOST_WIDE_INT)(X)) < 65536) 260 #define LARGE_INT(X) \ 261 ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ 262 && (X) <= (unsigned HOST_WIDE_INT) 0xffffffff) 263 264 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 265 ( (C) == 'J' ? (VALUE) == 0 \ 266 : (C) == 'K' ? MEDIUM_INT (VALUE) \ 267 : (C) == 'L' ? MEDIUM_UINT (VALUE) \ 268 : (C) == 'M' ? LARGE_INT (VALUE) \ 269 : 0 \ 270 ) 271 272 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 273 274 /*----------------------------------------*/ 275 /* Stack Layout and Calling Conventions. */ 276 /*----------------------------------------*/ 277 278 #define STACK_GROWS_DOWNWARD 1 279 280 #define FRAME_GROWS_DOWNWARD 1 281 282 #define STACK_POINTER_OFFSET (UNITS_PER_WORD) 283 284 #define STARTING_FRAME_OFFSET (UNITS_PER_WORD) 285 286 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) 287 288 #define STACK_POINTER_REGNUM SP_REGNUM 289 290 #define FRAME_POINTER_REGNUM FP_REGNUM 291 292 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 293 294 #define FRAME_POINTER_REQUIRED (cfun->calls_alloca) 295 296 #define RETURN_ADDR_RTX(count, frame) \ 297 lm32_return_addr_rtx (count, frame) 298 299 /* FIXME! */ 300 #define STATIC_CHAIN_REGNUM 3 301 302 #define ELIMINABLE_REGS \ 303 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 304 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 305 } 306 307 #define CAN_ELIMINATE(FROM, TO) \ 308 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) 309 310 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 311 (OFFSET) = lm32_compute_initial_elimination_offset (FROM, TO) 312 313 /*-----------------------------*/ 314 /* Function argument passing. */ 315 /*-----------------------------*/ 316 317 #define ACCUMULATE_OUTGOING_ARGS 1 318 319 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 320 321 /*--------------------------------*/ 322 /* Passing Arguments in Registers */ 323 /*--------------------------------*/ 324 325 /* The first argument register */ 326 #define LM32_FIRST_ARG_REG 1 327 328 /* The number of (integer) argument register available. */ 329 #define LM32_NUM_ARG_REGS 8 330 331 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 332 lm32_function_arg ((CUM), (MODE), (TYPE), (NAMED)) 333 334 #define CUMULATIVE_ARGS int 335 336 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ 337 (CUM) = 0 338 339 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 340 (CUM) += LM32_NUM_REGS2 (MODE, TYPE) 341 342 #define FUNCTION_ARG_REGNO_P(r) (((r) >= 1) && ((r) <= LM32_NUM_ARG_REGS)) 343 344 /*--------------------*/ 345 /* Function results. */ 346 /*--------------------*/ 347 348 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 349 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ 350 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ 351 ? word_mode \ 352 : TYPE_MODE (VALTYPE), \ 353 RV_REGNUM) 354 355 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RV_REGNUM) 356 357 #define FUNCTION_VALUE_REGNO_P(N) ((N) == RV_REGNUM) 358 359 #define RETURN_IN_MEMORY(TYPE) lm32_return_in_memory (TYPE) 360 361 #define DEFAULT_PCC_STRUCT_RETURN 0 362 363 /* Convert from bytes to ints. */ 364 #define LM32_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 365 366 /* The number of (integer) registers required to hold a quantity of 367 type MODE. */ 368 #define LM32_NUM_REGS(MODE) LM32_NUM_INTS (GET_MODE_SIZE (MODE)) 369 370 /* The number of (integer) registers required to hold a quantity of 371 TYPE MODE. */ 372 #define LM32_NUM_REGS2(MODE, TYPE) \ 373 LM32_NUM_INTS ((MODE) == BLKmode ? \ 374 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 375 376 #define STRUCT_VALUE 0 377 378 /*---------------------------*/ 379 /* Function entry and exit. */ 380 /*---------------------------*/ 381 382 /*-------------*/ 383 /* Profiling. */ 384 /*-------------*/ 385 386 #define FUNCTION_PROFILER(FILE, LABELNO) 387 388 /*---------------*/ 389 /* Trampolines. */ 390 /*---------------*/ 391 392 #define INITIALIZE_TRAMPOLINE 393 #define TRAMPOLINE_SIZE 0 394 395 /*---------------------*/ 396 /* Addressing Modes. */ 397 /*---------------------*/ 398 399 #define CONSTANT_ADDRESS_P(X) \ 400 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 401 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 402 || (GET_CODE (X) == CONST))) 403 404 #define MAX_REGS_PER_ADDRESS 1 405 406 #ifdef REG_OK_STRICT 407 #define REG_OK_FOR_FRAME_PTR_P(X) (REGNO (X) == FRAME_POINTER_REGNUM) 408 #else 409 #define REG_OK_FOR_FRAME_PTR_P(X) (REGNO (X) == FRAME_POINTER_REGNUM) 410 #endif 411 412 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X)) 413 #define RTX_OK_FOR_STACK_P(X) (REG_P (X) && (REGNO (X) == STACK_POINTER_REGNUM)) 414 #define CONST_OK_FOR_BASE_OFFSET(X, MODE) const_ok_for_base_offset ((X), (MODE)) 415 416 #define LEGITIMATE_BASE_INDEX_P(ADDR, MODE) \ 417 ( GET_CODE (ADDR)==PLUS \ 418 && RTX_OK_FOR_BASE_P (XEXP (ADDR, 0)) \ 419 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT \ 420 && CONST_OK_FOR_BASE_OFFSET (XEXP ((ADDR), 1), (MODE))) 421 422 #define LEGITIMATE_GPREL_P(ADDR) \ 423 ( GET_CODE (ADDR) == SYMBOL_REF \ 424 && SYMBOL_REF_SMALL_P (ADDR)) 425 426 #ifdef REG_OK_STRICT 427 #define REG_OK_FOR_BASE_P(X) (G_REG_P (REGNO (X))) 428 #else 429 #define REG_OK_FOR_BASE_P(X) (G_REG_P (REGNO (X)) || PSEUDO_REG_P (REGNO (X))) 430 #endif 431 432 #ifdef REG_OK_STRICT 433 #define REG_OK_FOR_INDEX_P(X) (G_REG_P (REGNO (X))) 434 #else 435 #define REG_OK_FOR_INDEX_P(X) (G_REG_P (REGNO (X)) || PSEUDO_REG_P (REGNO (X))) 436 #endif 437 438 #define GO_IF_LEGITIMATE_ADDRESS(m,x,l) \ 439 { \ 440 if (RTX_OK_FOR_BASE_P (x)) goto l; /* (rM) */ \ 441 else if (LEGITIMATE_BASE_INDEX_P (x, m)) goto l; /* (rM)+literal) */ \ 442 else if (LEGITIMATE_GPREL_P (x)) goto l; \ 443 } 444 445 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 446 do { \ 447 if (flag_pic) \ 448 X = lm32_legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 449 } while (0) 450 451 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 452 if (GET_CODE (ADDR) == PLUS) goto LABEL; \ 453 454 #define LEGITIMATE_CONSTANT_P(X) 1 455 456 /*-------------------------*/ 457 /* Condition Code Status. */ 458 /*-------------------------*/ 459 460 #define REVERSIBLE_CC_MODE(MODE) 1 461 462 /*---------*/ 463 /* Costs. */ 464 /*---------*/ 465 466 #define SLOW_BYTE_ACCESS 1 467 468 #define NO_FUNCTION_CSE 469 470 #define BRANCH_COST(speed_p, predictable_p) 4 471 472 #define MOVE_RATIO(speed) (speed ? 24 : 3) 473 474 /*------------*/ 475 /* Sections. */ 476 /*------------*/ 477 478 #define TEXT_SECTION_ASM_OP "\t.section\t.text" 479 #define DATA_SECTION_ASM_OP "\t.section\t.data" 480 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\"" 481 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 482 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\"" 483 484 /*-------*/ 485 /* PIC. */ 486 /*-------*/ 487 488 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? GP_REGNUM : INVALID_REGNUM) 489 490 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 491 492 #define LEGITIMATE_PIC_OPERAND_P(X) \ 493 (!(nonpic_symbol_mentioned_p (X))) 494 495 /*-------------*/ 496 /* Assembler. */ 497 /*-------------*/ 498 499 #define ASM_COMMENT_START "#" 500 501 #define ASM_APP_ON "#APP\n" 502 503 #define ASM_APP_OFF "#NO_APP\n" 504 505 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ 506 do { \ 507 fputc ( '\t', FILE); \ 508 assemble_name (FILE, LABEL1); \ 509 fputs ( " = ", FILE); \ 510 assemble_name (FILE, LABEL2); \ 511 fputc ( '\n', FILE); \ 512 } while (0) 513 514 /* Override default implementation in elfos.h to support -G. */ 515 #undef ASM_OUTPUT_ALIGNED_LOCAL 516 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 517 do { \ 518 if ((SIZE) <= g_switch_value) \ 519 switch_to_section (sbss_section); \ 520 else \ 521 switch_to_section (bss_section); \ 522 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ 523 if (!flag_inhibit_size_directive) \ 524 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 525 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \ 526 ASM_OUTPUT_LABEL(FILE, NAME); \ 527 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \ 528 } while (0) 529 530 /* Override default implementation in elfos.h to support -G. */ 531 #undef ASM_OUTPUT_ALIGNED_COMMON 532 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 533 do \ 534 { \ 535 if ((SIZE) <= g_switch_value) \ 536 { \ 537 switch_to_section (sbss_section); \ 538 (*targetm.asm_out.globalize_label) (FILE, NAME); \ 539 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ 540 if (!flag_inhibit_size_directive) \ 541 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 542 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \ 543 ASM_OUTPUT_LABEL(FILE, NAME); \ 544 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \ 545 } \ 546 else \ 547 { \ 548 switch_to_section (bss_section); \ 549 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 550 assemble_name ((FILE), (NAME)); \ 551 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \ 552 } \ 553 } \ 554 while (0) 555 556 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 557 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 558 559 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 560 do { \ 561 const char *xname = (NAME); \ 562 if (xname[0] == '@') \ 563 xname += 1; \ 564 if (xname[0] == '*') \ 565 xname += 1; \ 566 fputs (xname, FILE); \ 567 } while (0) 568 569 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ 570 do { \ 571 assemble_name (STREAM, XSTR (SYMBOL, 0)); \ 572 } while (0) 573 574 #define GLOBAL_ASM_OP "\t.global\t" 575 576 #define REGISTER_NAMES \ 577 { \ 578 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 579 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 580 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 581 "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba"} 582 583 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 584 (((CHAR) == '&') || ((CHAR) == '@') || ((CHAR) == '*')) 585 586 #define PRINT_OPERAND(FILE, X, CODE) \ 587 lm32_print_operand (FILE, X, CODE) 588 589 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 590 lm32_print_operand_address (FILE, ADDR) 591 592 #ifndef LOCAL_LABEL_PREFIX 593 #define LOCAL_LABEL_PREFIX "." 594 #endif 595 596 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 597 do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", (1 << (LOG))); } while (0) 598 599 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 600 do { \ 601 char label[64]; \ 602 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 603 fprintf (FILE, "\n\t.word\t"); \ 604 assemble_name (FILE, label); \ 605 fprintf (FILE, "\n"); \ 606 } while (0) 607 608 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 609 do { \ 610 char label[64]; \ 611 fprintf (FILE, "\t.word\t("); \ 612 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 613 assemble_name (FILE, label); \ 614 fprintf (FILE, "-"); \ 615 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 616 assemble_name (FILE, label); \ 617 fprintf (FILE, ")\n"); \ 618 } while (0) 619 620 /*-------------*/ 621 /* Debugging. */ 622 /*-------------*/ 623 624 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 625 626 #define CAN_DEBUG_WITHOUT_FP 627 628 #define DEFAULT_GDB_EXTENSIONS 1 629 630 /*--------*/ 631 /* Misc. */ 632 /*--------*/ 633 634 #define CASE_VECTOR_MODE Pmode 635 636 #define WORD_REGISTER_OPERATIONS 637 638 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 639 640 #define SHORT_IMMEDIATES_SIGN_EXTEND 641 642 #define MOVE_MAX UNITS_PER_WORD 643 #define MAX_MOVE_MAX 4 644 645 #define SHIFT_COUNT_TRUNCATED 1 646 647 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 648 649 #define Pmode SImode 650 651 #define FUNCTION_MODE SImode 652 653 #ifndef NO_IMPLICIT_EXTERN_C 654 #define NO_IMPLICIT_EXTERN_C 655 #endif 656 657 #define STORE_FLAG_VALUE 1 -
gcc/config/lm32/lm32.md
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.md gcc-4.4.6/gcc/config/lm32/lm32.md
old new 1 ;; Machine description of the Lattice Mico32 architecture for GNU C compiler. 2 ;; Contributed by Jon Beniston <jon@beniston.com> 3 4 ;; This file is part of GCC. 5 6 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; under the terms of the GNU General Public License as published 8 ;; by the Free Software Foundation; either version 3, or (at your 9 ;; option) any later version. 10 11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT 12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 ;; License for more details. 15 16 ;; You should have received a copy of the GNU General Public License 17 ;; along with GCC; see the file COPYING3. If not see 18 ;; <http://www.gnu.org/licenses/>. 19 20 ;; Include predicate definitions 21 (include "predicates.md") 22 23 ;; Register numbers 24 (define_constants 25 [(RA_REGNUM 29) ; return address register. 26 ] 27 ) 28 29 ;; LM32 specific volatile operations 30 (define_constants 31 [(UNSPECV_BLOCKAGE 1)] ; use to prevent scheduler from optimising accross bounaries 32 ) 33 34 ;; LM32 specific operations 35 (define_constants 36 [(UNSPEC_GOT 2) 37 (UNSPEC_GOTOFF_HI16 3) 38 (UNSPEC_GOTOFF_LO16 4)] 39 ) 40 41 ;; --------------------------------- 42 ;; instruction types 43 ;; --------------------------------- 44 45 (define_attr "type" 46 "unknown,load,store,arith,compare,shift,multiply,divide,call,icall,ubranch,uibranch,cbranch" 47 (const_string "unknown")) 48 49 ;; --------------------------------- 50 ;; instruction lengths 51 ;; --------------------------------- 52 53 ; All instructions are 4 bytes 54 ; Except for branches that are out of range, and have to be implemented 55 ; as two instructions 56 (define_attr "length" "" 57 (cond [ 58 (eq_attr "type" "cbranch") 59 (if_then_else 60 (lt (abs (minus (match_dup 2) (pc))) 61 (const_int 32768) 62 ) 63 (const_int 4) 64 (const_int 8) 65 ) 66 ] 67 (const_int 4)) 68 ) 69 70 ;; --------------------------------- 71 ;; scheduling 72 ;; --------------------------------- 73 74 (define_automaton "lm32") 75 76 (define_cpu_unit "x" "lm32") 77 (define_cpu_unit "m" "lm32") 78 (define_cpu_unit "w" "lm32") 79 80 (define_insn_reservation "singlecycle" 1 81 (eq_attr "type" "store,arith,call,icall,ubranch,uibranch,cbranch") 82 "x") 83 84 (define_insn_reservation "twocycle" 2 85 (eq_attr "type" "compare,shift,divide") 86 "x,m") 87 88 (define_insn_reservation "threecycle" 3 89 (eq_attr "type" "load,multiply") 90 "x,m,w") 91 92 ;; --------------------------------- 93 ;; mov 94 ;; --------------------------------- 95 96 (define_expand "movqi" 97 [(set (match_operand:QI 0 "general_operand" "") 98 (match_operand:QI 1 "general_operand" ""))] 99 "" 100 " 101 { 102 if (can_create_pseudo_p ()) 103 { 104 if (GET_CODE (operand0) == MEM) 105 { 106 /* Source operand for store must be in a register */ 107 operands[1] = force_reg (QImode, operands[1]); 108 } 109 } 110 if ( GET_CODE (operands[1]) == CONST_INT 111 && GET_CODE (operands[0]) == REG) 112 { 113 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); 114 emit_insn (gen_movsi (operands[0], operands[1])); 115 DONE; 116 } 117 }") 118 119 (define_expand "movhi" 120 [(set (match_operand:HI 0 "general_operand" "") 121 (match_operand:HI 1 "general_operand" ""))] 122 "" 123 " 124 { 125 if (can_create_pseudo_p ()) 126 { 127 if (GET_CODE (operands[0]) == MEM) 128 { 129 /* Source operand for store must be in a register */ 130 operands[1] = force_reg (HImode, operands[1]); 131 } 132 } 133 if (GET_CODE (operands[1]) == CONST_INT) 134 { 135 operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); 136 if (MEDIUM_INT (INTVAL (operands[1]))) 137 emit_insn (gen_movsi_kimm (operands[0], operands[1])); 138 else if (MEDIUM_UINT (INTVAL (operands[1]))) 139 emit_insn (gen_movsi_limm (operands[0], operands[1])); 140 else 141 { 142 emit_insn (gen_movsi_imm_hi (operands[0], GEN_INT (INTVAL (operands[1])))); 143 emit_insn (gen_movsi_imm_lo (operands[0], operands[0], GEN_INT (INTVAL (operands[1])))); 144 } 145 DONE; 146 } 147 }") 148 149 (define_expand "movsi" 150 [(set (match_operand:SI 0 "general_operand" "") 151 (match_operand:SI 1 "general_operand" ""))] 152 "" 153 " 154 { 155 if (can_create_pseudo_p ()) 156 { 157 if (GET_CODE (operands[0]) == MEM 158 || (GET_CODE (operands[0]) == SUBREG 159 && GET_CODE (SUBREG_REG (operands[0])) == MEM)) 160 { 161 /* Source operand for store must be in a register */ 162 operands[1] = force_reg (SImode, operands[1]); 163 } 164 } 165 166 if (flag_pic && symbolic_operand (operands[1], SImode)) 167 { 168 if (GET_CODE (operands[1]) == LABEL_REF 169 || (GET_CODE (operands[1]) == SYMBOL_REF 170 && SYMBOL_REF_LOCAL_P (operands[1]) 171 && !SYMBOL_REF_WEAK (operands[1]))) 172 { 173 emit_insn (gen_movsi_gotoff_hi16 (operands[0], operands[1])); 174 emit_insn (gen_addsi3 (operands[0], operands[0], pic_offset_table_rtx)); 175 emit_insn (gen_movsi_gotoff_lo16 (operands[0], operands[0], operands[1])); 176 } 177 else 178 { 179 emit_insn (gen_movsi_got (operands[0], operands[1])); 180 } 181 crtl->uses_pic_offset_table = 1; 182 DONE; 183 } 184 else if (flag_pic && GET_CODE (operands[1]) == CONST) 185 { 186 rtx op = XEXP (operands[1], 0); 187 if (GET_CODE (op) == PLUS) 188 { 189 rtx arg0 = XEXP (op, 0); 190 rtx arg1 = XEXP (op, 1); 191 if (GET_CODE (arg0) == LABEL_REF 192 || (GET_CODE (arg0) == SYMBOL_REF 193 && SYMBOL_REF_LOCAL_P (arg0) 194 && !SYMBOL_REF_WEAK (arg0))) 195 { 196 emit_insn (gen_movsi_gotoff_hi16 (operands[0], arg0)); 197 emit_insn (gen_addsi3 (operands[0], operands[0], pic_offset_table_rtx)); 198 emit_insn (gen_movsi_gotoff_lo16 (operands[0], operands[0], arg0)); 199 } 200 else 201 { 202 emit_insn (gen_movsi_got (operands[0], arg0)); 203 } 204 emit_insn (gen_addsi3 (operands[0], operands[0], arg1)); 205 crtl->uses_pic_offset_table = 1; 206 DONE; 207 } 208 } 209 else if (!flag_pic && ( GET_CODE (operands[1]) == SYMBOL_REF 210 && SYMBOL_REF_SMALL_P (operands[1]) 211 ) 212 ) 213 { 214 emit_insn (gen_movsi_reloc_gprel (operands[0], operands[1])); 215 DONE; 216 } 217 else if (!flag_pic && ( GET_CODE (operands[1]) == LABEL_REF 218 || GET_CODE (operands[1]) == SYMBOL_REF 219 || GET_CODE (operands[1]) == CONST 220 ) 221 ) 222 { 223 emit_insn (gen_movsi_reloc_hi (operands[0], operands[1])); 224 emit_insn (gen_movsi_reloc_lo (operands[0], operands[0], operands[1])); 225 DONE; 226 } 227 else if (GET_CODE (operands[1]) == CONST_INT) 228 { 229 if (MEDIUM_INT (INTVAL (operands[1]))) 230 emit_insn (gen_movsi_kimm (operands[0], operands[1])); 231 else if (MEDIUM_UINT (INTVAL (operands[1]))) 232 emit_insn (gen_movsi_limm (operands[0], operands[1])); 233 else 234 { 235 emit_insn (gen_movsi_imm_hi (operands[0], GEN_INT (INTVAL (operands[1])))); 236 emit_insn (gen_movsi_imm_lo (operands[0], operands[0], GEN_INT (INTVAL (operands[1])))); 237 } 238 DONE; 239 } 240 }") 241 242 ;;(define_expand "movmemsi" 243 ;; [(parallel [(set (match_operand:BLK 0 "general_operand" "") 244 ;; (match_operand:BLK 1 "general_operand" "")) 245 ;; (use (match_operand:SI 2 "" "")) 246 ;; (use (match_operand:SI 3 "const_int_operand" ""))])] 247 ;; "" 248 ;;{ 249 ;; if (!lm32_expand_block_move (operands)) 250 ;; FAIL; 251 ;; DONE; 252 ;;}) 253 254 ;; --------------------------------- 255 ;; load/stores/moves 256 ;; --------------------------------- 257 258 (define_insn "movsi_kimm" 259 [(set (match_operand:SI 0 "register_operand" "=r") 260 (match_operand:SI 1 "constant_K_operand" "K"))] 261 "" 262 "addi %0, r0, %1" 263 [(set_attr "type" "arith")] 264 ) 265 266 (define_insn "movsi_limm" 267 [(set (match_operand:SI 0 "register_operand" "=r") 268 (match_operand:SI 1 "constant_L_operand" "L"))] 269 "" 270 "ori %0, r0, %1" 271 [(set_attr "type" "arith")] 272 ) 273 274 (define_insn "movsi_imm_hi" 275 [(set (match_operand:SI 0 "register_operand" "=r") 276 (high:SI (match_operand:SI 1 "immediate_operand" "i")))] 277 "" 278 "orhi %0, r0, hi(%1)" 279 [(set_attr "type" "arith")] 280 ) 281 282 (define_insn "movsi_imm_lo" 283 [(set (match_operand:SI 0 "register_operand" "=r") 284 (lo_sum:SI (match_operand:SI 1 "register_operand" "0") 285 (match_operand:SI 2 "immediate_operand" "i")))] 286 "" 287 "ori %0, %0, lo(%2)" 288 [(set_attr "type" "arith")] 289 ) 290 291 (define_insn "movsi_reloc_gprel" 292 [(set (match_operand:SI 0 "register_operand" "=r") 293 (match_operand:SI 1 "reloc_operand" "i"))] 294 "GET_CODE (operands[1]) == SYMBOL_REF && SYMBOL_REF_SMALL_P (operands[1])" 295 "mva %0, gp(%1)" 296 [(set_attr "type" "arith")] 297 ) 298 299 (define_insn "movsi_got" 300 [(set (match_operand:SI 0 "register_operand" "=r") 301 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOT))] 302 "flag_pic" 303 "lw %0, (gp+got(%1))" 304 [(set_attr "type" "load")] 305 ) 306 307 (define_insn "movsi_gotoff_hi16" 308 [(set (match_operand:SI 0 "register_operand" "=r") 309 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF_HI16))] 310 "flag_pic" 311 "orhi %0, r0, gotoffhi16(%1)" 312 [(set_attr "type" "load")] 313 ) 314 315 (define_insn "movsi_gotoff_lo16" 316 [(set (match_operand:SI 0 "register_operand" "=r") 317 (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "0") 318 (match_operand 2 "" ""))] UNSPEC_GOTOFF_LO16))] 319 "flag_pic" 320 "addi %0, %1, gotofflo16(%2)" 321 [(set_attr "type" "arith")] 322 ) 323 324 (define_insn "movsi_reloc_hi" 325 [(set (match_operand:SI 0 "register_operand" "=r") 326 (high:SI (match_operand:SI 1 "reloc_operand" "i")))] 327 "!flag_pic" 328 "orhi %0, r0, hi(%1)" 329 [(set_attr "type" "arith")] 330 ) 331 332 (define_insn "movsi_reloc_lo" 333 [(set (match_operand:SI 0 "register_operand" "=r") 334 (lo_sum:SI (match_operand:SI 1 "register_operand" "0") 335 (match_operand:SI 2 "reloc_operand" "i")))] 336 "!flag_pic" 337 "ori %0, %0, lo(%2)" 338 [(set_attr "type" "arith")] 339 ) 340 341 (define_insn "*movqi_insn" 342 [(set (match_operand:QI 0 "register_or_memory_operand" "=r,r,m") 343 (match_operand:QI 1 "register_or_memory_operand" "m,r,r"))] 344 "" 345 "@ 346 lbu %0, %1 347 or %0, %1, r0 348 sb %0, %1" 349 [(set_attr "type" "load,arith,store")] 350 ) 351 352 (define_insn "*movhi_insn" 353 [(set (match_operand:HI 0 "register_or_memory_operand" "=r,r,m") 354 (match_operand:HI 1 "register_or_memory_operand" "m,r,r"))] 355 "" 356 "@ 357 lhu %0, %1 358 or %0, %1, r0 359 sh %0, %1" 360 [(set_attr "type" "load,arith,store")] 361 ) 362 363 (define_insn "*movsi_insn" 364 [(set (match_operand:SI 0 "register_or_memory_operand" "=r,r,m") 365 (match_operand:SI 1 "register_or_memory_operand" "m,r,r"))] 366 "" 367 "@ 368 lw %0, %1 369 or %0, %1, r0 370 sw %0, %1" 371 [(set_attr "type" "load,arith,store")] 372 ) 373 374 ;; --------------------------------- 375 ;; sign and zero extension 376 ;; --------------------------------- 377 378 (define_insn "*extendqihi2" 379 [(set (match_operand:HI 0 "register_operand" "=r,r") 380 (sign_extend:HI (match_operand:QI 1 "register_or_memory_operand" "m,r")))] 381 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)" 382 "@ 383 lb %0, %1 384 sextb %0, %1" 385 [(set_attr "type" "load,arith")] 386 ) 387 388 (define_insn "zero_extendqihi2" 389 [(set (match_operand:HI 0 "register_operand" "=r,r") 390 (zero_extend:HI (match_operand:QI 1 "register_or_memory_operand" "m,r")))] 391 "" 392 "@ 393 lbu %0, %1 394 andi %0, %1, 0xff" 395 [(set_attr "type" "load,arith")] 396 ) 397 398 (define_insn "*extendqisi2" 399 [(set (match_operand:SI 0 "register_operand" "=r,r") 400 (sign_extend:SI (match_operand:QI 1 "register_or_memory_operand" "m,r")))] 401 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)" 402 "@ 403 lb %0, %1 404 sextb %0, %1" 405 [(set_attr "type" "load,arith")] 406 ) 407 408 (define_insn "zero_extendqisi2" 409 [(set (match_operand:SI 0 "register_operand" "=r,r") 410 (zero_extend:SI (match_operand:QI 1 "register_or_memory_operand" "m,r")))] 411 "" 412 "@ 413 lbu %0, %1 414 andi %0, %1, 0xff" 415 [(set_attr "type" "load,arith")] 416 ) 417 418 (define_insn "*extendhisi2" 419 [(set (match_operand:SI 0 "register_operand" "=r,r") 420 (sign_extend:SI (match_operand:HI 1 "register_or_memory_operand" "m,r")))] 421 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)" 422 "@ 423 lh %0, %1 424 sexth %0, %1" 425 [(set_attr "type" "load,arith")] 426 ) 427 428 (define_insn "zero_extendhisi2" 429 [(set (match_operand:SI 0 "register_operand" "=r,r") 430 (zero_extend:SI (match_operand:HI 1 "register_or_memory_operand" "m,r")))] 431 "" 432 "@ 433 lhu %0, %1 434 andi %0, %1, 0xffff" 435 [(set_attr "type" "load,arith")] 436 ) 437 438 ;; --------------------------------- 439 ;; compare 440 ;; --------------------------------- 441 442 (define_expand "cmpsi" 443 [(set (cc0) 444 (compare:CC (match_operand:SI 0 "register_operand" "") 445 (match_operand:SI 1 "register_or_K_operand" "")))] 446 "" 447 " 448 { 449 lm32_compare_op0 = operands[0]; 450 lm32_compare_op1 = operands[1]; 451 DONE; 452 }") 453 454 455 (define_expand "tstsi" 456 [(set (cc0) 457 (match_operand:SI 0 "register_operand" ""))] 458 "" 459 " 460 { 461 lm32_compare_op0 = operands[0]; 462 lm32_compare_op1 = const0_rtx; 463 DONE; 464 }") 465 466 (define_expand "seq" 467 [(set (match_operand:SI 0 "register_operand" "=r") 468 (eq:SI (match_dup 1) 469 (match_dup 2)))] 470 "" 471 { 472 operands[1] = lm32_compare_op0; 473 operands[2] = lm32_compare_op1; 474 gen_int_relational (EQ, operands[0], operands[1], operands[2], NULL_RTX); 475 DONE; 476 }) 477 478 (define_insn "*seq" 479 [(set (match_operand:SI 0 "register_operand" "=r,r") 480 (eq:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 481 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 482 "" 483 "@ 484 cmpe %0, %z1, %2 485 cmpei %0, %z1, %2" 486 [(set_attr "type" "compare")] 487 ) 488 489 (define_expand "sne" 490 [(set (match_operand:SI 0 "register_operand" "=r") 491 (ne:SI (match_dup 1) 492 (match_dup 2)))] 493 "" 494 { 495 operands[1] = lm32_compare_op0; 496 operands[2] = lm32_compare_op1; 497 gen_int_relational (NE, operands[0], operands[1], operands[2], NULL_RTX); 498 DONE; 499 }) 500 501 (define_insn "*sne" 502 [(set (match_operand:SI 0 "register_operand" "=r,r") 503 (ne:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 504 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 505 "" 506 "@ 507 cmpne %0, %z1, %2 508 cmpnei %0, %z1, %2" 509 [(set_attr "type" "compare")] 510 ) 511 512 (define_expand "sgt" 513 [(set (match_operand:SI 0 "register_operand" "=r") 514 (gt:SI (match_dup 1) 515 (match_dup 2)))] 516 "" 517 { 518 operands[1] = lm32_compare_op0; 519 operands[2] = lm32_compare_op1; 520 gen_int_relational (GT, operands[0], operands[1], operands[2], NULL_RTX); 521 DONE; 522 }) 523 524 (define_insn "*sgt" 525 [(set (match_operand:SI 0 "register_operand" "=r,r") 526 (gt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 527 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 528 "" 529 "@ 530 cmpg %0, %z1, %2 531 cmpgi %0, %z1, %2" 532 [(set_attr "type" "compare")] 533 ) 534 535 (define_expand "slt" 536 [(set (match_operand:SI 0 "register_operand" "=r") 537 (lt:SI (match_dup 1) 538 (match_dup 2)))] 539 "" 540 { 541 operands[1] = lm32_compare_op0; 542 operands[2] = lm32_compare_op1; 543 gen_int_relational (LT, operands[0], operands[1], operands[2], NULL_RTX); 544 DONE; 545 }) 546 547 (define_expand "sge" 548 [(set (match_operand:SI 0 "register_operand" "=r") 549 (ge:SI (match_dup 1) 550 (match_dup 2)))] 551 "" 552 { 553 operands[1] = lm32_compare_op0; 554 operands[2] = lm32_compare_op1; 555 gen_int_relational (GE, operands[0], operands[1], operands[2], NULL_RTX); 556 DONE; 557 }) 558 559 (define_insn "*sge" 560 [(set (match_operand:SI 0 "register_operand" "=r,r") 561 (ge:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 562 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 563 "" 564 "@ 565 cmpge %0, %z1, %2 566 cmpgei %0, %z1, %2" 567 [(set_attr "type" "compare")] 568 ) 569 570 (define_expand "sle" 571 [(set (match_operand:SI 0 "register_operand" "=r") 572 (le:SI (match_dup 1) 573 (match_dup 2)))] 574 "" 575 { 576 operands[1] = lm32_compare_op0; 577 operands[2] = lm32_compare_op1; 578 gen_int_relational (LE, operands[0], operands[1], operands[2], NULL_RTX); 579 DONE; 580 }) 581 582 (define_expand "sgtu" 583 [(set (match_operand:SI 0 "register_operand" "=r") 584 (gtu:SI (match_dup 1) 585 (match_dup 2)))] 586 "" 587 { 588 operands[1] = lm32_compare_op0; 589 operands[2] = lm32_compare_op1; 590 gen_int_relational (GTU, operands[0], operands[1], operands[2], NULL_RTX); 591 DONE; 592 }) 593 594 (define_insn "*sgtu" 595 [(set (match_operand:SI 0 "register_operand" "=r,r") 596 (gtu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 597 (match_operand:SI 2 "register_or_K_operand" "r,L")))] 598 "" 599 "@ 600 cmpgu %0, %z1, %2 601 cmpgui %0, %z1, %2" 602 [(set_attr "type" "compare")] 603 ) 604 605 (define_expand "sltu" 606 [(set (match_operand:SI 0 "register_operand" "=r") 607 (ltu:SI (match_dup 1) 608 (match_dup 2)))] 609 "" 610 { 611 operands[1] = lm32_compare_op0; 612 operands[2] = lm32_compare_op1; 613 gen_int_relational (LTU, operands[0], operands[1], operands[2], NULL_RTX); 614 DONE; 615 }) 616 617 (define_expand "sgeu" 618 [(set (match_operand:SI 0 "register_operand" "=r") 619 (geu:SI (match_dup 1) 620 (match_dup 2)))] 621 "" 622 { 623 operands[1] = lm32_compare_op0; 624 operands[2] = lm32_compare_op1; 625 gen_int_relational (GEU, operands[0], operands[1], operands[2], NULL_RTX); 626 DONE; 627 }) 628 629 (define_insn "*sgeu" 630 [(set (match_operand:SI 0 "register_operand" "=r,r") 631 (geu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 632 (match_operand:SI 2 "register_or_K_operand" "r,L")))] 633 "" 634 "@ 635 cmpgeu %0, %z1, %2 636 cmpgeui %0, %z1, %2" 637 [(set_attr "type" "compare")] 638 ) 639 640 (define_expand "sleu" 641 [(set (match_operand:SI 0 "register_operand" "=r") 642 (leu:SI (match_dup 1) 643 (match_dup 2)))] 644 "" 645 { 646 operands[1] = lm32_compare_op0; 647 operands[2] = lm32_compare_op1; 648 gen_int_relational (LEU, operands[0], operands[1], operands[2], NULL_RTX); 649 DONE; 650 }) 651 652 ;; --------------------------------- 653 ;; unconditional branch 654 ;; --------------------------------- 655 656 (define_insn "jump" 657 [(set (pc) (label_ref (match_operand 0 "" "")))] 658 "" 659 "bi %0" 660 [(set_attr "type" "ubranch")] 661 ) 662 663 (define_expand "indirect_jump" 664 [(set (pc) (match_operand 0 "register_operand" ""))] 665 "" 666 " 667 { 668 emit_jump_insn (gen_indirect_jumpsi (operands[0])); 669 DONE; 670 }") 671 672 (define_insn "indirect_jumpsi" 673 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 674 "" 675 "b %0" 676 [(set_attr "type" "uibranch")] 677 ) 678 679 ;; --------------------------------- 680 ;; conditional branch 681 ;; --------------------------------- 682 683 (define_expand "beq" 684 [(set (pc) 685 (if_then_else (eq:CC (cc0) 686 (const_int 0)) 687 (label_ref (match_operand 0 "" "")) 688 (pc)))] 689 "" 690 " 691 { 692 gen_int_relational (EQ, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 693 DONE; 694 }") 695 696 (define_expand "bne" 697 [(set (pc) 698 (if_then_else (ne:CC (cc0) 699 (const_int 0)) 700 (label_ref (match_operand 0 "" "")) 701 (pc)))] 702 "" 703 " 704 { 705 gen_int_relational (NE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 706 DONE; 707 }") 708 709 (define_expand "bgt" 710 [(set (pc) 711 (if_then_else (gt:CC (cc0) 712 (const_int 0)) 713 (label_ref (match_operand 0 "" "")) 714 (pc)))] 715 "" 716 " 717 { 718 gen_int_relational (GT, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 719 DONE; 720 }") 721 722 (define_expand "bge" 723 [(set (pc) 724 (if_then_else (ge:CC (cc0) 725 (const_int 0)) 726 (label_ref (match_operand 0 "" "")) 727 (pc)))] 728 "" 729 " 730 { 731 gen_int_relational (GE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 732 DONE; 733 }") 734 735 (define_expand "ble" 736 [(set (pc) 737 (if_then_else (le:CC (cc0) 738 (const_int 0)) 739 (label_ref (match_operand 0 "" "")) 740 (pc)))] 741 "" 742 " 743 { 744 gen_int_relational (LE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 745 DONE; 746 }") 747 748 (define_expand "blt" 749 [(set (pc) 750 (if_then_else (lt:CC (cc0) 751 (const_int 0)) 752 (label_ref (match_operand 0 "" "")) 753 (pc)))] 754 "" 755 " 756 { 757 gen_int_relational (LT, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 758 DONE; 759 }") 760 761 (define_expand "bgtu" 762 [(set (pc) 763 (if_then_else (gtu:CC (cc0) 764 (const_int 0)) 765 (label_ref (match_operand 0 "" "")) 766 (pc)))] 767 "" 768 " 769 { 770 gen_int_relational (GTU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 771 DONE; 772 }") 773 774 (define_expand "bgeu" 775 [(set (pc) 776 (if_then_else (geu:CC (cc0) 777 (const_int 0)) 778 (label_ref (match_operand 0 "" "")) 779 (pc)))] 780 "" 781 " 782 { 783 gen_int_relational (GEU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 784 DONE; 785 }") 786 787 (define_expand "bleu" 788 [(set (pc) 789 (if_then_else (leu:CC (cc0) 790 (const_int 0)) 791 (label_ref (match_operand 0 "" "")) 792 (pc)))] 793 "" 794 " 795 { 796 gen_int_relational (LEU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 797 DONE; 798 }") 799 800 (define_expand "bltu" 801 [(set (pc) 802 (if_then_else (ltu:CC (cc0) 803 (const_int 0)) 804 (label_ref (match_operand 0 "" "")) 805 (pc)))] 806 "" 807 " 808 { 809 gen_int_relational (LTU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]); 810 DONE; 811 }") 812 813 (define_insn "*beq" 814 [(set (pc) 815 (if_then_else (eq:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 816 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 817 (label_ref (match_operand 2 "" "")) 818 (pc)))] 819 "" 820 { 821 return get_attr_length (insn) == 4 822 ? "be %z0,%z1,%2" 823 : "bne %z0,%z1,8\n\tbi %2"; 824 } 825 [(set_attr "type" "cbranch")]) 826 827 (define_insn "*bne" 828 [(set (pc) 829 (if_then_else (ne:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 830 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 831 (label_ref (match_operand 2 "" "")) 832 (pc)))] 833 "" 834 { 835 return get_attr_length (insn) == 4 836 ? "bne %z0,%z1,%2" 837 : "be %z0,%z1,8\n\tbi %2"; 838 } 839 [(set_attr "type" "cbranch")]) 840 841 (define_insn "*bgt" 842 [(set (pc) 843 (if_then_else (gt:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 844 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 845 (label_ref (match_operand 2 "" "")) 846 (pc)))] 847 "" 848 { 849 return get_attr_length (insn) == 4 850 ? "bg %z0,%z1,%2" 851 : "bge %z1,%z0,8\n\tbi %2"; 852 } 853 [(set_attr "type" "cbranch")]) 854 855 (define_insn "*bge" 856 [(set (pc) 857 (if_then_else (ge:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 858 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 859 (label_ref (match_operand 2 "" "")) 860 (pc)))] 861 "" 862 { 863 return get_attr_length (insn) == 4 864 ? "bge %z0,%z1,%2" 865 : "bg %z1,%z0,8\n\tbi %2"; 866 } 867 [(set_attr "type" "cbranch")]) 868 869 (define_insn "*bgtu" 870 [(set (pc) 871 (if_then_else (gtu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 872 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 873 (label_ref (match_operand 2 "" "")) 874 (pc)))] 875 "" 876 { 877 return get_attr_length (insn) == 4 878 ? "bgu %z0,%z1,%2" 879 : "bgeu %z1,%z0,8\n\tbi %2"; 880 } 881 [(set_attr "type" "cbranch")]) 882 883 (define_insn "*bgeu" 884 [(set (pc) 885 (if_then_else (geu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") 886 (match_operand:SI 1 "register_or_zero_operand" "rJ")) 887 (label_ref (match_operand 2 "" "")) 888 (pc)))] 889 "" 890 { 891 return get_attr_length (insn) == 4 892 ? "bgeu %z0,%z1,%2" 893 : "bgu %z1,%z0,8\n\tbi %2"; 894 } 895 [(set_attr "type" "cbranch")]) 896 897 ;; --------------------------------- 898 ;; call 899 ;; --------------------------------- 900 901 (define_expand "call" 902 [(parallel [(call (match_operand 0 "memory_operand" "m") 903 (match_operand 1 "" "")) 904 (clobber (reg:SI RA_REGNUM)) 905 ])] 906 "" 907 " 908 { 909 rtx addr = XEXP (operands[0], 0); 910 if (!CONSTANT_ADDRESS_P (addr)) 911 { 912 emit_call_insn (gen_call_via_regsi (addr, operands[1])); 913 DONE; 914 } 915 }") 916 917 (define_insn "call_via_regsi" 918 [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) 919 (match_operand 1 "" "")) 920 (clobber (reg:SI RA_REGNUM))] 921 "" 922 "call %0" 923 [(set_attr "type" "icall")] 924 ) 925 926 (define_insn "*call_via_labelsi" 927 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "X")) 928 (match_operand 1 "" "")) 929 (clobber (reg:SI RA_REGNUM))] 930 "" 931 "calli %0" 932 [(set_attr "type" "call")] 933 ) 934 935 (define_expand "call_value" 936 [(parallel [(set (match_operand 0 "register_operand" "=r") 937 (call (match_operand 1 "memory_operand" "m") 938 (match_operand 2 "" ""))) 939 (clobber (reg:SI RA_REGNUM)) 940 ])] 941 "" 942 " 943 { 944 rtx addr = XEXP (operands[1], 0); 945 if (!CONSTANT_ADDRESS_P (addr)) 946 { 947 emit_call_insn (gen_call_value_via_regsi (operands[0], addr, operands[2])); 948 DONE; 949 } 950 }") 951 952 (define_insn "call_value_via_regsi" 953 [(set (match_operand 0 "register_operand" "=r") 954 (call (mem:SI (match_operand:SI 1 "register_operand" "r")) 955 (match_operand 2 "" ""))) 956 (clobber (reg:SI RA_REGNUM))] 957 "" 958 "call %1" 959 [(set_attr "type" "icall")] 960 ) 961 962 (define_insn "*call_value_via_labelsi" 963 [(set (match_operand 0 "register_operand" "=r") 964 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "X")) 965 (match_operand 2 "" ""))) 966 (clobber (reg:SI RA_REGNUM))] 967 "" 968 "calli %1" 969 [(set_attr "type" "call")] 970 ) 971 972 (define_insn "return_internalsi" 973 [(use (match_operand:SI 0 "register_operand" "r")) 974 (return)] 975 "" 976 "b %0" 977 [(set_attr "type" "uibranch")] 978 ) 979 980 (define_insn "return" 981 [(return)] 982 "lm32_can_use_return ()" 983 "ret" 984 [(set_attr "type" "uibranch")] 985 ) 986 987 ;; --------------------------------- 988 ;; switch/case statements 989 ;; --------------------------------- 990 991 (define_expand "tablejump" 992 [(set (pc) (match_operand 0 "register_operand" "")) 993 (use (label_ref (match_operand 1 "" "")))] 994 "" 995 " 996 { 997 rtx target = operands[0]; 998 if (flag_pic) 999 { 1000 /* For PIC, the table entry is relative to the start of the table. */ 1001 rtx label = gen_reg_rtx (SImode); 1002 target = gen_reg_rtx (SImode); 1003 emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1])); 1004 emit_insn (gen_addsi3 (target, operands[0], label)); 1005 } 1006 emit_jump_insn (gen_tablejumpsi (target, operands[1])); 1007 DONE; 1008 }") 1009 1010 (define_insn "tablejumpsi" 1011 [(set (pc) (match_operand:SI 0 "register_operand" "r")) 1012 (use (label_ref (match_operand 1 "" "")))] 1013 "" 1014 "b %0" 1015 [(set_attr "type" "ubranch")] 1016 ) 1017 1018 ;; --------------------------------- 1019 ;; arithmetic 1020 ;; --------------------------------- 1021 1022 (define_insn "addsi3" 1023 [(set (match_operand:SI 0 "register_operand" "=r,r") 1024 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1025 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 1026 "" 1027 "@ 1028 add %0, %z1, %2 1029 addi %0, %z1, %2" 1030 [(set_attr "type" "arith")] 1031 ) 1032 1033 (define_insn "subsi3" 1034 [(set (match_operand:SI 0 "register_operand" "=r") 1035 (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") 1036 (match_operand:SI 2 "register_or_zero_operand" "rJ")))] 1037 "" 1038 "sub %0, %z1, %z2" 1039 [(set_attr "type" "arith")] 1040 ) 1041 1042 (define_insn "mulsi3" 1043 [(set (match_operand:SI 0 "register_operand" "=r,r") 1044 (mult:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1045 (match_operand:SI 2 "register_or_K_operand" "r,K")))] 1046 "TARGET_MULTIPLY_ENABLED" 1047 "@ 1048 mul %0, %z1, %2 1049 muli %0, %z1, %2" 1050 [(set_attr "type" "multiply")] 1051 ) 1052 1053 (define_insn "udivsi3" 1054 [(set (match_operand:SI 0 "register_operand" "=r") 1055 (udiv:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") 1056 (match_operand:SI 2 "register_operand" "r")))] 1057 "TARGET_DIVIDE_ENABLED" 1058 "divu %0, %z1, %2" 1059 [(set_attr "type" "divide")] 1060 ) 1061 1062 (define_insn "umodsi3" 1063 [(set (match_operand:SI 0 "register_operand" "=r") 1064 (umod:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") 1065 (match_operand:SI 2 "register_operand" "r")))] 1066 "TARGET_DIVIDE_ENABLED" 1067 "modu %0, %z1, %2" 1068 [(set_attr "type" "divide")] 1069 ) 1070 1071 ;; --------------------------------- 1072 ;; negation and inversion 1073 ;; --------------------------------- 1074 1075 (define_insn "negsi2" 1076 [(set (match_operand:SI 0 "register_operand" "=r") 1077 (neg:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))] 1078 "" 1079 "sub %0, r0, %z1" 1080 [(set_attr "type" "arith")] 1081 ) 1082 1083 (define_insn "one_cmplsi2" 1084 [(set (match_operand:SI 0 "register_operand" "=r") 1085 (not:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))] 1086 "" 1087 "not %0, %z1" 1088 [(set_attr "type" "arith")] 1089 ) 1090 1091 ;; --------------------------------- 1092 ;; logical 1093 ;; --------------------------------- 1094 1095 (define_insn "andsi3" 1096 [(set (match_operand:SI 0 "register_operand" "=r,r") 1097 (and:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1098 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1099 "" 1100 "@ 1101 and %0, %z1, %2 1102 andi %0, %z1, %2" 1103 [(set_attr "type" "arith")] 1104 ) 1105 1106 (define_insn "iorsi3" 1107 [(set (match_operand:SI 0 "register_operand" "=r,r") 1108 (ior:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1109 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1110 "" 1111 "@ 1112 or %0, %z1, %2 1113 ori %0, %z1, %2" 1114 [(set_attr "type" "arith")] 1115 ) 1116 1117 (define_insn "xorsi3" 1118 [(set (match_operand:SI 0 "register_operand" "=r,r") 1119 (xor:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1120 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1121 "" 1122 "@ 1123 xor %0, %z1, %2 1124 xori %0, %z1, %2" 1125 [(set_attr "type" "arith")] 1126 ) 1127 1128 (define_insn "*norsi3" 1129 [(set (match_operand:SI 0 "register_operand" "=r,r") 1130 (not:SI (ior:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1131 (match_operand:SI 2 "register_or_L_operand" "r,L"))))] 1132 "" 1133 "@ 1134 nor %0, %z1, %2 1135 nori %0, %z1, %2" 1136 [(set_attr "type" "arith")] 1137 ) 1138 1139 (define_insn "*xnorsi3" 1140 [(set (match_operand:SI 0 "register_operand" "=r,r") 1141 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1142 (match_operand:SI 2 "register_or_L_operand" "r,L"))))] 1143 "" 1144 "@ 1145 xnor %0, %z1, %2 1146 xnori %0, %z1, %2" 1147 [(set_attr "type" "arith")] 1148 ) 1149 1150 ;; --------------------------------- 1151 ;; shifts 1152 ;; --------------------------------- 1153 1154 (define_insn "ashlsi3" 1155 [(set (match_operand:SI 0 "register_operand" "=r,r") 1156 (ashift:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1157 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1158 "TARGET_BARREL_SHIFT_ENABLED" 1159 "@ 1160 sl %0, %z1, %2 1161 sli %0, %z1, %2" 1162 [(set_attr "type" "shift")] 1163 ) 1164 1165 (define_insn "ashrsi3" 1166 [(set (match_operand:SI 0 "register_operand" "=r,r") 1167 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1168 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1169 "TARGET_BARREL_SHIFT_ENABLED" 1170 "@ 1171 sr %0, %z1, %2 1172 sri %0, %z1, %2" 1173 [(set_attr "type" "shift")] 1174 ) 1175 1176 (define_insn "lshrsi3" 1177 [(set (match_operand:SI 0 "register_operand" "=r,r") 1178 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") 1179 (match_operand:SI 2 "register_or_L_operand" "r,L")))] 1180 "TARGET_BARREL_SHIFT_ENABLED" 1181 "@ 1182 sru %0, %z1, %2 1183 srui %0, %z1, %2" 1184 [(set_attr "type" "shift")] 1185 ) 1186 1187 ;; --------------------------------- 1188 ;; function entry / exit 1189 ;; --------------------------------- 1190 1191 (define_expand "prologue" 1192 [(const_int 1)] 1193 "" 1194 " 1195 { 1196 lm32_expand_prologue (); 1197 DONE; 1198 }") 1199 1200 (define_expand "epilogue" 1201 [(return)] 1202 "" 1203 " 1204 { 1205 lm32_expand_epilogue (); 1206 DONE; 1207 }") 1208 1209 ;; --------------------------------- 1210 ;; nop 1211 ;; --------------------------------- 1212 1213 (define_insn "nop" 1214 [(const_int 0)] 1215 "" 1216 "nop" 1217 [(set_attr "type" "arith")] 1218 ) 1219 1220 ;; --------------------------------- 1221 ;; blockage 1222 ;; --------------------------------- 1223 1224 ;; used to stop the scheduler from 1225 ;; scheduling code across certain boundaries 1226 1227 (define_insn "blockage" 1228 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 1229 "" 1230 "" 1231 [(set_attr "length" "0")] 1232 ) 1233 -
gcc/config/lm32/lm32.opt
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.opt gcc-4.4.6/gcc/config/lm32/lm32.opt
old new 1 ; Options for the Lattice Mico32 port of the compiler. 2 ; Contributed by Jon Beniston <jon@beniston.com> 3 ; 4 ; Copyright (C) 2008 Free Software Foundation, Inc. 5 ; 6 ; This file is part of GCC. 7 ; 8 ; GCC is free software; you can redistribute it and/or modify it 9 ; under the terms of the GNU General Public License as published 10 ; by the Free Software Foundation; either version 3, or (at your 11 ; option) any later version. 12 ; 13 ; GCC is distributed in the hope that it will be useful, but WITHOUT 14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 ; License for more details. 17 ; 18 ; You should have received a copy of the GNU General Public License 19 ; along with GCC; see the file COPYING3. If not see 20 ; <http://www.gnu.org/licenses/>. 21 22 mmultiply-enabled 23 Target Report Mask(MULTIPLY_ENABLED) 24 Enable multiply instructions 25 26 mdivide-enabled 27 Target Report Mask(DIVIDE_ENABLED) 28 Enable divide and modulus instructions 29 30 mbarrel-shift-enabled 31 Target Report Mask(BARREL_SHIFT_ENABLED) 32 Enable barrel shift instructions 33 34 msign-extend-enabled 35 Target Report Mask(SIGN_EXTEND_ENABLED) 36 Enable sign extend instructions 37 38 muser-enabled 39 Target Report Mask(USER_ENABLED) 40 Enable user-defined instructions -
gcc/config/lm32/lm32-protos.h
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32-protos.h gcc-4.4.6/gcc/config/lm32/lm32-protos.h
old new 1 /* Prototypes of target machine functions, Lattice Mico32 architecture. 2 Contributed by Jon Beniston <jon@beniston.com> 3 4 Copyright (C) 2008 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 extern int lm32_return_in_memory (tree type); 23 extern void lm32_declare_object (FILE *stream, char *name, char *init_string, 24 char *final_string, int size); 25 extern int symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED); 26 extern int register_or_zero_operand (rtx op, enum machine_mode mode); 27 extern int register_or_K_operand (rtx op, enum machine_mode mode); 28 extern int constant_K_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED); 29 extern int register_or_L_operand (rtx op, enum machine_mode mode); 30 extern int constant_L_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED); 31 extern int register_or_memory_operand (rtx op, enum machine_mode mode); 32 extern int register_operand (rtx op, enum machine_mode mode); 33 extern int const_ok_for_base_offset (rtx op, enum machine_mode mode); 34 extern void lm32_expand_prologue (void); 35 extern void lm32_expand_epilogue (void); 36 extern HOST_WIDE_INT lm32_compute_frame_size (int size); 37 extern void lm32_print_operand (FILE *file, rtx op, int letter); 38 extern void lm32_print_operand_address (FILE *file, rtx addr); 39 extern rtx lm32_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, 40 tree type, int named); 41 extern void lm32_override_options (void); 42 extern HOST_WIDE_INT lm32_compute_initial_elimination_offset (int from, 43 int to); 44 extern int lm32_can_use_return (void); 45 extern rtx lm32_return_addr_rtx (int count, rtx frame); 46 #ifdef RTX_CODE 47 extern void gen_int_relational (enum rtx_code code, rtx result, rtx cmp0, 48 rtx cmp1, rtx destination); 49 #endif 50 extern int lm32_expand_block_move (rtx *); 51 extern int nonpic_symbol_mentioned_p (rtx); 52 extern rtx lm32_legitimize_pic_address (rtx, enum machine_mode, rtx); -
gcc/config/lm32/predicates.md
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/predicates.md gcc-4.4.6/gcc/config/lm32/predicates.md
old new 1 ;; Predicate definitions for Lattice Mico32. 2 ;; Contributed by Jon Beniston <jon@beniston.com> 3 ;; 4 ;; Copyright (C) 2008 Free Software Foundation, Inc. 5 ;; 6 ;; This file is part of GCC. 7 ;; 8 ;; GCC is free software; you can redistribute it and/or modify it 9 ;; under the terms of the GNU General Public License as published 10 ;; by the Free Software Foundation; either version 3, or (at your 11 ;; option) any later version. 12 ;; 13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT 14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 ;; License for more details. 17 ;; 18 ;; You should have received a copy of the GNU General Public License 19 ;; along with GCC; see the file COPYING3. If not see 20 ;; <http://www.gnu.org/licenses/>. 21 22 (define_predicate "const0_operand" 23 (and (match_code "const_int,const_double,const_vector") 24 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 25 26 (define_predicate "constant_K_operand" 27 (and (match_code "const_int") 28 (match_test "MEDIUM_INT (INTVAL (op))"))) 29 30 (define_predicate "constant_L_operand" 31 (and (match_code "const_int") 32 (match_test "MEDIUM_UINT (INTVAL (op))"))) 33 34 (define_predicate "register_or_zero_operand" 35 (ior (match_operand 0 "register_operand") 36 (match_operand 0 "const0_operand"))) 37 38 (define_predicate "register_or_memory_operand" 39 (ior (match_operand 0 "register_operand") 40 (match_operand 0 "memory_operand"))) 41 42 (define_predicate "register_or_K_operand" 43 (ior (match_operand 0 "register_operand") 44 (match_operand 0 "constant_K_operand"))) 45 46 (define_predicate "register_or_L_operand" 47 (ior (match_operand 0 "register_operand") 48 (match_operand 0 "constant_L_operand"))) 49 50 (define_predicate "reloc_operand" 51 (ior (ior (match_code "label_ref") 52 (match_code "symbol_ref")) 53 (match_code "const"))) 54 55 (define_predicate "symbolic_operand" 56 (ior (match_code "label_ref") 57 (match_code "symbol_ref"))) 58 -
gcc/config/lm32/rtems.h
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/rtems.h gcc-4.4.6/gcc/config/lm32/rtems.h
old new 1 /* Definitions for rtems targeting a lm32 using ELF. 2 Copyright (C) 2009, Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* Target OS builtins. */ 21 #undef TARGET_OS_CPP_BUILTINS 22 #define TARGET_OS_CPP_BUILTINS() \ 23 do \ 24 { \ 25 builtin_define ("__rtems__"); \ 26 builtin_define ("__USE_INIT_FINI__"); \ 27 builtin_assert ("system=rtems"); \ 28 } \ 29 while (0) 30 31 /* Use the default */ 32 #undef LINK_GCC_C_SEQUENCE_SPEC -
gcc/config/lm32/sfp-machine.h
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/sfp-machine.h gcc-4.4.6/gcc/config/lm32/sfp-machine.h
old new 1 #define _FP_W_TYPE_SIZE 32 2 #define _FP_W_TYPE unsigned long 3 #define _FP_WS_TYPE signed long 4 #define _FP_I_TYPE long 5 6 #define _FP_MUL_MEAT_S(R,X,Y) \ 7 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) 8 #define _FP_MUL_MEAT_D(R,X,Y) \ 9 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) 10 #define _FP_MUL_MEAT_Q(R,X,Y) \ 11 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) 12 13 #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y) 14 #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) 15 #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) 16 17 #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) 18 #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 19 #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 20 #define _FP_NANSIGN_S 0 21 #define _FP_NANSIGN_D 0 22 #define _FP_NANSIGN_Q 0 23 24 #define _FP_KEEPNANFRACP 1 25 26 /* Someone please check this. */ 27 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ 28 do { \ 29 if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ 30 && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ 31 { \ 32 R##_s = Y##_s; \ 33 _FP_FRAC_COPY_##wc(R,Y); \ 34 } \ 35 else \ 36 { \ 37 R##_s = X##_s; \ 38 _FP_FRAC_COPY_##wc(R,X); \ 39 } \ 40 R##_c = FP_CLS_NAN; \ 41 } while (0) 42 43 #define __LITTLE_ENDIAN 1234 44 #define __BIG_ENDIAN 4321 45 46 #define __BYTE_ORDER __BIG_ENDIAN 47 48 /* Define ALIASNAME as a strong alias for NAME. */ 49 # define strong_alias(name, aliasname) _strong_alias(name, aliasname) 50 # define _strong_alias(name, aliasname) \ 51 extern __typeof (name) aliasname __attribute__ ((alias (#name))); -
gcc/config/lm32/t-fprules-softfp
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/t-fprules-softfp gcc-4.4.6/gcc/config/lm32/t-fprules-softfp
old new 1 softfp_float_modes := sf df 2 softfp_int_modes := si di 3 softfp_extensions := sfdf 4 softfp_truncations := dfsf 5 softfp_machine_header := lm32/sfp-machine.h -
gcc/config/lm32/t-lm32
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/t-lm32 gcc-4.4.6/gcc/config/lm32/t-lm32
old new 1 LIB1ASMSRC = lm32/lib1funcs.S 2 LIB1ASMFUNCS = _ashlsi3 _ashrsi3 _lshrsi3 3 4 LM32_LIB1CSRC = $(srcdir)/config/lm32/arithmetic.c 5 LIB2FUNCS_EXTRA = _mulsi3.c \ 6 _udivmodsi4.c _divsi3.c _modsi3.c _udivsi3.c _umodsi3.c 7 # Size optimised versions: _ashlsi3.c _ashrsi3.c _lshrsi3.c 8 9 # The fixed-point arithmetic code is in one file 10 # similar to libgcc2.c (or the old libgcc1.c). We need to 11 # "split it up" with one file per define. 12 $(LIB2FUNCS_EXTRA): $(LM32_LIB1CSRC) 13 name=`echo $@ | sed -e 's,.*/,,' | sed -e 's,.c$$,,'`; \ 14 echo "#define L$$name" > tmp-$@ \ 15 && echo '#include "$<"' >> tmp-$@ \ 16 && mv -f tmp-$@ $@ 17 18 MULTILIB_OPTIONS = mmultiply-enabled mbarrel-shift-enabled 19 # Don't bother building multilib with mdivide-enabled, not much of a gain -
gcc/config/lm32/uclinux-elf.h
diff -Naur gcc-4.4.6.orig/gcc/config/lm32/uclinux-elf.h gcc-4.4.6/gcc/config/lm32/uclinux-elf.h
old new 1 /* Definitions for LM32 running Linux-based GNU systems using ELF 2 Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 3 2008 Free Software Foundation, Inc. 4 Contributed by Philip Blundell <philb@gnu.org> 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* elfos.h should have already been included. Now just override 23 any conflicting definitions and add any extras. */ 24 25 /* Run-time Target Specification. */ 26 #undef TARGET_VERSION 27 #define TARGET_VERSION fputs (" (LM32 GNU/Linux with ELF)", stderr); 28 29 /* Do not assume anything about header files. */ 30 #undef NO_IMPLICIT_EXTERN_C 31 #define NO_IMPLICIT_EXTERN_C 32 33 /* The GNU C++ standard library requires that these macros be defined. */ 34 #undef CPLUSPLUS_CPP_SPEC 35 #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" 36 37 /* Now we define the strings used to build the spec file. */ 38 #undef LIB_SPEC 39 #define LIB_SPEC \ 40 "%{pthread:-lpthread} \ 41 %{shared:-lc} \ 42 %{!shared:-lc} " 43 44 #define LIBGCC_SPEC "-lgcc" 45 46 /* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add 47 the GNU/Linux magical crtbegin.o file (see crtstuff.c) which 48 provides part of the support for getting C++ file-scope static 49 object constructed before entering `main'. */ 50 51 #undef STARTFILE_SPEC 52 #define STARTFILE_SPEC \ 53 "%{!shared: \ 54 %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \ 55 %{!p:%{profile:gcrt1.o%s} \ 56 %{!profile:crt1.o%s}}}} \ 57 crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" 58 59 /* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on 60 the GNU/Linux magical crtend.o file (see crtstuff.c) which 61 provides part of the support for getting C++ file-scope static 62 object constructed before entering `main', followed by a normal 63 GNU/Linux "finalizer" file, `crtn.o'. */ 64 65 #undef ENDFILE_SPEC 66 #define ENDFILE_SPEC \ 67 "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" 68 69 #undef LINK_SPEC 70 #define LINK_SPEC "%{h*} %{version:-v} \ 71 %{b} %{Wl,*:%*} \ 72 %{static:-Bstatic} \ 73 %{shared:-shared} \ 74 %{symbolic:-Bsymbolic} \ 75 %{rdynamic:-export-dynamic} \ 76 %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}" 77 78 #define TARGET_OS_CPP_BUILTINS() LINUX_TARGET_OS_CPP_BUILTINS() 79 80 #define LINK_GCC_C_SEQUENCE_SPEC \ 81 "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}" 82 83 #undef CC1_SPEC 84 #define CC1_SPEC "%{G*} %{!fno-PIC:-fPIC}" 85 -
gcc/config/m32c/rtems.h
diff -Naur gcc-4.4.6.orig/gcc/config/m32c/rtems.h gcc-4.4.6/gcc/config/m32c/rtems.h
old new 29 29 } \ 30 30 while (0) 31 31 32 /* Use the default */32 /* Use the defaults */ 33 33 #undef LINK_GCC_C_SEQUENCE_SPEC 34 35 #undef WCHAR_TYPE 36 37 #undef WCHAR_TYPE_SIZE -
gcc/config/m68k/rtemself.h
diff -Naur gcc-4.4.6.orig/gcc/config/m68k/rtemself.h gcc-4.4.6/gcc/config/m68k/rtemself.h
old new 31 31 builtin_assert ("system=rtems"); \ 32 32 } \ 33 33 while (0) 34 35 /* Use the defaults */ 36 #undef WCHAR_TYPE 37 38 #undef WCHAR_TYPE_SIZE -
gcc/config/mips/elf.h
diff -Naur gcc-4.4.6.orig/gcc/config/mips/elf.h gcc-4.4.6/gcc/config/mips/elf.h
old new 48 48 #undef ENDFILE_SPEC 49 49 #define ENDFILE_SPEC "crtend%O%s crtn%O%s" 50 50 51 #define NO_IMPLICIT_EXTERN_C 152 53 51 #define HANDLE_PRAGMA_PACK_PUSH_POP 1 -
gcc/config/rs6000/rtems.h
diff -Naur gcc-4.4.6.orig/gcc/config/rs6000/rtems.h gcc-4.4.6/gcc/config/rs6000/rtems.h
old new 49 49 %{mcpu=604: %{!Dppc*: %{!Dmpc*: -Dmpc604} } } \ 50 50 %{mcpu=750: %{!Dppc*: %{!Dmpc*: -Dmpc750} } } \ 51 51 %{mcpu=821: %{!Dppc*: %{!Dmpc*: -Dmpc821} } } \ 52 %{mcpu=860: %{!Dppc*: %{!Dmpc*: -Dmpc860} } }" 52 %{mcpu=860: %{!Dppc*: %{!Dmpc*: -Dmpc860} } } \ 53 %{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540} } }" 53 54 54 55 #undef SUBSUBTARGET_EXTRA_SPECS 55 56 #define SUBSUBTARGET_EXTRA_SPECS \ 56 57 { "cpp_os_rtems", CPP_OS_RTEMS_SPEC } 58 59 #undef SUBSUBTARGET_OVERRIDE_OPTIONS 60 #define SUBSUBTARGET_OVERRIDE_OPTIONS \ 61 do { \ 62 if (TARGET_E500) \ 63 { \ 64 rs6000_float_gprs = 1; \ 65 } \ 66 } while(0) 67 68 #undef WCHAR_TYPE 69 70 #undef WCHAR_TYPE_SIZE -
gcc/config/rs6000/t-rtems
diff -Naur gcc-4.4.6.orig/gcc/config/rs6000/t-rtems gcc-4.4.6/gcc/config/rs6000/t-rtems
old new 1 1 # Multilibs for powerpc RTEMS targets. 2 # 3 # Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc. 4 # 5 # This file is part of GCC. 6 # 7 # GCC is free software; you can redistribute it and/or modify 8 # it under the terms of the GNU General Public License as published by 9 # the Free Software Foundation; either version 3, or (at your option) 10 # any later version. 11 # 12 # GCC is distributed in the hope that it will be useful, 13 # but WITHOUT ANY WARRANTY; without even the implied warranty of 14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 # GNU General Public License for more details. 16 # 17 # You should have received a copy of the GNU General Public License 18 # along with GCC; see the file COPYING3. If not see 19 # <http://www.gnu.org/licenses/>. 2 20 3 21 MULTILIB_OPTIONS = \ 4 mcpu=403/mcpu=505/mcpu=601/mcpu=603e/mcpu=604/mcpu=860/mcpu=7400 \ 5 Dmpc8260 \ 22 mcpu=403/mcpu=505/mcpu=601/mcpu=603e/mcpu=604/mcpu=860/mcpu=7400/mcpu=8540 \ 6 23 msoft-float 7 24 8 25 MULTILIB_DIRNAMES = \ 9 m403 m505 m601 m603e m604 m860 m7400 \ 10 mpc8260 \ 26 m403 m505 m601 m603e m604 m860 m7400 m8540 \ 11 27 nof 12 28 13 29 # MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT} … … 29 45 # Map 750 to . 30 46 MULTILIB_MATCHES += mcpu?750= 31 47 48 # Map 8548 to 8540 49 MULTILIB_MATCHES += mcpu?8540=mcpu?8548 50 32 51 # Soft-float only, default implies msoft-float 33 52 # NOTE: Must match with MULTILIB_MATCHES_FLOAT and MULTILIB_MATCHES 34 53 MULTILIB_SOFTFLOAT_ONLY = \ … … 55 74 56 75 # Special rules 57 76 # Take out all variants we don't want 58 MULTILIB_EXCEPTIONS += *mcpu=403/Dmpc*59 MULTILIB_EXCEPTIONS += *mcpu=505/Dmpc*60 MULTILIB_EXCEPTIONS += *mcpu=601/Dmpc*61 MULTILIB_EXCEPTIONS += *mcpu=604/Dmpc*62 MULTILIB_EXCEPTIONS += *mcpu=750/Dmpc*63 MULTILIB_EXCEPTIONS += *mcpu=860/Dmpc*64 MULTILIB_EXCEPTIONS += *mcpu=7400/Dmpc* -
gcc/config/rtems.h
diff -Naur gcc-4.4.6.orig/gcc/config/rtems.h gcc-4.4.6/gcc/config/rtems.h
old new 38 38 #undef LIB_SPEC 39 39 #define LIB_SPEC "%{!qrtems: " STD_LIB_SPEC "} " \ 40 40 "%{!nostdlib: %{qrtems: --start-group \ 41 %{!qrtems_debug: -lrtemsbsp -lrtemscpu} \ 42 %{qrtems_debug: -lrtemsbsp_g -lrtemscpu_g} \ 41 -lrtemsbsp -lrtemscpu \ 43 42 -lc -lgcc --end-group %{!qnolinkcmds: -T linkcmds%s}}}" -
gcc/config/sh/rtemself.h
diff -Naur gcc-4.4.6.orig/gcc/config/sh/rtemself.h gcc-4.4.6/gcc/config/sh/rtemself.h
old new 24 24 builtin_define( "__rtems__" ); \ 25 25 builtin_assert( "system=rtems" ); \ 26 26 } while (0) 27 28 /* Use the defaults */ 29 #undef WCHAR_TYPE 30 31 #undef WCHAR_TYPE_SIZE -
gcc/config/sparc/rtemself.h
diff -Naur gcc-4.4.6.orig/gcc/config/sparc/rtemself.h gcc-4.4.6/gcc/config/sparc/rtemself.h
old new 29 29 } \ 30 30 while (0) 31 31 32 /* Use the default */32 /* Use the defaults */ 33 33 #undef LINK_GCC_C_SEQUENCE_SPEC 34 35 #undef WCHAR_TYPE 36 37 #undef WCHAR_TYPE_SIZE -
gcc/config.gcc
diff -Naur gcc-4.4.6.orig/gcc/config.gcc gcc-4.4.6/gcc/config.gcc
old new 1377 1377 out_file=iq2000/iq2000.c 1378 1378 md_file=iq2000/iq2000.md 1379 1379 ;; 1380 lm32-*-elf*) 1381 tm_file="dbxelf.h elfos.h ${tm_file}" 1382 tmake_file="lm32/t-lm32" 1383 tmake_file="${tmake_file} lm32/t-fprules-softfp soft-fp/t-softfp" 1384 ;; 1385 lm32-*-rtems*) 1386 tm_file="dbxelf.h elfos.h ${tm_file} lm32/rtems.h rtems.h" 1387 tmake_file="lm32/t-lm32" 1388 tmake_file="${tmake_file} lm32/t-fprules-softfp soft-fp/t-softfp" 1389 tmake_file="${tmake_file} t-rtems" 1390 extra_parts="crtbegin.o crtend.o crti.o crtn.o" 1391 ;; 1392 lm32-*-uclinux*) 1393 tm_file="dbxelf.h elfos.h ${tm_file} linux.h lm32/uclinux-elf.h" 1394 tmake_file="lm32/t-lm32" 1395 tmake_file="${tmake_file} lm32/t-fprules-softfp soft-fp/t-softfp" 1396 ;; 1380 1397 m32r-*-elf*) 1381 1398 tm_file="dbxelf.h elfos.h svr4.h ${tm_file}" 1382 1399 extra_parts="crtinit.o crtfini.o" -
gcc/doc/contrib.texi
diff -Naur gcc-4.4.6.orig/gcc/doc/contrib.texi gcc-4.4.6/gcc/doc/contrib.texi
old new 55 55 Wolfgang Bangerth for processing tons of bug reports. 56 56 57 57 @item 58 Jon Beniston for his Microsoft Windows port of Java .58 Jon Beniston for his Microsoft Windows port of Java and port to Lattice Mico32. 59 59 60 60 @item 61 61 Daniel Berlin for better DWARF2 support, faster/better optimizations, -
gcc/doc/install.texi
diff -Naur gcc-4.4.6.orig/gcc/doc/install.texi gcc-4.4.6/gcc/doc/install.texi
old new 2660 2660 @item 2661 2661 @uref{#iq2000-x-elf,,iq2000-*-elf} 2662 2662 @item 2663 @uref{#lm32-x-elf,,lm32-*-elf} 2664 @item 2665 @uref{#lm32-x-uclinux,,lm32-*-uclinux} 2666 @item 2663 2667 @uref{#m32c-x-elf,,m32c-*-elf} 2664 2668 @item 2665 2669 @uref{#m32r-x-elf,,m32r-*-elf} … … 3472 3476 @html 3473 3477 <hr /> 3474 3478 @end html 3479 @heading @anchor{lm32-x-elf}lm32-*-elf 3480 Lattice Mico32 processor. 3481 This configuration is intended for embedded systems. 3482 3483 @html 3484 <hr /> 3485 @end html 3486 @heading @anchor{lm32-x-uclinux}lm32-*-uclinux 3487 Lattice Mico32 processor. 3488 This configuration is intended for embedded systems running uClinux. 3489 3490 @html 3491 <hr /> 3492 @end html 3475 3493 @heading @anchor{m32c-x-elf}m32c-*-elf 3476 3494 Renesas M32C processor. 3477 3495 This configuration is intended for embedded systems. -
gcc/doc/invoke.texi
diff -Naur gcc-4.4.6.orig/gcc/doc/invoke.texi gcc-4.4.6/gcc/doc/invoke.texi
old new 610 610 -mno-sched-prefer-non-control-spec-insns @gol 611 611 -mno-sched-count-spec-in-critical-path} 612 612 613 @emph{LM32 Options} 614 @gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol 615 -msign-extend-enabled -muser-enabled} 616 613 617 @emph{M32R/D Options} 614 618 @gccoptlist{-m32r2 -m32rx -m32r @gol 615 619 -mdebug @gol … … 8858 8862 * i386 and x86-64 Options:: 8859 8863 * i386 and x86-64 Windows Options:: 8860 8864 * IA-64 Options:: 8865 * LM32 Options:: 8861 8866 * M32C Options:: 8862 8867 * M32R/D Options:: 8863 8868 * M680x0 Options:: … … 11907 11912 11908 11913 @end table 11909 11914 11915 @node LM32 Options 11916 @subsection LM32 Options 11917 @cindex LM32 options 11918 11919 These @option{-m} options are defined for the Lattice Mico32 architecture: 11920 11921 @table @gcctabopt 11922 @item -mbarrel-shift-enabled 11923 @opindex mbarrel-shift-enabled 11924 Enable barrel-shift instructions. 11925 11926 @item -mdivide-enabled 11927 @opindex mdivide-enabled 11928 Enable divide and modulus instructions. 11929 11930 @item -mmultiply-enabled 11931 @opindex multiply-enabled 11932 Enable multiply instructions. 11933 11934 @item -msign-extend-enabled 11935 @opindex msign-extend-enabled 11936 Enable sign extend instructions. 11937 11938 @item -muser-enabled 11939 @opindex muser-enabled 11940 Enable user-defined instructions. 11941 11942 @end table 11943 11910 11944 @node M32R/D Options 11911 11945 @subsection M32R/D Options 11912 11946 @cindex M32R/D options -
libgcc/ChangeLog.rtems
diff -Naur gcc-4.4.6.orig/libgcc/ChangeLog.rtems gcc-4.4.6/libgcc/ChangeLog.rtems
old new 1 Jon Beniston <jon@beniston.com> 2 3 * libgcc/config/lm32/t-elf, libgcc/config/lm32/t-uclinux, 4 libgcc/config/lm32/t-uclinux: New (lm32 port). 5 * libgcc/config.host: Add lm32* targets. -
libgcc/config/lm32/t-elf
diff -Naur gcc-4.4.6.orig/libgcc/config/lm32/t-elf gcc-4.4.6/libgcc/config/lm32/t-elf
old new 1 # Assemble startup files. 2 3 $(T)crti.o: $(gcc_srcdir)/config/lm32/crti.S $(GCC_PASSES) 4 $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ 5 -c -o $(T)crti.o -x assembler-with-cpp $(gcc_srcdir)/config/lm32/crti.S 6 7 $(T)crtn.o: $(gcc_srcdir)/config/lm32/crtn.S $(GCC_PASSES) 8 $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ 9 -c -o $(T)crtn.o -x assembler-with-cpp $(gcc_srcdir)/config/lm32/crtn.S 10 11 CRTSTUFF_T_CFLAGS = -G 0 12 TARGET_LIBGCC2_CFLAGS = -G 0 -
libgcc/config/lm32/t-uclinux
diff -Naur gcc-4.4.6.orig/libgcc/config/lm32/t-uclinux gcc-4.4.6/libgcc/config/lm32/t-uclinux
old new 1 CRTSTUFF_T_CFLAGS = -fPIC 2 TARGET_LIBGCC2_CFLAGS = -fPIC -
libgcc/config.host
diff -Naur gcc-4.4.6.orig/libgcc/config.host gcc-4.4.6/libgcc/config.host
old new 95 95 hppa*-*-*) 96 96 cpu_type=pa 97 97 ;; 98 lm32*-*-*) 99 cpu_type=lm32 100 ;; 98 101 m32r*-*-*) 99 102 cpu_type=m32r 100 103 ;; … … 355 358 ;; 356 359 iq2000*-*-elf*) 357 360 ;; 361 lm32-*-elf* | lm32-*-rtems*) 362 extra_parts="crtbegin.o crtend.o crti.o crtn.o" 363 tmake_file="lm32/t-elf" 364 ;; 365 lm32-*-uclinux*) 366 extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o" 367 tmake_file="lm32/t-uclinux" 368 ;; 358 369 m32r-*-elf*|m32r-*-rtems*) 359 370 ;; 360 371 m32rle-*-elf*)
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