source: rtems/contrib/crossrpms/patches/gcc-core-4.4.6-rtems4.10-20110420.diff @ 7c2d5b4

4.10
Last change on this file since 7c2d5b4 was 7c2d5b4, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 20, 2011 at 3:35:22 PM

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[7c2d5b4]1diff -Naur gcc-4.4.6.orig/ChangeLog.rtems gcc-4.4.6/ChangeLog.rtems
2--- gcc-4.4.6.orig/ChangeLog.rtems      1970-01-01 01:00:00.000000000 +0100
3+++ gcc-4.4.6/ChangeLog.rtems   2011-04-20 17:27:23.044805682 +0200
4@@ -0,0 +1,9 @@
5+2011-04-20     Ralf Corsépius <ralf.corsepius@rtems.org>
6+
7+       * configure, configure.ac (PPL): Merge gcc-4.6.0's ppl detection
8+         (Work-around build breakdown on fedora 15).
9+
10+               Ralf Corsépius <ralf.corsepius@rtems.org>
11+
12+       * configure, configure.ac (skipdirs): Add target-libiberty.
13+
14diff -Naur gcc-4.4.6.orig/configure gcc-4.4.6/configure
15--- gcc-4.4.6.orig/configure    2010-10-02 13:40:32.000000000 +0200
16+++ gcc-4.4.6/configure 2011-04-20 17:27:23.049805736 +0200
17@@ -935,7 +935,8 @@
18   --enable-gold           use gold instead of ld
19   --enable-libada         build libada directory
20   --enable-libssp         build libssp directory
21-  --disable-ppl-version-check    disable check for PPL version
22+  --disable-ppl-version-check
23+                          disable check for PPL version
24   --disable-cloog-version-check  disable check for CLooG version
25   --enable-stage1-languages[=all]   choose additional languages to build during
26                           stage1.  Mostly useful for compiler development.
27@@ -971,11 +972,12 @@
28   --with-gmp-lib=PATH     specify directory for the installed GMP library
29   --with-host-libstdcxx=L Use linker arguments L to link with libstdc++
30                           when linking with PPL
31-  --with-ppl=PATH         Specify prefix directory for the installed PPL package
32-                          Equivalent to --with-ppl-include=PATH/include
33-                          plus --with-ppl-lib=PATH/lib
34-  --with-ppl-include=PATH Specify directory for installed PPL include files
35-  --with-ppl-lib=PATH     Specify the directory for the installed PPL library
36+  --with-ppl=PATH         specify prefix directory for the installed PPL
37+                          package. Equivalent to
38+                          --with-ppl-include=PATH/include plus
39+                          --with-ppl-lib=PATH/lib
40+  --with-ppl-include=PATH specify directory for installed PPL include files
41+  --with-ppl-lib=PATH     specify directory for the installed PPL library
42   --with-cloog=PATH       Specify prefix directory for the installed CLooG-PPL package
43                           Equivalent to --with-cloog-include=PATH/include
44                           plus --with-cloog-lib=PATH/lib
45@@ -2267,6 +2269,7 @@
46     noconfigdirs="$noconfigdirs target-newlib target-libiberty target-libgloss ${libgcj} target-libmudflap"
47     ;;
48   *-*-rtems*)
49+    skipdirs="$skipdirs target-libiberty"
50     noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
51     ;;
52     # The tpf target doesn't support gdb yet.
53@@ -4829,10 +4832,9 @@
54 esac
55 
56 # Check for PPL
57-ppl_major_version=0
58-ppl_minor_version=10
59-ppllibs=" -lppl_c -lppl -lgmpxx $with_host_libstdcxx "
60+ppllibs=
61 pplinc=
62+pwllib=
63 
64 
65 # Check whether --with-ppl or --without-ppl was given.
66@@ -4841,55 +4843,143 @@
67 
68 fi;
69 
70-# Check whether --with-ppl_include or --without-ppl_include was given.
71+# Check whether --with-ppl-include or --without-ppl-include was given.
72 if test "${with_ppl_include+set}" = set; then
73   withval="$with_ppl_include"
74 
75 fi;
76 
77-# Check whether --with-ppl_lib or --without-ppl_lib was given.
78+# Check whether --with-ppl-lib or --without-ppl-lib was given.
79 if test "${with_ppl_lib+set}" = set; then
80   withval="$with_ppl_lib"
81 
82 fi;
83 
84+# Check whether --enable-ppl-version-check or --disable-ppl-version-check was given.
85+if test "${enable_ppl_version_check+set}" = set; then
86+  enableval="$enable_ppl_version_check"
87+
88+fi;
89+
90 case $with_ppl in
91-  no)
92-    ppllibs=
93+  yes | no | "")
94     ;;
95   *)
96-    ppllibs="-L$with_ppl/lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"
97+    ppllibs="-L$with_ppl/lib"
98     pplinc="-I$with_ppl/include $pplinc"
99-    LIBS="$ppllibs $LIBS"
100+    if test -d "$with_ppl/lib" && test -d "$with_ppl/include"; then
101+      with_ppl=yes
102+    else
103+      { { echo "$as_me:$LINENO: error: cannot find directories \"$with_ppl/lib\" or \"$with_ppl/include\"" >&5
104+echo "$as_me: error: cannot find directories \"$with_ppl/lib\" or \"$with_ppl/include\"" >&2;}
105+   { (exit 1); exit 1; }; }
106+    fi
107     ;;
108 esac
109-if test "x$with_ppl_include" != x; then
110+
111+if test x"$with_ppl_include" != x; then
112   pplinc="-I$with_ppl_include $pplinc"
113+  with_ppl=yes
114 fi
115+
116 if test "x$with_ppl_lib" != x; then
117-  ppllibs="-L$with_ppl_lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"
118-  LIBS="$ppllibs $LIBS"
119+  ppllibs="-L$with_ppl_lib"
120+  with_ppl=yes
121 fi
122-if test "x$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then
123-  ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/.libs -L$$r/$(HOST_SUBDIR)/ppl/_libs -lppl_c -lppl -lgmpxx '"$with_host_libstdcxx "
124-  pplinc='-I$$r/$(HOST_SUBDIR)/ppl/include -I$$s/ppl/include '
125-  LIBS="$ppllibs $LIBS"
126+
127+if test x"$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then
128+  if test x"$enable_watchdog" = xyes; then
129+    pwllib="-lpwl"
130+  fi
131+  ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/interfaces/C/'"$lt_cv_objdir"' -L$$r/$(HOST_SUBDIR)/ppl/src/'"$lt_cv_objdir"
132+  pplinc='-I$$r/$(HOST_SUBDIR)/ppl/src -I$$r/$(HOST_SUBDIR)/ppl/interfaces/C '
133+  enable_ppl_version_check=no
134+  with_ppl=yes
135 fi
136 
137-# Check whether --enable-ppl-version-check or --disable-ppl-version-check was given.
138-if test "${enable_ppl_version_check+set}" = set; then
139-  enableval="$enable_ppl_version_check"
140-  ENABLE_PPL_CHECK=$enableval
141+if test "x$with_ppl" != xno; then
142+  if test "x$pwllib" = x; then
143+    saved_LDFLAGS="$LDFLAGS"
144+    LDFLAGS="$LDFLAGS $ppllibs"
145+    echo "$as_me:$LINENO: checking for PWL_handle_timeout in -lpwl" >&5
146+echo $ECHO_N "checking for PWL_handle_timeout in -lpwl... $ECHO_C" >&6
147+if test "${ac_cv_lib_pwl_PWL_handle_timeout+set}" = set; then
148+  echo $ECHO_N "(cached) $ECHO_C" >&6
149 else
150-  ENABLE_PPL_CHECK=yes
151-fi;
152+  ac_check_lib_save_LIBS=$LIBS
153+LIBS="-lpwl  $LIBS"
154+cat >conftest.$ac_ext <<_ACEOF
155+/* confdefs.h.  */
156+_ACEOF
157+cat confdefs.h >>conftest.$ac_ext
158+cat >>conftest.$ac_ext <<_ACEOF
159+/* end confdefs.h.  */
160 
161-if test "${ENABLE_PPL_CHECK}" = "yes"; then
162-  saved_CFLAGS="$CFLAGS"
163-  CFLAGS="$CFLAGS $pplinc $gmpinc"
164-  echo "$as_me:$LINENO: checking for version $ppl_major_version.$ppl_minor_version of PPL" >&5
165-echo $ECHO_N "checking for version $ppl_major_version.$ppl_minor_version of PPL... $ECHO_C" >&6
166-  cat >conftest.$ac_ext <<_ACEOF
167+/* Override any gcc2 internal prototype to avoid an error.  */
168+#ifdef __cplusplus
169+extern "C"
170+#endif
171+/* We use char because int might match the return type of a gcc2
172+   builtin and then its argument prototype would still apply.  */
173+char PWL_handle_timeout ();
174+int
175+main ()
176+{
177+PWL_handle_timeout ();
178+  ;
179+  return 0;
180+}
181+_ACEOF
182+rm -f conftest.$ac_objext conftest$ac_exeext
183+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
184+  (eval $ac_link) 2>conftest.er1
185+  ac_status=$?
186+  grep -v '^ *+' conftest.er1 >conftest.err
187+  rm -f conftest.er1
188+  cat conftest.err >&5
189+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
190+  (exit $ac_status); } &&
191+        { ac_try='test -z "$ac_c_werror_flag"
192+                        || test ! -s conftest.err'
193+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
194+  (eval $ac_try) 2>&5
195+  ac_status=$?
196+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
197+  (exit $ac_status); }; } &&
198+        { ac_try='test -s conftest$ac_exeext'
199+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
200+  (eval $ac_try) 2>&5
201+  ac_status=$?
202+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
203+  (exit $ac_status); }; }; then
204+  ac_cv_lib_pwl_PWL_handle_timeout=yes
205+else
206+  echo "$as_me: failed program was:" >&5
207+sed 's/^/| /' conftest.$ac_ext >&5
208+
209+ac_cv_lib_pwl_PWL_handle_timeout=no
210+fi
211+rm -f conftest.err conftest.$ac_objext \
212+      conftest$ac_exeext conftest.$ac_ext
213+LIBS=$ac_check_lib_save_LIBS
214+fi
215+echo "$as_me:$LINENO: result: $ac_cv_lib_pwl_PWL_handle_timeout" >&5
216+echo "${ECHO_T}$ac_cv_lib_pwl_PWL_handle_timeout" >&6
217+if test $ac_cv_lib_pwl_PWL_handle_timeout = yes; then
218+  pwllib="-lpwl"
219+fi
220+
221+    LDFLAGS="$saved_LDFLAGS"
222+  fi
223+
224+  ppllibs="$ppllibs -lppl_c -lppl $pwllib -lgmpxx"
225+
226+  if test "$enable_ppl_version_check" != no; then
227+    saved_CFLAGS="$CFLAGS"
228+    CFLAGS="$CFLAGS $pplinc $gmpinc"
229+    echo "$as_me:$LINENO: checking for version 0.10 (revision 0 or later) of PPL" >&5
230+echo $ECHO_N "checking for version 0.10 (revision 0 or later) of PPL... $ECHO_C" >&6
231+    cat >conftest.$ac_ext <<_ACEOF
232 /* confdefs.h.  */
233 _ACEOF
234 cat confdefs.h >>conftest.$ac_ext
235@@ -4900,9 +4990,9 @@
236 main ()
237 {
238 
239-  #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
240-  choke me
241-  #endif
242+    #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
243+    choke me
244+    #endif
245 
246   ;
247   return 0;
248@@ -4937,10 +5027,11 @@
249 sed 's/^/| /' conftest.$ac_ext >&5
250 
251 echo "$as_me:$LINENO: result: no" >&5
252-echo "${ECHO_T}no" >&6; ppllibs= ; pplinc=
253+echo "${ECHO_T}no" >&6; ppllibs= ; pplinc= ; with_ppl=no
254 fi
255 rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
256-  CFLAGS="$saved_CFLAGS"
257+    CFLAGS="$saved_CFLAGS"
258+  fi
259 fi
260 
261 # Flags needed for PPL
262@@ -6259,7 +6350,7 @@
263        # to it.  This is right: we don't want to search that directory
264        # for binaries, but we want the header files in there, so add
265        # them explicitly.
266-       FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include'
267+       FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include -isystem $$r/$(HOST_SUBDIR)/gcc/include-fixed'
268 
269        # Someone might think of using the pre-installed headers on
270        # Canadian crosses, in case the installed compiler is not fully
271diff -Naur gcc-4.4.6.orig/configure.ac gcc-4.4.6/configure.ac
272--- gcc-4.4.6.orig/configure.ac 2010-10-02 13:40:32.000000000 +0200
273+++ gcc-4.4.6/configure.ac      2011-04-20 17:27:23.050805747 +0200
274@@ -502,6 +502,7 @@
275     noconfigdirs="$noconfigdirs target-newlib target-libiberty target-libgloss ${libgcj} target-libmudflap"
276     ;;
277   *-*-rtems*)
278+    skipdirs="$skipdirs target-libiberty"
279     noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
280     ;;
281     # The tpf target doesn't support gdb yet.
282@@ -1328,55 +1329,81 @@
283 esac
284 
285 # Check for PPL
286-ppl_major_version=0
287-ppl_minor_version=10
288-ppllibs=" -lppl_c -lppl -lgmpxx $with_host_libstdcxx "
289+ppllibs=
290 pplinc=
291+pwllib=
292 
293-AC_ARG_WITH(ppl, [  --with-ppl=PATH         Specify prefix directory for the installed PPL package
294-                          Equivalent to --with-ppl-include=PATH/include
295-                          plus --with-ppl-lib=PATH/lib])
296-AC_ARG_WITH(ppl_include, [  --with-ppl-include=PATH Specify directory for installed PPL include files])
297-AC_ARG_WITH(ppl_lib, [  --with-ppl-lib=PATH     Specify the directory for the installed PPL library])
298+AC_ARG_WITH(ppl,
299+[AS_HELP_STRING([--with-ppl=PATH],
300+               [specify prefix directory for the installed PPL package.
301+                Equivalent to --with-ppl-include=PATH/include
302+                plus --with-ppl-lib=PATH/lib])])
303+AC_ARG_WITH(ppl-include,
304+[AS_HELP_STRING([--with-ppl-include=PATH],
305+               [specify directory for installed PPL include files])])
306+AC_ARG_WITH(ppl-lib,
307+[AS_HELP_STRING([--with-ppl-lib=PATH],
308+               [specify directory for the installed PPL library])])
309 
310-case $with_ppl in
311-  no)
312-    ppllibs=
313+AC_ARG_ENABLE(ppl-version-check,
314+[AS_HELP_STRING([--disable-ppl-version-check],
315+               [disable check for PPL version])])
316+
317+case $with_ppl in
318+  yes | no | "")
319     ;;
320   *)
321-    ppllibs="-L$with_ppl/lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"
322+    ppllibs="-L$with_ppl/lib"
323     pplinc="-I$with_ppl/include $pplinc"
324-    LIBS="$ppllibs $LIBS"
325+    if test -d "$with_ppl/lib" && test -d "$with_ppl/include"; then
326+      with_ppl=yes
327+    else
328+      AC_MSG_ERROR([cannot find directories "$with_ppl/lib" or "$with_ppl/include"])
329+    fi
330     ;;
331 esac
332-if test "x$with_ppl_include" != x; then
333+
334+if test x"$with_ppl_include" != x; then
335   pplinc="-I$with_ppl_include $pplinc"
336+  with_ppl=yes
337 fi
338+
339 if test "x$with_ppl_lib" != x; then
340-  ppllibs="-L$with_ppl_lib -lppl_c -lppl -lgmpxx $with_host_libstdcxx"
341-  LIBS="$ppllibs $LIBS"
342+  ppllibs="-L$with_ppl_lib"
343+  with_ppl=yes
344 fi
345-if test "x$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then
346-  ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/.libs -L$$r/$(HOST_SUBDIR)/ppl/_libs -lppl_c -lppl -lgmpxx '"$with_host_libstdcxx "
347-  pplinc='-I$$r/$(HOST_SUBDIR)/ppl/include -I$$s/ppl/include '
348-  LIBS="$ppllibs $LIBS"
349+
350+if test x"$with_ppl$with_ppl_include$with_ppl_lib" = x && test -d ${srcdir}/ppl; then
351+  if test x"$enable_watchdog" = xyes; then
352+    pwllib="-lpwl"
353+  fi
354+  ppllibs='-L$$r/$(HOST_SUBDIR)/ppl/interfaces/C/'"$lt_cv_objdir"' -L$$r/$(HOST_SUBDIR)/ppl/src/'"$lt_cv_objdir"
355+  pplinc='-I$$r/$(HOST_SUBDIR)/ppl/src -I$$r/$(HOST_SUBDIR)/ppl/interfaces/C '
356+  enable_ppl_version_check=no
357+  with_ppl=yes
358 fi
359 
360-AC_ARG_ENABLE(ppl-version-check,
361-[  --disable-ppl-version-check    disable check for PPL version],
362-ENABLE_PPL_CHECK=$enableval,
363-ENABLE_PPL_CHECK=yes)
364+if test "x$with_ppl" != xno; then
365+  if test "x$pwllib" = x; then
366+    saved_LDFLAGS="$LDFLAGS"
367+    LDFLAGS="$LDFLAGS $ppllibs"
368+    AC_CHECK_LIB(pwl,PWL_handle_timeout,[pwllib="-lpwl"])
369+    LDFLAGS="$saved_LDFLAGS"
370+  fi
371 
372-if test "${ENABLE_PPL_CHECK}" = "yes"; then
373-  saved_CFLAGS="$CFLAGS"
374-  CFLAGS="$CFLAGS $pplinc $gmpinc"
375-  AC_MSG_CHECKING([for version $ppl_major_version.$ppl_minor_version of PPL])
376-  AC_TRY_COMPILE([#include "ppl_c.h"],[
377-  #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
378-  choke me
379-  #endif
380-  ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ])
381-  CFLAGS="$saved_CFLAGS"
382+  ppllibs="$ppllibs -lppl_c -lppl $pwllib -lgmpxx"
383+
384+  if test "$enable_ppl_version_check" != no; then
385+    saved_CFLAGS="$CFLAGS"
386+    CFLAGS="$CFLAGS $pplinc $gmpinc"
387+    AC_MSG_CHECKING([for version 0.10 (revision 0 or later) of PPL])
388+    AC_TRY_COMPILE([#include "ppl_c.h"],[
389+    #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
390+    choke me
391+    #endif
392+    ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ; with_ppl=no ])
393+    CFLAGS="$saved_CFLAGS"
394+  fi
395 fi
396 
397 # Flags needed for PPL
398@@ -2560,7 +2587,7 @@
399        # to it.  This is right: we don't want to search that directory
400        # for binaries, but we want the header files in there, so add
401        # them explicitly.
402-       FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include'
403+       FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -isystem $$r/$(HOST_SUBDIR)/gcc/include -isystem $$r/$(HOST_SUBDIR)/gcc/include-fixed'
404 
405        # Someone might think of using the pre-installed headers on
406        # Canadian crosses, in case the installed compiler is not fully
407diff -Naur gcc-4.4.6.orig/gcc/ChangeLog.rtems gcc-4.4.6/gcc/ChangeLog.rtems
408--- gcc-4.4.6.orig/gcc/ChangeLog.rtems  1970-01-01 01:00:00.000000000 +0100
409+++ gcc-4.4.6/gcc/ChangeLog.rtems       2011-04-20 17:27:23.061805866 +0200
410@@ -0,0 +1,54 @@
411+2011-02-20     Ralf Corsépius <ralf.corsepius@rtems.org>
412+
413+       * config/rs6000/t-rtems: Remove -mcpu=601 multilib.
414+       * config/rs6000/t-rtems: Remove -Dmpc8260 multilib.
415+
416+2010-03-15     Ralf Corsépius <ralf.corsepius@rtems.org>
417+
418+       Patch from Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>:
419+       * config/arm/rtems-elf.h, config/arm/t-rtems: Add optional support
420+       for vfp FPU model
421+
422+2010-02-10     Ralf Corsépius <ralf.corsepius@rtems.org>
423+
424+       * config/rtems.h: Abandon -qrtems_debug.
425+
426+2009-12-01     Ralf Corsépius <ralf.corsepius@rtems.org>
427+
428+       * config/avr/avr.h (LINK_SPEC): Pass -m avrN to ld for -mmcu=avrN.
429+
430+2009-11-04     Ralf Corsépius <ralf.corsepius@rtems.org>
431+
432+       * config/m32c/rtems.h, config/m68k/rtemself.h,
433+       config/m68k/rtemself.h, config/sh/rtemself.h,
434+       config/sparc/rtemself.h: Undef WCHAR_TYPE_SIZE, WCHAR_TYPE.
435+       (Resets WCHAR_TYPE's to defaults. Prevents broken GCC tm_files
436+       to interfere and cause wchar_t/wint_t incompatibilities).
437+
438+2009-10-15     Ralf Corsépius <ralf.corsepius@rtems.org>
439+
440+       * config/avr/t-rtems: Don't build _exit.
441+
442+               Jon Beniston <jon@beniston.com>
443+
444+       * config/lm32/arithmetic.c, config/lm32/crti.S,
445+       config/lm32/crtn.S, config/lm32/lib1funcs.S,
446+       config/lm32/lm32.c, config/lm32/lm32.h,
447+       config/lm32/lm32.md, config/lm32/lm32.opt,
448+       config/lm32/lm32-protos.h, config/lm32/predicates.md,
449+       config/lm32/rtems.h, config/lm32/sfp-machine.h,
450+       config/lm32/t-fprules-softfp, config/lm32/t-lm32,
451+       config/lm32/uclinux-elf.h: New (lm32 port).
452+       * config.gcc: Add lm32* targets.
453+       * doc/contrib.texi, doc/invoke.texi: Add lm32.
454+
455+               Ralf Corsépius <ralf.corsepius@rtems.org>
456+
457+       * config/rs6000/rtems.h: Support for custom RTEMS multilibs.
458+       Support TARGET_E500.
459+       * config/rs6000/t-rtems: Custom RTEMS multilibs.
460+
461+               Ralf Corsépius <ralf.corsepius@rtems.org>
462+
463+       * config/mips/elf.h: Remove NO_IMPLICIT_EXTERN_C.
464+       
465\ No newline at end of file
466diff -Naur gcc-4.4.6.orig/gcc/config/arm/rtems-elf.h gcc-4.4.6/gcc/config/arm/rtems-elf.h
467--- gcc-4.4.6.orig/gcc/config/arm/rtems-elf.h   2009-03-25 13:54:16.000000000 +0100
468+++ gcc-4.4.6/gcc/config/arm/rtems-elf.h        2011-04-20 17:27:23.061805866 +0200
469@@ -36,7 +36,7 @@
470  */
471 #undef SUBTARGET_EXTRA_ASM_SPEC
472 #define SUBTARGET_EXTRA_ASM_SPEC "\
473-  %{!mhard-float: %{!msoft-float:-mfpu=softfpa}}"
474+  %{!mhard-float: %{!mfpu=vfp: %{!msoft-float:-mfpu=softfpa}}}"
475 
476 /*
477  *  The default includes --start-group and --end-group which conflicts
478diff -Naur gcc-4.4.6.orig/gcc/config/arm/t-rtems gcc-4.4.6/gcc/config/arm/t-rtems
479--- gcc-4.4.6.orig/gcc/config/arm/t-rtems       2004-11-23 06:30:32.000000000 +0100
480+++ gcc-4.4.6/gcc/config/arm/t-rtems    2011-04-20 17:27:23.062805877 +0200
481@@ -5,6 +5,41 @@
482 MULTILIB_EXCEPTIONS  =
483 MULTILIB_MATCHES     = marm=mno-thumb
484 
485-MULTILIB_OPTIONS    += msoft-float/mhard-float
486-MULTILIB_DIRNAMES   += soft fpu
487-MULTILIB_EXCEPTIONS += *mthumb/*mhard-float*
488+MULTILIB_OPTIONS    += mhard-float/mfloat-abi=softfp
489+MULTILIB_DIRNAMES   += fpu softfp
490+MULTILIB_EXCEPTIONS += *mthumb*/*mhard-float* *mthumb*/*mfloat-abi=softfp*
491+MULTILIB_MATCHES     =
492+
493+MULTILIB_OPTIONS    += mfpu=vfp
494+MULTILIB_DIRNAMES   += vfp
495+MULTILIB_EXCEPTIONS += *mhard-float*/*mfpu=vfp* *marm*/*mfloat-abi=softfp*/*mfpu=fpa*
496+MULTILIB_EXCLUSIONS += !mthumb/mfloat-abi=softfp/!mfpu=vfp
497+
498+# default float model is fpa, so don't create a explicit copy of it
499+MULTILIB_EXCEPTIONS += *marm*/*mfpa*
500+
501+# permutations of the options which are useful (+) or make no sense (-),
502+# defaults are in brackets:
503+# + (arm/soft/fpa)
504+# + (arm/soft)/vfp
505+# - (arm)/softfp(/fpa)
506+# + (arm)/softfp/vfp
507+# + (arm)/hard-float(/fpa)
508+# - (arm)/hard-float/vfp
509+# + thumb/(soft/fpa)
510+# + thumb/(soft/)vfp
511+# - thumb/softfp/fpa
512+# - thumb/softfp/vfp
513+# - thumb/hard-float/fpa
514+# - thumb/hard-float/vfp
515+
516+# subdirs to be used for multilibs and their respective options:
517+#/thumb/vfp  -> thumb/soft/vfp
518+#/thumb/fpa  -> thumb/soft/fpa
519+#/thumb      -> thumb/soft/fpa
520+#/vfp        -> arm/soft/vfp
521+#/softfp/vfp -> arm/softfp/cfp
522+#/fpu/fpa    -> arm/hard/fpa
523+#/fpu        -> arm/hard/fpa
524+#/fpa        -> arm/soft/fpa
525+#.           -> arm/soft/fpa
526diff -Naur gcc-4.4.6.orig/gcc/config/avr/avr.h gcc-4.4.6/gcc/config/avr/avr.h
527--- gcc-4.4.6.orig/gcc/config/avr/avr.h 2009-03-28 22:09:50.000000000 +0100
528+++ gcc-4.4.6/gcc/config/avr/avr.h      2011-04-20 17:27:23.062805877 +0200
529@@ -811,12 +811,15 @@
530                                mmcu=at90can64*|\
531                                mmcu=at90usb64*:--pmem-wrap-around=64k}}}\
532 %{!mmcu*: -m avr2}\
533-%{mmcu=at90s1200|\
534+%{mmcu=avr1|\
535+  mmcu=at90s1200|\
536   mmcu=attiny11|\
537   mmcu=attiny12|\
538   mmcu=attiny15|\
539   mmcu=attiny28: -m avr1}\
540-%{mmcu=attiny22|\
541+%{mmcu=avr2|\
542+  mmcu=avr25|\
543+  mmcu=attiny22|\
544   mmcu=attiny26|\
545   mmcu=at90s2*|\
546   mmcu=at90s4*|\
547@@ -831,14 +834,18 @@
548   mmcu=attiny261|\
549   mmcu=attiny4*|\
550   mmcu=attiny8*: -m avr2}\
551-%{mmcu=atmega103|\
552+%{mmcu=avr3|\
553+  mmcu=avr31|\
554+  mmcu=avr35|\
555+  mmcu=atmega103|\
556   mmcu=at43*|\
557   mmcu=at76*|\
558   mmcu=at90usb82|\
559   mmcu=at90usb162|\
560   mmcu=attiny16*|\
561   mmcu=attiny32*: -m avr3}\
562-%{mmcu=atmega8*|\
563+%{mmcu=avr4|\
564+  mmcu=atmega8*|\
565   mmcu=atmega4*|\
566   mmcu=at90pwm1|\
567   mmcu=at90pwm2|\
568@@ -846,7 +853,9 @@
569   mmcu=at90pwm3|\
570   mmcu=at90pwm3b|\
571   mmcu=at90pwm81: -m avr4}\
572-%{mmcu=atmega16*|\
573+%{mmcu=avr5|\
574+  mmcu=avr51|\
575+  mmcu=atmega16*|\
576   mmcu=atmega32*|\
577   mmcu=atmega406|\
578   mmcu=atmega64*|\
579@@ -860,7 +869,8 @@
580   mmcu=at94k|\
581   mmcu=m3000*|\
582   mmcu=m3001*: -m avr5}\
583-%{mmcu=atmega256*:-m avr6}\
584+%{mmcu=avr6|\
585+  mmcu=atmega256*:-m avr6}\
586 %{mmcu=atmega324*|\
587   mmcu=atmega325*|\
588   mmcu=atmega328p|\
589diff -Naur gcc-4.4.6.orig/gcc/config/avr/t-rtems gcc-4.4.6/gcc/config/avr/t-rtems
590--- gcc-4.4.6.orig/gcc/config/avr/t-rtems       2004-11-23 04:44:03.000000000 +0100
591+++ gcc-4.4.6/gcc/config/avr/t-rtems    2011-04-20 17:27:23.062805877 +0200
592@@ -1,3 +1,4 @@
593 # Multilibs for avr RTEMS targets.
594 
595-# ATM, this is just a stub
596+# RTEMS uses _exit from newlib
597+LIB1ASMFUNCS := $(filter-out _exit,$(LIB1ASMFUNCS))
598diff -Naur gcc-4.4.6.orig/gcc/config/lm32/arithmetic.c gcc-4.4.6/gcc/config/lm32/arithmetic.c
599--- gcc-4.4.6.orig/gcc/config/lm32/arithmetic.c 1970-01-01 01:00:00.000000000 +0100
600+++ gcc-4.4.6/gcc/config/lm32/arithmetic.c      2011-04-20 17:27:23.062805877 +0200
601@@ -0,0 +1,305 @@
602+/* Fixed-point arithmetic for Lattice Mico32.
603+   Contributed by Jon Beniston <jon@beniston.com>
604+   
605+   Copyright (C) 2008 Free Software Foundation, Inc.
606+
607+   This file is free software; you can redistribute it and/or modify it
608+   under the terms of the GNU General Public License as published by the
609+   Free Software Foundation; either version 2, or (at your option) any
610+   later version.
611+
612+   In addition to the permissions in the GNU General Public License, the
613+   Free Software Foundation gives you unlimited permission to link the
614+   compiled version of this file into combinations with other programs,
615+   and to distribute those combinations without any restriction coming
616+   from the use of this file.  (The General Public License restrictions
617+   do apply in other respects; for example, they cover modification of
618+   the file, and distribution when not linked into a combine
619+   executable.)
620+
621+   This file is distributed in the hope that it will be useful, but
622+   WITHOUT ANY WARRANTY; without even the implied warranty of
623+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
624+   General Public License for more details.
625+
626+   You should have received a copy of the GNU General Public License
627+   along with this program; see the file COPYING.  If not, write to
628+   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
629+   Boston, MA 02110-1301, USA.  */
630+
631+typedef unsigned long UQItype __attribute__ ((mode (QI)));
632+typedef        long SItype __attribute__ ((mode (SI)));
633+typedef unsigned long USItype __attribute__ ((mode (SI)));
634+
635+/* Prototypes */
636+
637+USItype __mulsi3 (USItype a, USItype b);
638+
639+USItype __udivmodsi4 (USItype num, USItype den, int modwanted);
640+SItype __divsi3 (SItype a, SItype b);
641+SItype __modsi3 (SItype a, SItype b);
642+USItype __udivsi3 (USItype a, USItype b);
643+USItype __umodsi3 (USItype a, USItype b);
644+
645+SItype __ashlsi3 (SItype a, SItype b);
646+SItype __ashrsi3 (SItype a, SItype b);
647+USItype __lshrsi3 (USItype a, USItype b);
648+
649+/* Multiplication */
650+
651+#ifdef L_mulsi3
652+USItype
653+__mulsi3 (USItype a, USItype b)
654+{
655+  USItype result;
656+   
657+  result = 0;
658+
659+  if (a==0)
660+    return 0;
661+
662+  while (b!=0)
663+    {
664+      if (b & 1)
665+        result += a;
666+      a <<= 1;
667+      b >>= 1;
668+    }
669+       
670+  return result;   
671+}
672+#endif
673+
674+/* Division */
675+
676+#ifdef L_udivmodsi4
677+USItype
678+__udivmodsi4 (USItype num, USItype den, int modwanted)
679+{
680+  USItype bit = 1;
681+  USItype res = 0;
682+
683+  while (den < num && bit && !(den & (1L<<31)))
684+    {
685+      den <<=1;
686+      bit <<=1;
687+    }
688+  while (bit)
689+    {
690+      if (num >= den)
691+       {
692+         num -= den;
693+         res |= bit;
694+       }
695+      bit >>=1;
696+      den >>=1;
697+    }
698+  if (modwanted)
699+    return num;
700+  return res;
701+}
702+#endif
703+
704+#ifdef L_divsi3
705+
706+static const UQItype __divsi3_table[] = {
707+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
708+  0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
709+  0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
710+  0, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
711+  0, 4, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
712+  0, 5, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
713+  0, 6, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
714+  0, 7, 3, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
715+  0, 8, 4, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
716+  0, 9, 4, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
717+  0, 10, 5, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
718+  0, 11, 5, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
719+  0, 12, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0,
720+  0, 13, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
721+  0, 14, 7, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0,
722+  0, 15, 7, 5, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
723+};
724+
725+SItype
726+__divsi3 (SItype a, SItype b)
727+{
728+  int neg = 0;
729+  SItype res;
730+  int cfg;
731+
732+  if (b == 0)
733+    {
734+      /* Raise divide by zero exception */
735+      int eba;
736+      __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba));
737+      eba += 32 * 5;
738+      __asm__ __volatile__ ("mv ea, ra");
739+      __asm__ __volatile__ ("b %0" : : "r" (eba));
740+    }
741+
742+  if (((USItype)(a | b)) < 16)
743+    {
744+      res = __divsi3_table[(a << 4) + b];
745+    }
746+  else
747+    {
748+
749+      if (a < 0)
750+        {
751+          a = -a;
752+          neg = !neg;
753+        }
754+   
755+      if (b < 0)
756+        {
757+          b = -b;
758+          neg = !neg;
759+        }
760+   
761+      __asm__ ("rcsr %0, CFG" : "=r" (cfg));
762+      if (cfg & 2)
763+        __asm__ ("divu %0, %1, %2" : "=r" (res) : "r" (a), "r" (b));
764+      else
765+        res = __udivmodsi4 (a, b, 0);
766+   
767+      if (neg)
768+        res = -res;
769+    }
770+
771+  return res;
772+}
773+#endif
774+
775+#ifdef L_modsi3
776+SItype
777+__modsi3 (SItype a, SItype b)
778+{
779+  int neg = 0;
780+  SItype res;
781+  int cfg;
782
783+  if (b == 0)
784+    {
785+      /* Raise divide by zero exception */
786+      int eba, sr;
787+      /* Save interrupt enable */
788+      __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr));
789+      sr = (sr & 1) << 1;
790+      __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr));
791+      /* Branch to exception handler */
792+      __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba));
793+      eba += 32 * 5;
794+      __asm__ __volatile__ ("mv ea, ra");
795+      __asm__ __volatile__ ("b %0" : : "r" (eba));
796+    }
797
798+  if (a < 0)
799+    {
800+      a = -a;
801+      neg = 1;
802+    }
803+
804+  if (b < 0)
805+    b = -b;
806+
807+  __asm__ ("rcsr %0, CFG" : "=r" (cfg));
808+  if (cfg & 2)
809+    __asm__ ("modu %0, %1, %2" : "=r" (res) : "r" (a), "r" (b));
810+  else
811+    res = __udivmodsi4 (a, b, 1);
812+
813+  if (neg)
814+    res = -res;
815+
816+  return res;
817+}
818+#endif
819+
820+#ifdef L_udivsi3
821+USItype
822+__udivsi3 (USItype a, USItype b)
823+{
824+  if (b == 0)
825+    {
826+      /* Raise divide by zero exception */
827+      int eba, sr;
828+      /* Save interrupt enable */
829+      __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr));
830+      sr = (sr & 1) << 1;
831+      __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr));
832+      /* Branch to exception handler */
833+      __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba));
834+      eba += 32 * 5;
835+      __asm__ __volatile__ ("mv ea, ra");
836+      __asm__ __volatile__ ("b %0" : : "r" (eba));
837+    }
838
839+  return __udivmodsi4 (a, b, 0);
840+}
841+#endif
842+
843+#ifdef L_umodsi3
844+USItype
845+__umodsi3 (USItype a, USItype b)
846+{
847+  if (b == 0)
848+    {
849+      /* Raise divide by zero exception */
850+      int eba, sr;
851+      /* Save interrupt enable */
852+      __asm__ __volatile__ ("rcsr %0, IE" : "=r" (sr));
853+      sr = (sr & 1) << 1;
854+      __asm__ __volatile__ ("wcsr IE, %0" : : "r" (sr));
855+      /* Branch to exception handler */
856+      __asm__ __volatile__ ("rcsr %0, EBA" : "=r" (eba));
857+      eba += 32 * 5;
858+      __asm__ __volatile__ ("mv ea, ra");
859+      __asm__ __volatile__ ("b %0" : : "r" (eba));
860+    }
861
862+  return __udivmodsi4 (a, b, 1);
863+}
864+#endif
865+
866+#if 0
867+
868+/* Shifts - Optimized versions implemented in assembly. Use these if code space is preferred to performance.  */
869+
870+#ifdef L_ashlsi3
871+SItype
872+__ashlsi3 (SItype a, SItype b)
873+{
874+  int i;
875
876+  for (i = (b & 0x1f); i > 0; --i)
877+    a += a;
878+  return a;
879+}
880+#endif
881+
882+#ifdef L_ashrsi3
883+SItype
884+__ashrsi3 (SItype a, SItype b)
885+{
886+  int i;
887
888+  for (i = (b & 0x1f); i > 0; --i)
889+    __asm__ ("sri      %0, %0, 1" : "=r" (a) : "0" (a));
890+  return a;
891+}
892+#endif
893+
894+#ifdef L_lshrsi3
895+USItype
896+__lshrsi3 (USItype a, USItype b)
897+{
898+  int i;
899
900+  for (i = (b & 0x1f); i > 0; --i)
901+    __asm__ ("srui     %0, %0, 1" : "=r" (a) : "0" (a));
902+  return a;
903+}
904+#endif
905+
906+#endif
907diff -Naur gcc-4.4.6.orig/gcc/config/lm32/crti.S gcc-4.4.6/gcc/config/lm32/crti.S
908--- gcc-4.4.6.orig/gcc/config/lm32/crti.S       1970-01-01 01:00:00.000000000 +0100
909+++ gcc-4.4.6/gcc/config/lm32/crti.S    2011-04-20 17:27:23.062805877 +0200
910@@ -0,0 +1,45 @@
911+# crti.S for Lattice Mico32
912+# Contributed by Jon Beniston <jon@beniston.com>
913+#
914+# Copyright (C) 2008 Free Software Foundation, Inc.
915+#
916+# This file is free software; you can redistribute it and/or modify it
917+# under the terms of the GNU General Public License as published by the
918+# Free Software Foundation; either version 2, or (at your option) any
919+# later version.
920+#
921+# In addition to the permissions in the GNU General Public License, the
922+# Free Software Foundation gives you unlimited permission to link the
923+# compiled version of this file into combinations with other programs,
924+# and to distribute those combinations without any restriction coming
925+# from the use of this file.  (The General Public License restrictions
926+# do apply in other respects; for example, they cover modification of
927+# the file, and distribution when not linked into a combine
928+# executable.)
929+#
930+# This file is distributed in the hope that it will be useful, but
931+# WITHOUT ANY WARRANTY; without even the implied warranty of
932+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
933+# General Public License for more details.
934+#
935+# You should have received a copy of the GNU General Public License
936+# along with this program; see the file COPYING.  If not, write to
937+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
938+# Boston, MA 02110-1301, USA. 
939+#
940+
941+        .section .init
942+        .global _init
943+        .type _init,@function
944+        .align 4
945+_init:
946+        addi    sp, sp, -4       
947+        sw      (sp+4), ra
948+
949+        .section .fini
950+        .global _fini
951+        .type _fini,@function
952+        .align 4
953+_fini:       
954+        addi    sp, sp, -4       
955+        sw      (sp+4), ra
956diff -Naur gcc-4.4.6.orig/gcc/config/lm32/crtn.S gcc-4.4.6/gcc/config/lm32/crtn.S
957--- gcc-4.4.6.orig/gcc/config/lm32/crtn.S       1970-01-01 01:00:00.000000000 +0100
958+++ gcc-4.4.6/gcc/config/lm32/crtn.S    2011-04-20 17:27:23.063805887 +0200
959@@ -0,0 +1,42 @@
960+# crtn.S for Lattice Mico32
961+# Contributed by Jon Beniston <jon@beniston.com>
962+#
963+# Copyright (C) 2008 Free Software Foundation, Inc.
964+#
965+# This file is free software; you can redistribute it and/or modify it
966+# under the terms of the GNU General Public License as published by the
967+# Free Software Foundation; either version 2, or (at your option) any
968+# later version.
969+#
970+# In addition to the permissions in the GNU General Public License, the
971+# Free Software Foundation gives you unlimited permission to link the
972+# compiled version of this file into combinations with other programs,
973+# and to distribute those combinations without any restriction coming
974+# from the use of this file.  (The General Public License restrictions
975+# do apply in other respects; for example, they cover modification of
976+# the file, and distribution when not linked into a combine
977+# executable.)
978+#
979+# This file is distributed in the hope that it will be useful, but
980+# WITHOUT ANY WARRANTY; without even the implied warranty of
981+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
982+# General Public License for more details.
983+#
984+# You should have received a copy of the GNU General Public License
985+# along with this program; see the file COPYING.  If not, write to
986+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
987+# Boston, MA 02110-1301, USA. 
988+#
989+
990+        .section .init
991+       
992+        lw      ra, (sp+4)
993+        addi    sp, sp, 4
994+        ret
995+               
996+        .section .fini
997+       
998+        lw      ra, (sp+4)
999+        addi    sp, sp, 4
1000+        ret
1001+       
1002diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lib1funcs.S gcc-4.4.6/gcc/config/lm32/lib1funcs.S
1003--- gcc-4.4.6.orig/gcc/config/lm32/lib1funcs.S  1970-01-01 01:00:00.000000000 +0100
1004+++ gcc-4.4.6/gcc/config/lm32/lib1funcs.S       2011-04-20 17:27:23.063805887 +0200
1005@@ -0,0 +1,429 @@
1006+# lib1funcs.S for Lattice Mico32
1007+# Contributed by Jon Beniston <jon@beniston.com>
1008+#
1009+# Copyright (C) 2008 Free Software Foundation, Inc.
1010+#
1011+# This file is free software; you can redistribute it and/or modify it
1012+# under the terms of the GNU General Public License as published by the
1013+# Free Software Foundation; either version 2, or (at your option) any
1014+# later version.
1015+#
1016+# In addition to the permissions in the GNU General Public License, the
1017+# Free Software Foundation gives you unlimited permission to link the
1018+# compiled version of this file into combinations with other programs,
1019+# and to distribute those combinations without any restriction coming
1020+# from the use of this file.  (The General Public License restrictions
1021+# do apply in other respects; for example, they cover modification of
1022+# the file, and distribution when not linked into a combine
1023+# executable.)
1024+#
1025+# This file is distributed in the hope that it will be useful, but
1026+# WITHOUT ANY WARRANTY; without even the implied warranty of
1027+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
1028+# General Public License for more details.
1029+#
1030+# You should have received a copy of the GNU General Public License
1031+# along with this program; see the file COPYING.  If not, write to
1032+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
1033+# Boston, MA 02110-1301, USA. 
1034+#
1035+
1036+/* Arithmetic left shift */
1037+       
1038+        .text
1039+
1040+        .global __ashlsi3
1041+        .type __ashlsi3,@function
1042+        .align 4
1043+       
1044+__ashlsi3:
1045+        /* Only use 5 LSBs, as that's all the h/w shifter uses */
1046+        andi    r2, r2, 0x1f
1047+        /* Get address of offset into unrolled shift loop to jump to */
1048+#ifdef __PIC__
1049+        orhi    r3, r0, gotoffhi16(__ashlsi3_table)
1050+        addi    r3, r3, gotofflo16(__ashlsi3_table)
1051+        add     r3, r3, gp
1052+#else
1053+        mvhi    r3, hi(__ashlsi3_table)
1054+        ori     r3, r3, lo(__ashlsi3_table)
1055+#endif
1056+        add     r2, r2, r2
1057+        add     r2, r2, r2
1058+        add     r3, r3, r2
1059+        lw      r3, (r3+0)
1060+        b       r3       
1061+       
1062+__ashlsi3_31:
1063+        add     r1, r1, r1
1064+__ashlsi3_30:
1065+        add     r1, r1, r1
1066+__ashlsi3_29:
1067+        add     r1, r1, r1
1068+__ashlsi3_28:
1069+        add     r1, r1, r1
1070+__ashlsi3_27:
1071+        add     r1, r1, r1
1072+__ashlsi3_26:
1073+        add     r1, r1, r1
1074+__ashlsi3_25:
1075+        add     r1, r1, r1
1076+__ashlsi3_24:
1077+        add     r1, r1, r1
1078+__ashlsi3_23:
1079+        add     r1, r1, r1
1080+__ashlsi3_22:
1081+        add     r1, r1, r1
1082+__ashlsi3_21:
1083+        add     r1, r1, r1
1084+__ashlsi3_20:
1085+        add     r1, r1, r1
1086+__ashlsi3_19:
1087+        add     r1, r1, r1
1088+__ashlsi3_18:
1089+        add     r1, r1, r1
1090+__ashlsi3_17:
1091+        add     r1, r1, r1
1092+__ashlsi3_16:
1093+        add     r1, r1, r1
1094+__ashlsi3_15:
1095+        add     r1, r1, r1
1096+__ashlsi3_14:
1097+        add     r1, r1, r1
1098+__ashlsi3_13:
1099+        add     r1, r1, r1
1100+__ashlsi3_12:
1101+        add     r1, r1, r1
1102+__ashlsi3_11:
1103+        add     r1, r1, r1
1104+__ashlsi3_10:
1105+        add     r1, r1, r1
1106+__ashlsi3_9:
1107+        add     r1, r1, r1
1108+__ashlsi3_8:
1109+        add     r1, r1, r1
1110+__ashlsi3_7:
1111+        add     r1, r1, r1
1112+__ashlsi3_6:
1113+        add     r1, r1, r1
1114+__ashlsi3_5:
1115+        add     r1, r1, r1
1116+__ashlsi3_4:
1117+        add     r1, r1, r1
1118+__ashlsi3_3:
1119+        add     r1, r1, r1
1120+__ashlsi3_2:
1121+        add     r1, r1, r1
1122+__ashlsi3_1:
1123+        add     r1, r1, r1
1124+__ashlsi3_0:
1125+        ret
1126+       
1127+#ifdef __PIC__
1128+        .section .data
1129+#else
1130+        .section .rodata
1131+#endif       
1132+
1133+        .align 4
1134+
1135+__ashlsi3_table:
1136+        .word   __ashlsi3_0
1137+        .word   __ashlsi3_1
1138+        .word   __ashlsi3_2
1139+        .word   __ashlsi3_3
1140+        .word   __ashlsi3_4
1141+        .word   __ashlsi3_5
1142+        .word   __ashlsi3_6
1143+        .word   __ashlsi3_7
1144+        .word   __ashlsi3_8
1145+        .word   __ashlsi3_9
1146+        .word   __ashlsi3_10
1147+        .word   __ashlsi3_11
1148+        .word   __ashlsi3_12
1149+        .word   __ashlsi3_13
1150+        .word   __ashlsi3_14
1151+        .word   __ashlsi3_15
1152+        .word   __ashlsi3_16
1153+        .word   __ashlsi3_17
1154+        .word   __ashlsi3_18
1155+        .word   __ashlsi3_19
1156+        .word   __ashlsi3_20
1157+        .word   __ashlsi3_21
1158+        .word   __ashlsi3_22
1159+        .word   __ashlsi3_23
1160+        .word   __ashlsi3_24
1161+        .word   __ashlsi3_25
1162+        .word   __ashlsi3_26
1163+        .word   __ashlsi3_27
1164+        .word   __ashlsi3_28
1165+        .word   __ashlsi3_29
1166+        .word   __ashlsi3_30
1167+        .word   __ashlsi3_31
1168+       
1169+/* Logical right shift */
1170+       
1171+        .text
1172+       
1173+        .global __lshrsi3
1174+        .type __lshrsi3,@function
1175+        .align 4
1176+       
1177+__lshrsi3:
1178+        /* Only use 5 LSBs, as that's all the h/w shifter uses */
1179+        andi    r2, r2, 0x1f
1180+        /* Get address of offset into unrolled shift loop to jump to */
1181+#ifdef __PIC__
1182+        orhi    r3, r0, gotoffhi16(__lshrsi3_table)       
1183+        addi    r3, r3, gotofflo16(__lshrsi3_table)
1184+        add     r3, r3, gp
1185+#else
1186+        mvhi    r3, hi(__lshrsi3_table)
1187+        ori     r3, r3, lo(__lshrsi3_table)
1188+#endif
1189+        add     r2, r2, r2
1190+        add     r2, r2, r2
1191+        add     r3, r3, r2
1192+        lw      r3, (r3+0)
1193+        b       r3       
1194+       
1195+__lshrsi3_31:       
1196+        srui    r1, r1, 1
1197+__lshrsi3_30:       
1198+        srui    r1, r1, 1
1199+__lshrsi3_29:       
1200+        srui    r1, r1, 1
1201+__lshrsi3_28:       
1202+        srui    r1, r1, 1
1203+__lshrsi3_27:       
1204+        srui    r1, r1, 1
1205+__lshrsi3_26:       
1206+        srui    r1, r1, 1
1207+__lshrsi3_25:       
1208+        srui    r1, r1, 1
1209+__lshrsi3_24:       
1210+        srui    r1, r1, 1
1211+__lshrsi3_23:       
1212+        srui    r1, r1, 1
1213+__lshrsi3_22:       
1214+        srui    r1, r1, 1
1215+__lshrsi3_21:       
1216+        srui    r1, r1, 1
1217+__lshrsi3_20:       
1218+        srui    r1, r1, 1
1219+__lshrsi3_19:       
1220+        srui    r1, r1, 1
1221+__lshrsi3_18:       
1222+        srui    r1, r1, 1
1223+__lshrsi3_17:       
1224+        srui    r1, r1, 1
1225+__lshrsi3_16:       
1226+        srui    r1, r1, 1
1227+__lshrsi3_15:       
1228+        srui    r1, r1, 1
1229+__lshrsi3_14:       
1230+        srui    r1, r1, 1
1231+__lshrsi3_13:       
1232+        srui    r1, r1, 1
1233+__lshrsi3_12:       
1234+        srui    r1, r1, 1
1235+__lshrsi3_11:       
1236+        srui    r1, r1, 1
1237+__lshrsi3_10:       
1238+        srui    r1, r1, 1
1239+__lshrsi3_9:       
1240+        srui    r1, r1, 1
1241+__lshrsi3_8:       
1242+        srui    r1, r1, 1
1243+__lshrsi3_7:       
1244+        srui    r1, r1, 1
1245+__lshrsi3_6:       
1246+        srui    r1, r1, 1
1247+__lshrsi3_5:       
1248+        srui    r1, r1, 1
1249+__lshrsi3_4:       
1250+        srui    r1, r1, 1
1251+__lshrsi3_3:       
1252+        srui    r1, r1, 1
1253+__lshrsi3_2:       
1254+        srui    r1, r1, 1
1255+__lshrsi3_1:       
1256+        srui    r1, r1, 1
1257+__lshrsi3_0:       
1258+        ret
1259+       
1260+#ifdef __PIC__
1261+        .section .data
1262+#else
1263+        .section .rodata
1264+#endif       
1265+
1266+        .align 4
1267+
1268+__lshrsi3_table:       
1269+        .word   __lshrsi3_0       
1270+        .word   __lshrsi3_1       
1271+        .word   __lshrsi3_2       
1272+        .word   __lshrsi3_3       
1273+        .word   __lshrsi3_4       
1274+        .word   __lshrsi3_5       
1275+        .word   __lshrsi3_6       
1276+        .word   __lshrsi3_7       
1277+        .word   __lshrsi3_8       
1278+        .word   __lshrsi3_9       
1279+        .word   __lshrsi3_10       
1280+        .word   __lshrsi3_11       
1281+        .word   __lshrsi3_12       
1282+        .word   __lshrsi3_13       
1283+        .word   __lshrsi3_14       
1284+        .word   __lshrsi3_15       
1285+        .word   __lshrsi3_16       
1286+        .word   __lshrsi3_17       
1287+        .word   __lshrsi3_18       
1288+        .word   __lshrsi3_19       
1289+        .word   __lshrsi3_20       
1290+        .word   __lshrsi3_21       
1291+        .word   __lshrsi3_22       
1292+        .word   __lshrsi3_23       
1293+        .word   __lshrsi3_24       
1294+        .word   __lshrsi3_25       
1295+        .word   __lshrsi3_26       
1296+        .word   __lshrsi3_27       
1297+        .word   __lshrsi3_28
1298+        .word   __lshrsi3_29       
1299+        .word   __lshrsi3_30       
1300+        .word   __lshrsi3_31       
1301+       
1302+/* Arithmetic right shift */
1303+
1304+        .text
1305+       
1306+        .global __ashrsi3
1307+        .type __ashrsi3,@function
1308+        .align 4
1309+       
1310+__ashrsi3:
1311+        /* Only use 5 LSBs, as that's all the h/w shifter uses */
1312+        andi    r2, r2, 0x1f
1313+        /* Get address of offset into unrolled shift loop to jump to */
1314+#ifdef __PIC__
1315+        orhi    r3, r0, gotoffhi16(__ashrsi3_table)
1316+        addi    r3, r3, gotofflo16(__ashrsi3_table)
1317+        add     r3, r3, gp
1318+#else
1319+        mvhi    r3, hi(__ashrsi3_table)
1320+        ori     r3, r3, lo(__ashrsi3_table)
1321+#endif
1322+        add     r2, r2, r2
1323+        add     r2, r2, r2
1324+        add     r3, r3, r2
1325+        lw      r3, (r3+0)
1326+        b       r3       
1327+       
1328+__ashrsi3_31:
1329+        sri     r1, r1, 1
1330+__ashrsi3_30:
1331+        sri     r1, r1, 1
1332+__ashrsi3_29:
1333+        sri     r1, r1, 1
1334+__ashrsi3_28:
1335+        sri     r1, r1, 1
1336+__ashrsi3_27:
1337+        sri     r1, r1, 1
1338+__ashrsi3_26:
1339+        sri     r1, r1, 1
1340+__ashrsi3_25:
1341+        sri     r1, r1, 1
1342+__ashrsi3_24:
1343+        sri     r1, r1, 1
1344+__ashrsi3_23:
1345+        sri     r1, r1, 1
1346+__ashrsi3_22:
1347+        sri     r1, r1, 1
1348+__ashrsi3_21:
1349+        sri     r1, r1, 1
1350+__ashrsi3_20:
1351+        sri     r1, r1, 1
1352+__ashrsi3_19:
1353+        sri     r1, r1, 1
1354+__ashrsi3_18:
1355+        sri     r1, r1, 1
1356+__ashrsi3_17:
1357+        sri     r1, r1, 1
1358+__ashrsi3_16:
1359+        sri     r1, r1, 1
1360+__ashrsi3_15:
1361+        sri     r1, r1, 1
1362+__ashrsi3_14:
1363+        sri     r1, r1, 1
1364+__ashrsi3_13:
1365+        sri     r1, r1, 1
1366+__ashrsi3_12:
1367+        sri     r1, r1, 1
1368+__ashrsi3_11:
1369+        sri     r1, r1, 1
1370+__ashrsi3_10:
1371+        sri     r1, r1, 1
1372+__ashrsi3_9:
1373+        sri     r1, r1, 1
1374+__ashrsi3_8:
1375+        sri     r1, r1, 1
1376+__ashrsi3_7:
1377+        sri     r1, r1, 1
1378+__ashrsi3_6:
1379+        sri     r1, r1, 1
1380+__ashrsi3_5:
1381+        sri     r1, r1, 1
1382+__ashrsi3_4:
1383+        sri     r1, r1, 1
1384+__ashrsi3_3:
1385+        sri     r1, r1, 1
1386+__ashrsi3_2:
1387+        sri     r1, r1, 1
1388+__ashrsi3_1:
1389+        sri     r1, r1, 1
1390+__ashrsi3_0:
1391+        ret
1392+       
1393+#ifdef __PIC__
1394+        .section .data
1395+#else
1396+        .section .rodata
1397+#endif       
1398+
1399+        .align 4
1400+
1401+__ashrsi3_table:
1402+        .word   __ashrsi3_0
1403+        .word   __ashrsi3_1
1404+        .word   __ashrsi3_2
1405+        .word   __ashrsi3_3
1406+        .word   __ashrsi3_4
1407+        .word   __ashrsi3_5
1408+        .word   __ashrsi3_6
1409+        .word   __ashrsi3_7
1410+        .word   __ashrsi3_8
1411+        .word   __ashrsi3_9
1412+        .word   __ashrsi3_10
1413+        .word   __ashrsi3_11
1414+        .word   __ashrsi3_12
1415+        .word   __ashrsi3_13
1416+        .word   __ashrsi3_14
1417+        .word   __ashrsi3_15
1418+        .word   __ashrsi3_16
1419+        .word   __ashrsi3_17
1420+        .word   __ashrsi3_18
1421+        .word   __ashrsi3_19
1422+        .word   __ashrsi3_20
1423+        .word   __ashrsi3_21
1424+        .word   __ashrsi3_22
1425+        .word   __ashrsi3_23
1426+        .word   __ashrsi3_24
1427+        .word   __ashrsi3_25
1428+        .word   __ashrsi3_26
1429+        .word   __ashrsi3_27
1430+        .word   __ashrsi3_28
1431+        .word   __ashrsi3_29
1432+        .word   __ashrsi3_30
1433+        .word   __ashrsi3_31
1434+       
1435diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.c gcc-4.4.6/gcc/config/lm32/lm32.c
1436--- gcc-4.4.6.orig/gcc/config/lm32/lm32.c       1970-01-01 01:00:00.000000000 +0100
1437+++ gcc-4.4.6/gcc/config/lm32/lm32.c    2011-04-20 17:27:23.063805887 +0200
1438@@ -0,0 +1,869 @@
1439+/* Subroutines used for code generation on the Lattice Mico32 architecture.
1440+   Contributed by Jon Beniston <jon@beniston.com>
1441+
1442+   Copyright (C) 2008 Free Software Foundation, Inc.
1443+
1444+   This file is part of GCC.
1445+
1446+   GCC is free software; you can redistribute it and/or modify it
1447+   under the terms of the GNU General Public License as published
1448+   by the Free Software Foundation; either version 3, or (at your
1449+   option) any later version.
1450+
1451+   GCC is distributed in the hope that it will be useful, but WITHOUT
1452+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1453+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
1454+   License for more details.
1455+
1456+   You should have received a copy of the GNU General Public License
1457+   along with GCC; see the file COPYING3.  If not see
1458+   <http://www.gnu.org/licenses/>.  */
1459+
1460+#include "config.h"
1461+#include "system.h"
1462+#include "coretypes.h"
1463+#include "tm.h"
1464+#include "rtl.h"
1465+#include "regs.h"
1466+#include "hard-reg-set.h"
1467+#include "basic-block.h"
1468+#include "real.h"
1469+#include "insn-config.h"
1470+#include "conditions.h"
1471+#include "insn-flags.h"
1472+#include "insn-attr.h"
1473+#include "insn-codes.h"
1474+#include "recog.h"
1475+#include "output.h"
1476+#include "tree.h"
1477+#include "expr.h"
1478+#include "flags.h"
1479+#include "reload.h"
1480+#include "tm_p.h"
1481+#include "function.h"
1482+#include "toplev.h"
1483+#include "optabs.h"
1484+#include "libfuncs.h"
1485+#include "ggc.h"
1486+#include "target.h"
1487+#include "target-def.h"
1488+#include "langhooks.h"
1489+#include "tm-constrs.h"
1490+#include "df.h"
1491+
1492+struct lm32_frame_info
1493+{
1494+  HOST_WIDE_INT total_size;      /* number of bytes that the entire frame takes up.  */
1495+  HOST_WIDE_INT callee_size;     /* number of bytes to save callee save registers  */
1496+  HOST_WIDE_INT pretend_size;    /* number of bytes we push and pretend caller did.  */
1497+  HOST_WIDE_INT args_size;       /* number of bytes that outgoing arguments take up.  */
1498+  HOST_WIDE_INT locals_size;     /* number of bytes that local variables take up.  */
1499+  unsigned int reg_save_mask;   /* mask of saved registers.  */
1500+};
1501+
1502+/* Prototypes for static functions */
1503+static rtx emit_add (rtx dest, rtx src0, rtx src1);
1504+static void expand_save_restore (struct lm32_frame_info *info, int op);
1505+static void abort_with_insn (rtx insn, const char *reason);
1506+static void stack_adjust (HOST_WIDE_INT amount);
1507+static bool lm32_in_small_data_p (const_tree);
1508+static void lm32_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1509+                             tree type, int *pretend_size, int no_rtl);
1510+
1511+/* Detemines if given constant can be used as a displacement */
1512+#define OFFSET_INT(X)  (((X) > -32768) && ((X) < 32768))
1513+
1514+#undef TARGET_ADDRESS_COST
1515+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1516+#undef TARGET_IN_SMALL_DATA_P
1517+#define TARGET_IN_SMALL_DATA_P lm32_in_small_data_p
1518+#undef TARGET_PROMOTE_FUNCTION_ARGS
1519+#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1520+#undef TARGET_PROMOTE_FUNCTION_RETURN
1521+#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1522+#undef TARGET_SETUP_INCOMING_VARARGS
1523+#define TARGET_SETUP_INCOMING_VARARGS lm32_setup_incoming_varargs
1524+#undef TARGET_PROMOTE_PROTOTYPES
1525+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
1526+
1527+struct gcc_target targetm = TARGET_INITIALIZER;
1528+
1529+/* Current frame information calculated by lm32_compute_frame_size.  */
1530+static struct lm32_frame_info current_frame_info;
1531+
1532+rtx lm32_compare_op0;
1533+rtx lm32_compare_op1;
1534+
1535+/* Return non-zero if the specified return type should be returned in memory */
1536+int
1537+lm32_return_in_memory (tree type)
1538+{
1539+  HOST_WIDE_INT size;
1540+
1541+  if (!AGGREGATE_TYPE_P (type))
1542+    {
1543+      /* All simple types are returned in registers.  */
1544+      return 0;
1545+    }
1546+
1547+  size = int_size_in_bytes (type);
1548+  if (size >=0 && size <= UNITS_PER_WORD)
1549+    {
1550+      /* If it can fit in one register */
1551+      return 0;
1552+    }
1553
1554+  return 1;
1555+}
1556+
1557+/* Determine if given constant can be used as a register displacement */
1558+int
1559+const_ok_for_base_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1560+{
1561+  int val;
1562+
1563+  val = INTVAL (op);
1564+  return OFFSET_INT (val);
1565+}
1566+
1567+/* Generate an emit a word sized add instruction */
1568+static rtx
1569+emit_add (rtx dest, rtx src0, rtx src1)
1570+{
1571+  rtx insn;
1572+  insn = emit_insn (gen_addsi3 (dest, src0, src1));
1573+  return insn;
1574+}
1575+
1576+/* Generate the code to compare (and possibly branch) two integer values
1577+   TEST_CODE is the comparison code we are trying to emulate
1578+     (or implement directly)
1579+   RESULT is where to store the result of the comparison,
1580+     or null to emit a branch
1581+   CMP0 CMP1 are the two comparison operands
1582+   DESTINATION is the destination of the branch, or null to only compare
1583+   */
1584+
1585+void
1586+gen_int_relational (enum rtx_code code, /* relational test (EQ, etc) */
1587+                   rtx result,         /* result to store comp. or 0 if branch */
1588+                   rtx cmp0,           /* first operand to compare */
1589+                   rtx cmp1,           /* second operand to compare */
1590+                   rtx destination)    /* destination of the branch, or 0 if compare */
1591+{
1592+  enum machine_mode mode;
1593+  int branch_p;
1594+
1595+  mode = GET_MODE (cmp0);
1596+  if (mode == VOIDmode)
1597+    mode = GET_MODE (cmp1);
1598+
1599+  /* Is this a branch or compare */
1600+  branch_p = (destination != 0);
1601+
1602+  /* Instruction set doesn't support LE or LT, so swap operands and use GE, GT */
1603+  switch (code)
1604+    {
1605+      case LE:
1606+      case LT:
1607+      case LEU:
1608+      case LTU:
1609+        code = swap_condition (code);
1610+        rtx temp = cmp0;
1611+        cmp0 = cmp1;
1612+        cmp1 = temp;       
1613+        break;
1614+      default:
1615+        break; 
1616+    }
1617+   
1618+  if (branch_p)
1619+    {
1620+      rtx insn;
1621+     
1622+      /* Operands must be in registers */
1623+      if (!register_operand (cmp0, mode))
1624+        cmp0 = force_reg (mode, cmp0);
1625+      if (!register_operand (cmp1, mode))
1626+        cmp1 = force_reg (mode, cmp1);
1627+
1628+      /* Generate conditional branch instruction */           
1629+      rtx cond = gen_rtx_fmt_ee (code, mode, cmp0, cmp1);
1630+      rtx label = gen_rtx_LABEL_REF (VOIDmode, destination);
1631+      insn = gen_rtx_SET (VOIDmode, pc_rtx,
1632+            gen_rtx_IF_THEN_ELSE (VOIDmode,
1633+                           cond, label, pc_rtx));
1634+      emit_jump_insn (insn);
1635+    }
1636+  else
1637+    {   
1638+      /* We can't have const_ints in cmp0, other than 0 */
1639+      if ((GET_CODE (cmp0) == CONST_INT) && (INTVAL (cmp0) != 0))
1640+        cmp0 = force_reg (mode, cmp0);
1641+   
1642+      /* If the comparison is against an int not in legal range
1643+         move it into a register */
1644+      if (GET_CODE (cmp1) == CONST_INT)
1645+        {
1646+          HOST_WIDE_INT value = INTVAL (cmp1);
1647+          switch (code)
1648+            {
1649+              case EQ: case NE: case LE: case LT: case GE: case GT:
1650+                if (!MEDIUM_INT(value))
1651+                  cmp1 = force_reg (mode, cmp1);
1652+                break;
1653+              case LEU: case LTU: case GEU: case GTU:
1654+                if (!MEDIUM_UINT(value))
1655+                  cmp1 = force_reg (mode, cmp1);
1656+                break;
1657+              default:
1658+                abort ();
1659+            }   
1660+        }
1661+   
1662+      /* Generate compare instruction */
1663+      emit_move_insn (result, gen_rtx_fmt_ee (code, mode, cmp0, cmp1));
1664+    }
1665+}
1666+
1667+/* Generate and emit RTL to save or restore callee save registers */
1668+static void
1669+expand_save_restore (struct lm32_frame_info *info, int op)
1670+{
1671+  unsigned int reg_save_mask = info->reg_save_mask;
1672+  int regno;
1673+  HOST_WIDE_INT offset;
1674+  rtx insn;
1675+
1676+  /* Callee saves are below locals and above outgoing arguments */
1677+  offset = info->args_size + info->callee_size;
1678+  for (regno = 0; regno <= 31; regno++)
1679+    {
1680+      if ((reg_save_mask & (1 << regno)) != 0)
1681+        {
1682+          if (op == 0)
1683+            {
1684+              insn = emit_move_insn (gen_rtx_MEM (word_mode,
1685+                                                  gen_rtx_PLUS (Pmode,
1686+                                                                stack_pointer_rtx,
1687+                                                                GEN_INT (offset))),
1688+                                     gen_rtx_REG (word_mode, regno));
1689+            }
1690+          else
1691+            {
1692+              insn = emit_move_insn (gen_rtx_REG (word_mode, regno),
1693+                                     gen_rtx_MEM (word_mode,
1694+                                                  gen_rtx_PLUS (Pmode,
1695+                                                                stack_pointer_rtx,
1696+                                                                GEN_INT (offset))));
1697+            }
1698+
1699+         /* only prologue instructions which set the sp fp or save a
1700+            register should be marked as frame related */
1701+          if (op==0)
1702+           RTX_FRAME_RELATED_P (insn) = 1;
1703+          offset -= UNITS_PER_WORD;
1704+        }
1705+    }
1706+}
1707+
1708+static void
1709+stack_adjust (HOST_WIDE_INT amount)
1710+{
1711+  rtx insn;
1712
1713+  if (!MEDIUM_INT (amount))
1714+    {
1715+      /* r10 is caller saved so it can be used as a temp reg */
1716+      rtx r10;
1717+      r10 = gen_rtx_REG (word_mode, 10); 
1718+      insn = emit_move_insn (r10, GEN_INT (amount));
1719+      if (amount < 0)
1720+       RTX_FRAME_RELATED_P (insn) = 1;
1721+      insn = emit_add (stack_pointer_rtx, stack_pointer_rtx, r10);
1722+      if (amount < 0)
1723+       RTX_FRAME_RELATED_P (insn) = 1;
1724+    }
1725+  else
1726+    {
1727+      insn = emit_add (stack_pointer_rtx,
1728+                       stack_pointer_rtx,
1729+                       GEN_INT (amount));
1730+      if (amount < 0)
1731+       RTX_FRAME_RELATED_P (insn) = 1;
1732+    }
1733+}
1734+
1735+
1736+/* Create and emit instructions for a functions prologue */
1737+void
1738+lm32_expand_prologue (void)
1739+{
1740+  rtx insn;
1741+   
1742+  lm32_compute_frame_size (get_frame_size ());
1743+       
1744+  if (current_frame_info.total_size > 0)
1745+    {
1746+      /* Add space on stack new frame  */
1747+      stack_adjust (-current_frame_info.total_size);
1748+                               
1749+      /* Save callee save registers */
1750+      if (current_frame_info.reg_save_mask != 0)
1751+        expand_save_restore (&current_frame_info, 0);
1752+       
1753+      /* Setup frame pointer if it's needed */               
1754+      if (frame_pointer_needed == 1)
1755+        {
1756+          /* Load offset - Don't use total_size, as that includes pretend_size, which isn't part of this frame? */
1757+          insn = emit_move_insn (frame_pointer_rtx, GEN_INT (  current_frame_info.args_size
1758+                                                             + current_frame_info.callee_size
1759+                                                             + current_frame_info.locals_size));
1760+          RTX_FRAME_RELATED_P (insn) = 1;
1761+         
1762+          /* Add in sp */
1763+          insn = emit_add (frame_pointer_rtx,
1764+                           frame_pointer_rtx,
1765+                           stack_pointer_rtx);
1766+          RTX_FRAME_RELATED_P (insn) = 1;
1767+        } 
1768+               
1769+      /* Prevent prologue from being scheduled into function body */
1770+      emit_insn (gen_blockage ());       
1771+    }
1772+}
1773+
1774+/* Create an emit instructions for a functions epilogue */
1775+void
1776+lm32_expand_epilogue (void)
1777+{
1778+  rtx ra_rtx = gen_rtx_REG (Pmode, RA_REGNUM);
1779+   
1780+  lm32_compute_frame_size (get_frame_size ());
1781+
1782+  if (current_frame_info.total_size > 0)
1783+    {       
1784+      /* Prevent stack code from being reordered */
1785+      emit_insn (gen_blockage ());             
1786+           
1787+      /* Restore callee save registers */
1788+      if (current_frame_info.reg_save_mask != 0)
1789+        expand_save_restore (&current_frame_info, 1);         
1790+     
1791+      /* Deallocate stack */
1792+      stack_adjust (current_frame_info.total_size);
1793+
1794+      /* Return to calling function */
1795+      emit_jump_insn (gen_return_internalsi (ra_rtx));                   
1796+    }
1797+  else
1798+    {
1799+      /* Return to calling function */
1800+      emit_jump_insn (gen_return_internalsi (ra_rtx));
1801+    }   
1802+}
1803+
1804+/* Return the bytes needed to compute the frame pointer from the current
1805+   stack pointer. */
1806+HOST_WIDE_INT
1807+lm32_compute_frame_size (int size)
1808+{
1809+  int regno;
1810+  HOST_WIDE_INT total_size, locals_size, args_size, pretend_size, callee_size;
1811+  unsigned int reg_save_mask;
1812+
1813+  locals_size = size;
1814+  args_size = crtl->outgoing_args_size;
1815+  pretend_size = crtl->args.pretend_args_size;
1816+  callee_size = 0;
1817+  reg_save_mask = 0;
1818+   
1819+  /* Build mask that actually determines which regsiters we save
1820+     and calculate size required to store them in the stack. */
1821+  for (regno = 1; regno < SP_REGNUM; regno++)
1822+    {
1823+      if (df_regs_ever_live_p(regno) && !call_used_regs[regno])
1824+        {
1825+          reg_save_mask |= 1 << regno;
1826+          callee_size += UNITS_PER_WORD;
1827+        }
1828+    }
1829+  if (df_regs_ever_live_p(RA_REGNUM) || !current_function_is_leaf || !optimize)
1830+    {
1831+      reg_save_mask |= 1 << RA_REGNUM;       
1832+      callee_size += UNITS_PER_WORD;
1833+    }
1834+  if (!(reg_save_mask & (1 << FP_REGNUM)) && frame_pointer_needed)
1835+    {
1836+      reg_save_mask |= 1 << FP_REGNUM;       
1837+      callee_size += UNITS_PER_WORD;
1838+    }
1839+
1840+  /* Compute total frame size */
1841+  total_size = pretend_size + args_size + locals_size + callee_size;
1842+     
1843+  /* Align frame to appropriate boundary */
1844+  total_size = (total_size+3) & ~3;
1845
1846+  /* Save computed information.  */
1847+  current_frame_info.total_size = total_size;
1848+  current_frame_info.callee_size = callee_size;
1849+  current_frame_info.pretend_size = pretend_size;
1850+  current_frame_info.locals_size = locals_size;
1851+  current_frame_info.args_size = args_size;
1852+  current_frame_info.reg_save_mask = reg_save_mask;
1853+
1854+  return total_size;
1855+}
1856+
1857+void
1858+lm32_print_operand (FILE *file, rtx op, int letter)
1859+{
1860+  register enum rtx_code code;
1861+
1862+  if (! op)
1863+    {
1864+      error ("PRINT_OPERAND null pointer");
1865+      abort ();
1866+    }
1867+
1868+  code = GET_CODE (op);
1869+
1870+  if (code == SIGN_EXTEND)
1871+    op = XEXP (op, 0), code = GET_CODE (op);
1872+  else if (code == REG || code == SUBREG)
1873+    {
1874+      int regnum;
1875+
1876+      if (code == REG)
1877+        regnum = REGNO (op);
1878+      else
1879+        regnum = true_regnum (op);
1880+
1881+     if (   (letter == 'H' && !WORDS_BIG_ENDIAN)
1882+         || (letter == 'L' && WORDS_BIG_ENDIAN))
1883+         {
1884+         abort();
1885+            regnum++;
1886+            }
1887+
1888+      fprintf (file, "%s", reg_names[regnum]);
1889+    }
1890+  else if (code == MEM)
1891+      output_address (XEXP (op, 0));
1892+  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1893+    fprintf (file, "%s", reg_names[0]);
1894+  else if (GET_CODE (op) == CONST_DOUBLE)
1895+    {
1896+      if ((CONST_DOUBLE_LOW (op) != 0) || (CONST_DOUBLE_HIGH (op) != 0))
1897+        output_operand_lossage ("Only 0.0 can be loaded as an immediate");
1898+      else
1899+        fprintf (file, "0");
1900+    }       
1901+  else if (code == EQ)
1902+    fprintf (file, "e  "); 
1903+  else if (code == NE)
1904+    fprintf (file, "ne ");       
1905+  else if (code == GT)
1906+    fprintf (file, "g  ");   
1907+  else if (code == GTU)
1908+    fprintf (file, "gu ");   
1909+  else if (code == LT)
1910+    fprintf (file, "l  ");       
1911+  else if (code == LTU)
1912+    fprintf (file, "lu ");       
1913+  else if (code == GE)
1914+    fprintf (file, "ge ");       
1915+  else if (code == GEU)
1916+    fprintf (file, "geu");       
1917+  else if (code == LE)
1918+    fprintf (file, "le ");       
1919+  else if (code == LEU)
1920+    fprintf (file, "leu");                 
1921+  else
1922+    output_addr_const (file, op);
1923+}
1924+
1925+/* A C compound statement to output to stdio stream STREAM the
1926+   assembler syntax for an instruction operand that is a memory
1927+   reference whose address is ADDR.  ADDR is an RTL expression.
1928+
1929+   On some machines, the syntax for a symbolic address depends on
1930+   the section that the address refers to.  On these machines,
1931+   define the macro `ENCODE_SECTION_INFO' to store the information
1932+   into the `symbol_ref', and then check for it here.  */
1933+
1934+void
1935+lm32_print_operand_address (FILE *file, rtx addr)
1936+{
1937+  switch (GET_CODE (addr))
1938+    {
1939+    case REG:
1940+      fprintf (file, "(%s+0)", reg_names [REGNO (addr)]);
1941+      break;
1942+
1943+    case MEM:
1944+      output_address (XEXP (addr, 0));
1945+      break;
1946+
1947+    case PLUS:
1948+      {
1949+        rtx arg0 = XEXP (addr, 0);
1950+        rtx arg1 = XEXP (addr, 1);
1951+             
1952+        if (GET_CODE (arg0) == REG && CONSTANT_P (arg1))
1953+          {
1954+            if (GET_CODE(arg1) == CONST_INT)
1955+              fprintf (file, "(%s+%ld)", reg_names [REGNO (arg0)], INTVAL (arg1));
1956+            else
1957+              {
1958+                fprintf (file, "(%s+", reg_names [REGNO (arg0)]);
1959+                output_addr_const (file, arg1);
1960+                fprintf (file, ")");
1961+              }
1962+          }
1963+        else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
1964+          output_addr_const (file, addr);
1965+        else
1966+          abort_with_insn (addr, "bad operand");
1967+      }
1968+      break;
1969+   
1970+    case SYMBOL_REF:
1971+      if (SYMBOL_REF_SMALL_P (addr))
1972+        {       
1973+          fprintf (file, "gp(");
1974+          output_addr_const (file, addr);
1975+          fprintf (file, ")");
1976+        }
1977+      else
1978+        abort_with_insn (addr, "can't use non gp relative absolute address");
1979+      break;     
1980+       
1981+    default:
1982+      abort_with_insn (addr, "invalid addressing mode");
1983+      break;
1984+    }
1985+}
1986+
1987+/* Determine where to put an argument to a function.
1988+   Value is zero to push the argument on the stack,
1989+   or a hard register in which to store the argument.
1990+
1991+   MODE is the argument's machine mode.
1992+   TYPE is the data type of the argument (as a tree).
1993+    This is null for libcalls where that information may
1994+    not be available.
1995+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
1996+    the preceding args and about the function being called.
1997+   NAMED is nonzero if this argument is a named parameter
1998+    (otherwise it is an extra parameter matching an ellipsis).  */
1999+
2000+rtx
2001+lm32_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode,
2002+                   tree type, int named)
2003+{       
2004+  if (mode == VOIDmode)
2005+    /* Compute operand 2 of the call insn.  */
2006+    return GEN_INT (0);
2007+
2008+  if (targetm.calls.must_pass_in_stack (mode, type))
2009+    return NULL_RTX;
2010+   
2011+  if (!named  || (cum + LM32_NUM_REGS2(mode, type) > LM32_NUM_ARG_REGS))
2012+    return NULL_RTX;
2013+
2014+  return gen_rtx_REG (mode, cum + LM32_FIRST_ARG_REG);
2015+}
2016+
2017+HOST_WIDE_INT
2018+lm32_compute_initial_elimination_offset (int from, int to)
2019+{
2020+  HOST_WIDE_INT offset = 0;
2021
2022+  switch (from)
2023+    {
2024+    /*case FRAME_POINTER_REGNUM: - Same as ARG_POINTER_REGNUM */
2025+    case ARG_POINTER_REGNUM:
2026+      switch (to)
2027+        {
2028+        case FRAME_POINTER_REGNUM:
2029+          offset = 0;
2030+          break;
2031+        case STACK_POINTER_REGNUM:
2032+          offset = lm32_compute_frame_size (get_frame_size ()) - current_frame_info.pretend_size;
2033+          break;
2034+        default:
2035+          abort ();
2036+        }
2037+      break;
2038+    default:
2039+      abort ();
2040+    }
2041+   
2042+  return offset;   
2043+}
2044+
2045+static void
2046+lm32_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2047+                             tree type, int *pretend_size, int no_rtl)
2048+{
2049+  int first_anon_arg;
2050+  tree fntype;
2051+  int stdarg_p;
2052
2053+  fntype = TREE_TYPE (current_function_decl);
2054+  stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
2055+             && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2056+                 != void_type_node));
2057+   
2058+  if (stdarg_p)
2059+    first_anon_arg = *cum + LM32_FIRST_ARG_REG;
2060+  else
2061+    {
2062+      /* this is the common case, we have been passed details setup
2063+         for the last named argument, we want to skip over the
2064+         registers, if any used in passing this named paramter in
2065+         order to determine which is the first registers used to pass
2066+         anonymous arguments */
2067+      int size;
2068+
2069+      if (mode==BLKmode)
2070+        size = int_size_in_bytes (type);
2071+      else
2072+        size = GET_MODE_SIZE (mode);
2073+     
2074+      first_anon_arg = *cum + LM32_FIRST_ARG_REG + ((size + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
2075+    }
2076+
2077+  if ((first_anon_arg < (LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS)) && !no_rtl)
2078+    {
2079+      int first_reg_offset = first_anon_arg;
2080+      int size = LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS - first_anon_arg;
2081+      rtx regblock;
2082+
2083+      regblock = gen_rtx_MEM (BLKmode,
2084+                              plus_constant (arg_pointer_rtx,
2085+                                             FIRST_PARM_OFFSET (0)));
2086+      move_block_from_reg (first_reg_offset, regblock, size);
2087+
2088+      *pretend_size = size * UNITS_PER_WORD;
2089+    }
2090+}
2091+
2092+/* Abort after printing out a specific insn.  */
2093+static void
2094+abort_with_insn (rtx insn, const char *reason)
2095+{
2096+  error (reason);
2097+  debug_rtx (insn);
2098+  abort ();
2099+}
2100+
2101+/* Override command line options */
2102+void
2103+lm32_override_options (void)
2104+{         
2105+  /* We must have sign-extend enabled if barrel-shift isn't */
2106+  if (!MASK_BARREL_SHIFT_ENABLED)
2107+    {
2108+      warning (0, "neither -mbarrel-shift-enabled nor -msign-extend-enabled specified. Assuming -msign-extend-enabled");
2109+      target_flags |= MASK_SIGN_EXTEND_ENABLED;
2110+    }
2111+}
2112+
2113+/* Return nonzero if this function is known to have a null epilogue.
2114+   This allows the optimizer to omit jumps to jumps if no stack
2115+   was created.  */
2116+int
2117+lm32_can_use_return (void)
2118+{
2119+  if (!reload_completed)
2120+    return 0;
2121
2122+  if (df_regs_ever_live_p(RA_REGNUM) || crtl->profile)
2123+    return 0;
2124+   
2125+  if (lm32_compute_frame_size (get_frame_size ()) != 0)
2126+    return 0;
2127+   
2128+  return 1;
2129+}
2130+
2131+/* Support function to determine the return address of the function
2132+   'count' frames back up the stack. */
2133+rtx
2134+lm32_return_addr_rtx (int count, rtx frame)
2135+{
2136+  rtx r;
2137+  if (count == 0)
2138+    {
2139+      /* *mjs* This test originally used leaf_function_p (), we now use
2140+        the regs_ever_live test which I *think* is more accurate. */
2141+      if (!df_regs_ever_live_p(RA_REGNUM))
2142+       {
2143+         r = gen_rtx_REG (Pmode, RA_REGNUM);
2144+       }
2145+      else
2146+       {
2147+         r = gen_rtx_MEM (Pmode,
2148+                          gen_rtx_PLUS (Pmode, frame,
2149+                                        GEN_INT(- 2 * UNITS_PER_WORD)));
2150+         set_mem_alias_set (r, get_frame_alias_set ());
2151+       }
2152+    }
2153+  else if (flag_omit_frame_pointer)
2154+    r = NULL_RTX;
2155+  else
2156+    {
2157+      r = gen_rtx_MEM (Pmode,
2158+                      gen_rtx_PLUS (Pmode, frame,
2159+                                    GEN_INT(- 2 * UNITS_PER_WORD)));
2160+      set_mem_alias_set (r, get_frame_alias_set ());
2161+    }
2162+  return r;
2163+}
2164+
2165+/* Return true if EXP should be placed in the small data section.  */
2166+
2167+static bool
2168+lm32_in_small_data_p (const_tree exp)
2169+{
2170+  /* We want to merge strings, so we never consider them small data.  */
2171+  if (TREE_CODE (exp) == STRING_CST)
2172+    return false;
2173+
2174+  /* Functions are never in the small data area.  Duh.  */
2175+  if (TREE_CODE (exp) == FUNCTION_DECL)
2176+    return false;
2177+
2178+  if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2179+    {
2180+      const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2181+      if (strcmp (section, ".sdata") == 0
2182+         || strcmp (section, ".sbss") == 0)
2183+       return true;
2184+    }
2185+  else
2186+    {
2187+      HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2188+
2189+      /* If this is an incomplete type with size 0, then we can't put it
2190+        in sdata because it might be too big when completed.  */
2191+      if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
2192+       return true;
2193+    }
2194+
2195+  return false;
2196+}
2197+
2198+/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2199+   Assume that the areas do not overlap.  */
2200+
2201+static void
2202+lm32_block_move_inline (rtx dest, rtx src, HOST_WIDE_INT length, HOST_WIDE_INT alignment)
2203+{
2204+  HOST_WIDE_INT offset, delta;
2205+  unsigned HOST_WIDE_INT bits;
2206+  int i;
2207+  enum machine_mode mode;
2208+  rtx *regs;
2209+
2210+  /* Work out how many bits to move at a time.  */
2211+  switch (alignment)
2212+    {
2213+      case 1:
2214+        bits = 8;
2215+        break;
2216+      case 2:
2217+        bits = 16;
2218+        break;
2219+      case 4:
2220+        bits = 32;
2221+        break;
2222+      default:
2223+        abort ();
2224+    }
2225+
2226+  mode = mode_for_size (bits, MODE_INT, 0);
2227+  delta = bits / BITS_PER_UNIT;
2228+
2229+  /* Allocate a buffer for the temporary registers.  */
2230+  regs = alloca (sizeof (rtx) * length / delta);
2231+
2232+  /* Load as many BITS-sized chunks as possible.  */
2233+  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
2234+    {
2235+      regs[i] = gen_reg_rtx (mode);
2236+      emit_move_insn (regs[i], adjust_address (src, mode, offset));
2237+    }
2238+
2239+  /* Copy the chunks to the destination.  */
2240+  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
2241+    emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
2242+
2243+  /* Mop up any left-over bytes.  */
2244+  if (offset < length)
2245+    {
2246+      src = adjust_address (src, BLKmode, offset);
2247+      dest = adjust_address (dest, BLKmode, offset);
2248+      move_by_pieces (dest, src, length - offset,
2249+                     MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
2250+    }
2251+}
2252+
2253+/* Expand string/block move operations.
2254+
2255+   operands[0] is the pointer to the destination.
2256+   operands[1] is the pointer to the source.
2257+   operands[2] is the number of bytes to move.
2258+   operands[3] is the alignment.  */
2259+
2260+int
2261+lm32_expand_block_move (rtx *operands)
2262+{
2263+  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) <= 32))
2264+    {
2265+      lm32_block_move_inline (operands[0], operands[1], INTVAL (operands[2]), INTVAL (operands[3]));
2266+      return 1;
2267+    }
2268+  return 0;
2269+}
2270+
2271+/* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
2272+   isn't protected by a PIC unspec.  */
2273+int
2274+nonpic_symbol_mentioned_p (rtx x)
2275+{
2276+  register const char *fmt;
2277+  register int i;
2278+
2279+  if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
2280+      || GET_CODE (x) == PC)
2281+    return 1;
2282+
2283+  /* We don't want to look into the possible MEM location of a
2284+     CONST_DOUBLE, since we're not going to use it, in general.  */
2285+  if (GET_CODE (x) == CONST_DOUBLE)
2286+    return 0;
2287+
2288+  if (GET_CODE (x) == UNSPEC)
2289+    return 0;
2290+
2291+  fmt = GET_RTX_FORMAT (GET_CODE (x));
2292+  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2293+    {
2294+      if (fmt[i] == 'E')
2295+       {
2296+         register int j;
2297+
2298+         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2299+           if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
2300+             return 1;
2301+       }
2302+      else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
2303+       return 1;
2304+    }
2305+
2306+  return 0;
2307+}
2308diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.h gcc-4.4.6/gcc/config/lm32/lm32.h
2309--- gcc-4.4.6.orig/gcc/config/lm32/lm32.h       1970-01-01 01:00:00.000000000 +0100
2310+++ gcc-4.4.6/gcc/config/lm32/lm32.h    2011-04-20 17:27:23.064805897 +0200
2311@@ -0,0 +1,657 @@
2312+/* Definitions of target machine for GNU compiler, Lattice Mico32 architecture.
2313+   Contributed by Jon Beniston <jon@beniston.com>
2314+
2315+   Copyright (C) 2008 Free Software Foundation, Inc.
2316+
2317+   This file is part of GCC.
2318+
2319+   GCC is free software; you can redistribute it and/or modify it
2320+   under the terms of the GNU General Public License as published
2321+   by the Free Software Foundation; either version 3, or (at your
2322+   option) any later version.
2323+
2324+   GCC is distributed in the hope that it will be useful, but WITHOUT
2325+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2326+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
2327+   License for more details.
2328+
2329+   You should have received a copy of the GNU General Public License
2330+   along with GCC; see the file COPYING3.  If not see
2331+   <http://www.gnu.org/licenses/>.  */
2332+
2333+/*-------------------------------*/
2334+/* Run-time Target Specification */
2335+/*-------------------------------*/
2336+
2337+/* Print subsidiary information on the compiler version in use.  */
2338+#ifndef TARGET_VERSION
2339+#define TARGET_VERSION fprintf (stderr, " (LatticeMico32)")
2340+#endif
2341+
2342+/* Target CPU builtins.  */
2343+#define TARGET_CPU_CPP_BUILTINS()               \
2344+  do                                            \
2345+    {                                           \
2346+      builtin_define ("__lm32__");              \
2347+      builtin_define_std ("lm32");              \
2348+      builtin_assert ("cpu=lm32");              \
2349+      builtin_assert ("machine=lm32");          \
2350+    }                                           \
2351+  while (0)
2352+
2353+#define CPP_SPEC "\
2354+%{mmultiply-enabled:-D__multiply_enabled__} \
2355+%{mdivide-enabled:-D__divide_enabled__} \
2356+%{mbarrel-shift-enabled:-D__barrel_shift_enabled__} \
2357+%{msign-extend-enabled:-D__sign_extend_enabled__} \
2358+%{muser-enabled:-D__user_enabled__} \
2359+"
2360+
2361+#undef  ASM_SPEC
2362+#define ASM_SPEC "\
2363+%{mmultiply-enabled} \
2364+%{mdivide-enabled} \
2365+%{mbarrel-shift-enabled} \
2366+%{msign-extend-enabled} \
2367+%{muser-extend-enabled} \
2368+%{v} \
2369+"
2370+
2371+/* Let link script define all link options.
2372+   Default to using simulator link script.  */
2373+
2374+#undef  STARTFILE_SPEC
2375+#define STARTFILE_SPEC ""
2376+#undef  ENDFILE_SPEC
2377+#define ENDFILE_SPEC ""
2378+#undef  LIB_SPEC
2379+#define LIB_SPEC "%{!T*:-T sim.ld}"
2380+
2381+#define OVERRIDE_OPTIONS lm32_override_options()
2382+
2383+extern int target_flags;
2384+
2385+/* Add -G xx support.  */
2386+
2387+#undef  SWITCH_TAKES_ARG
2388+#define SWITCH_TAKES_ARG(CHAR) \
2389+(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
2390+
2391+#undef  CC1_SPEC
2392+#define CC1_SPEC "%{G*}"
2393+
2394+extern struct rtx_def *lm32_compare_op0;
2395+extern struct rtx_def *lm32_compare_op1;
2396+
2397+/*---------------------------------*/
2398+/* Target machine storage layout.  */
2399+/*---------------------------------*/
2400+
2401+#define BITS_BIG_ENDIAN 0
2402+#define BYTES_BIG_ENDIAN 1
2403+#define WORDS_BIG_ENDIAN 1
2404+#define LIBGCC2_WORDS_BIG_ENDIAN 1
2405+
2406+#define BITS_PER_UNIT 8
2407+#define BITS_PER_WORD 32
2408+#define UNITS_PER_WORD 4
2409+
2410+#define POINTER_SIZE 32
2411+
2412+#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)               \
2413+do {                                                    \
2414+  if (GET_MODE_CLASS (MODE) == MODE_INT                 \
2415+      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
2416+    (MODE) = word_mode;                                 \
2417+} while (0)
2418+
2419+#define PARM_BOUNDARY 32
2420+
2421+#define STACK_BOUNDARY 32
2422+
2423+#define BIGGEST_ALIGNMENT 64
2424+
2425+#define FUNCTION_BOUNDARY  32
2426+
2427+#define EMPTY_FIELD_BOUNDARY 32
2428+
2429+#define STRICT_ALIGNMENT 1
2430+
2431+#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2432+
2433+/* Make strings word-aligned so strcpy from constants will be faster.  */
2434+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
2435+  (TREE_CODE (EXP) == STRING_CST       \
2436+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
2437+
2438+/* Make arrays and structures word-aligned to allow faster copying etc.  */
2439+#define DATA_ALIGNMENT(TYPE, ALIGN)                                    \
2440+  ((((ALIGN) < BITS_PER_WORD)                                          \
2441+    && (TREE_CODE (TYPE) == ARRAY_TYPE                                 \
2442+       || TREE_CODE (TYPE) == UNION_TYPE                               \
2443+       || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
2444+
2445+/* We need this for the same reason as DATA_ALIGNMENT, namely to cause
2446+   character arrays to be word-aligned so that `strcpy' calls that copy
2447+   constants to character arrays can be done inline, and 'strcmp' can be
2448+   optimised to use word loads. */
2449+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
2450+  DATA_ALIGNMENT (TYPE, ALIGN)
2451+   
2452+/*----------------------------------------*/
2453+/* Layout of source language data types.  */
2454+/*----------------------------------------*/
2455+
2456+#define INT_TYPE_SIZE              32
2457+#define SHORT_TYPE_SIZE                    16
2458+#define LONG_TYPE_SIZE             32
2459+#define LONG_LONG_TYPE_SIZE        64
2460+
2461+#define FLOAT_TYPE_SIZE                    32
2462+#define DOUBLE_TYPE_SIZE           64
2463+#define LONG_DOUBLE_TYPE_SIZE       64
2464+
2465+#define DEFAULT_SIGNED_CHAR         0
2466+
2467+#define SIZE_TYPE "unsigned int"
2468+
2469+#define PTRDIFF_TYPE "int"
2470+
2471+/*---------------------------*/
2472+/* Standard register usage.  */
2473+/*---------------------------*/
2474+
2475+#define FIRST_PSEUDO_REGISTER  32
2476+
2477+#define RV_REGNUM   1
2478+#define GP_REGNUM   26
2479+#define FP_REGNUM   27
2480+#define SP_REGNUM   28
2481+#define RA_REGNUM   29
2482+
2483+#define G_REG_P(X)      ((X)<32)
2484+#define PSEUDO_REG_P(X) ((X)>=FIRST_PSEUDO_REGISTER)
2485+
2486+#define FIXED_REGISTERS   \
2487+{ 1, 0, 0, 0, 0, 0, 0, 0, \
2488+  0, 0, 0, 0, 0, 0, 0, 0, \
2489+  0, 0, 0, 0, 0, 0, 0, 0, \
2490+  0, 0, 1, 0, 1, 0, 1, 1}
2491+
2492+#define CALL_USED_REGISTERS \
2493+{ 1, 1, 1, 1, 1, 1, 1, 1,   \
2494+  1, 1, 1, 0, 0, 0, 0, 0,   \
2495+  0, 0, 0, 0, 0, 0, 0, 0,   \
2496+  0, 0, 1, 0, 1, 0, 1, 1}
2497
2498+#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
2499+    ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)     
2500+
2501+#define HARD_REGNO_MODE_OK(REGNO, MODE) G_REG_P(REGNO)
2502+
2503+#define MODES_TIEABLE_P(MODE1, MODE2)           \
2504+(      GET_MODE_CLASS (MODE1) == MODE_INT              \
2505+    && GET_MODE_CLASS (MODE2) == MODE_INT              \
2506+    && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
2507+    && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
2508+
2509+#define AVOID_CCMODE_COPIES
2510+
2511+/*----------------------------------*/
2512+/* Register classes and constants.  */
2513+/*----------------------------------*/
2514+
2515+enum reg_class {
2516+  NO_REGS,
2517+  GENERAL_REGS,
2518+  ALL_REGS,
2519+  LIM_REG_CLASSES
2520+};
2521+
2522+#define N_REG_CLASSES (int) LIM_REG_CLASSES
2523+
2524+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
2525+
2526+#define REG_CLASS_CONTENTS      \
2527+{ {0x00000000},                 \
2528+  {0xffffffff},                 \
2529+  {0xffffffff}                  \
2530+}
2531+
2532+#define REGNO_REG_CLASS(REGNO) \
2533+    (G_REG_P(REGNO) ? GENERAL_REGS : NO_REGS)
2534+   
2535+#define CLASS_MAX_NREGS(CLASS, MODE) \
2536+    ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)     
2537+   
2538+#define INDEX_REG_CLASS NO_REGS
2539+
2540+#define BASE_REG_CLASS GENERAL_REGS
2541+
2542+#define REG_CLASS_FROM_LETTER(C) NO_REGS
2543+
2544+#ifdef REG_OK_STRICT
2545+#define REGNO_OK_FOR_BASE_P(REGNO)                                     \
2546+(G_REG_P (REGNO) || G_REG_P (reg_renumber[REGNO]))
2547+#else
2548+#define REGNO_OK_FOR_BASE_P(REGNO)                                     \
2549+(G_REG_P (REGNO) || PSEUDO_REG_P (REGNO))
2550+#endif
2551+
2552+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
2553+
2554+#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
2555+
2556+/* The letters I, J, K, L, M, N, O, P in a register constraint string
2557+   can be used to stand for particular ranges of immediate operands.
2558+   This macro defines what the ranges are.
2559+   C is the letter, and VALUE is a constant value.
2560+   Return 1 if VALUE is in the range specified by C. 
2561+   
2562+   Lattice usage:
2563+   
2564+   J - 0
2565+   K - 16-bit signed
2566+   L - 16-bit unsigned
2567+   M - 32-bit signed
2568+   */
2569+#define MEDIUM_INT(X)  ((((HOST_WIDE_INT)(X)) >= -32768) && (((HOST_WIDE_INT)(X)) < 32768))
2570+#define MEDIUM_UINT(X) (((unsigned HOST_WIDE_INT)(X)) < 65536)
2571+#define LARGE_INT(X)                                    \
2572+((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1)               \
2573+ && (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
2574+
2575+#define CONST_OK_FOR_LETTER_P(VALUE, C)                 \
2576+(  (C) == 'J' ? (VALUE) == 0                            \
2577+ : (C) == 'K' ? MEDIUM_INT (VALUE)                      \
2578+ : (C) == 'L' ? MEDIUM_UINT (VALUE)                     \
2579+ : (C) == 'M' ? LARGE_INT (VALUE)                       \
2580+ : 0                                                    \
2581+)
2582+
2583+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
2584+
2585+/*----------------------------------------*/
2586+/* Stack Layout and Calling Conventions.  */
2587+/*----------------------------------------*/
2588+
2589+#define STACK_GROWS_DOWNWARD 1
2590+
2591+#define FRAME_GROWS_DOWNWARD 1
2592+
2593+#define STACK_POINTER_OFFSET (UNITS_PER_WORD)
2594+
2595+#define STARTING_FRAME_OFFSET (UNITS_PER_WORD)
2596+
2597+#define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
2598+
2599+#define STACK_POINTER_REGNUM SP_REGNUM
2600+
2601+#define FRAME_POINTER_REGNUM FP_REGNUM
2602+
2603+#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
2604+
2605+#define FRAME_POINTER_REQUIRED (cfun->calls_alloca)
2606+
2607+#define RETURN_ADDR_RTX(count, frame)                               \
2608+  lm32_return_addr_rtx (count, frame)
2609+
2610+/* FIXME! */
2611+#define STATIC_CHAIN_REGNUM 3
2612+
2613+#define ELIMINABLE_REGS \
2614+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },        \
2615+ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },          \
2616+}
2617+
2618+#define CAN_ELIMINATE(FROM, TO)                                                    \
2619+   (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
2620+
2621+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)    \
2622+  (OFFSET) = lm32_compute_initial_elimination_offset (FROM, TO)
2623+
2624+/*-----------------------------*/
2625+/* Function argument passing.  */
2626+/*-----------------------------*/
2627+
2628+#define ACCUMULATE_OUTGOING_ARGS 1
2629+
2630+#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
2631+
2632+/*--------------------------------*/
2633+/* Passing Arguments in Registers */
2634+/*--------------------------------*/
2635+
2636+/* The first argument register */
2637+#define LM32_FIRST_ARG_REG 1
2638+
2639+/* The number of (integer) argument register available.  */
2640+#define LM32_NUM_ARG_REGS 8
2641+
2642+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2643+  lm32_function_arg ((CUM), (MODE), (TYPE), (NAMED))
2644+
2645+#define CUMULATIVE_ARGS int
2646+
2647+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
2648+  (CUM) = 0
2649+
2650+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2651+  (CUM) += LM32_NUM_REGS2 (MODE, TYPE)
2652+
2653+#define FUNCTION_ARG_REGNO_P(r)        (((r) >= 1) && ((r) <= LM32_NUM_ARG_REGS))
2654+
2655+/*--------------------*/
2656+/* Function results.  */
2657+/*--------------------*/
2658+
2659+#define FUNCTION_VALUE(VALTYPE, FUNC)                                   \
2660+   gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE)                              \
2661+                 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)           \
2662+                   ? word_mode                                         \
2663+                   : TYPE_MODE (VALTYPE),                                                  \
2664+                   RV_REGNUM)
2665+
2666+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RV_REGNUM)
2667+
2668+#define FUNCTION_VALUE_REGNO_P(N) ((N) == RV_REGNUM)
2669+
2670+#define RETURN_IN_MEMORY(TYPE) lm32_return_in_memory (TYPE)
2671+
2672+#define DEFAULT_PCC_STRUCT_RETURN 0
2673+
2674+/* Convert from bytes to ints.  */
2675+#define LM32_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2676+
2677+/* The number of (integer) registers required to hold a quantity of
2678+   type MODE.  */
2679+#define LM32_NUM_REGS(MODE) LM32_NUM_INTS (GET_MODE_SIZE (MODE))
2680+
2681+/* The number of (integer) registers required to hold a quantity of
2682+   TYPE MODE.  */
2683+#define LM32_NUM_REGS2(MODE, TYPE)                       \
2684+  LM32_NUM_INTS ((MODE) == BLKmode ?                     \
2685+  int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
2686+
2687+#define STRUCT_VALUE 0
2688+
2689+/*---------------------------*/
2690+/* Function entry and exit.  */
2691+/*---------------------------*/
2692+
2693+/*-------------*/
2694+/* Profiling.  */
2695+/*-------------*/
2696+
2697+#define FUNCTION_PROFILER(FILE, LABELNO)
2698+
2699+/*---------------*/
2700+/* Trampolines.  */
2701+/*---------------*/
2702+
2703+#define INITIALIZE_TRAMPOLINE 
2704+#define TRAMPOLINE_SIZE                0
2705+
2706+/*---------------------*/
2707+/*  Addressing Modes.  */
2708+/*---------------------*/
2709+
2710+#define CONSTANT_ADDRESS_P(X)                                          \
2711+  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF            \
2712+    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH               \
2713+    || (GET_CODE (X) == CONST)))
2714+
2715+#define MAX_REGS_PER_ADDRESS 1
2716+
2717+#ifdef REG_OK_STRICT
2718+#define REG_OK_FOR_FRAME_PTR_P(X) (REGNO (X) == FRAME_POINTER_REGNUM)
2719+#else
2720+#define REG_OK_FOR_FRAME_PTR_P(X) (REGNO (X) == FRAME_POINTER_REGNUM)
2721+#endif
2722+
2723+#define RTX_OK_FOR_BASE_P(X)                    (REG_P (X) && REG_OK_FOR_BASE_P (X))
2724+#define RTX_OK_FOR_STACK_P(X)                   (REG_P (X) && (REGNO (X) == STACK_POINTER_REGNUM))
2725+#define CONST_OK_FOR_BASE_OFFSET(X, MODE)       const_ok_for_base_offset ((X), (MODE))
2726+               
2727+#define LEGITIMATE_BASE_INDEX_P(ADDR, MODE)                     \
2728+(   GET_CODE (ADDR)==PLUS                                       \
2729+ && RTX_OK_FOR_BASE_P (XEXP (ADDR, 0))                          \
2730+ && GET_CODE (XEXP (ADDR, 1)) == CONST_INT                      \
2731+ && CONST_OK_FOR_BASE_OFFSET (XEXP ((ADDR), 1), (MODE)))       
2732+
2733+#define LEGITIMATE_GPREL_P(ADDR)                                \
2734+(   GET_CODE (ADDR) == SYMBOL_REF                               \
2735+ && SYMBOL_REF_SMALL_P (ADDR))
2736+
2737+#ifdef REG_OK_STRICT
2738+#define REG_OK_FOR_BASE_P(X) (G_REG_P (REGNO (X)))
2739+#else
2740+#define REG_OK_FOR_BASE_P(X) (G_REG_P (REGNO (X)) || PSEUDO_REG_P (REGNO (X)))
2741+#endif
2742+
2743+#ifdef REG_OK_STRICT
2744+#define REG_OK_FOR_INDEX_P(X) (G_REG_P (REGNO (X)))
2745+#else
2746+#define REG_OK_FOR_INDEX_P(X) (G_REG_P (REGNO (X)) || PSEUDO_REG_P (REGNO (X)))
2747+#endif
2748+
2749+#define GO_IF_LEGITIMATE_ADDRESS(m,x,l)                                                                                                     \
2750+{                                                                                                                                    \
2751+  if (RTX_OK_FOR_BASE_P (x)) goto l;                            /* (rM) */                                                      \
2752+  else if (LEGITIMATE_BASE_INDEX_P (x, m)) goto l;              /* (rM)+literal) */                                            \
2753+  else if (LEGITIMATE_GPREL_P (x)) goto l;                                                                                      \
2754+}
2755+
2756+#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)          \
2757+do {                                                        \
2758+  if (flag_pic)                                              \
2759+    X = lm32_legitimize_pic_address (OLDX, MODE, NULL_RTX);  \
2760+} while (0)
2761+
2762+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)                      \
2763+  if (GET_CODE (ADDR) == PLUS) goto LABEL;                             \
2764+
2765+#define LEGITIMATE_CONSTANT_P(X) 1
2766+
2767+/*-------------------------*/
2768+/* Condition Code Status.  */
2769+/*-------------------------*/
2770+
2771+#define REVERSIBLE_CC_MODE(MODE) 1
2772+
2773+/*---------*/
2774+/* Costs.  */
2775+/*---------*/
2776+
2777+#define SLOW_BYTE_ACCESS 1
2778+
2779+#define NO_FUNCTION_CSE
2780+
2781+#define BRANCH_COST(speed_p, predictable_p) 4
2782+
2783+#define MOVE_RATIO(speed) (speed ? 24 : 3)
2784+
2785+/*------------*/
2786+/* Sections.  */
2787+/*------------*/
2788+
2789+#define TEXT_SECTION_ASM_OP             "\t.section\t.text"
2790+#define DATA_SECTION_ASM_OP             "\t.section\t.data"
2791+#define SDATA_SECTION_ASM_OP            "\t.section\t.sdata,\"aw\""
2792+#define BSS_SECTION_ASM_OP              "\t.section\t.bss"
2793+#define SBSS_SECTION_ASM_OP             "\t.section\t.sbss,\"aw\""
2794+
2795+/*-------*/
2796+/* PIC.  */
2797+/*-------*/
2798+
2799+#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? GP_REGNUM : INVALID_REGNUM)
2800+
2801+#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
2802+
2803+#define LEGITIMATE_PIC_OPERAND_P(X)                                    \
2804+       (!(nonpic_symbol_mentioned_p (X)))
2805+
2806+/*-------------*/
2807+/* Assembler.  */
2808+/*-------------*/
2809+
2810+#define ASM_COMMENT_START "#"
2811+
2812+#define ASM_APP_ON "#APP\n"
2813+
2814+#define ASM_APP_OFF "#NO_APP\n"
2815+
2816+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                             \
2817+ do {                                                                  \
2818+       fputc ( '\t', FILE);                                            \
2819+       assemble_name (FILE, LABEL1);                                   \
2820+       fputs ( " = ", FILE);                                           \
2821+       assemble_name (FILE, LABEL2);                                   \
2822+       fputc ( '\n', FILE);                                            \
2823+ } while (0)
2824+
2825+/* Override default implementation in elfos.h to support -G.  */
2826+#undef  ASM_OUTPUT_ALIGNED_LOCAL
2827+#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)              \
2828+do {                                                                   \
2829+  if ((SIZE) <= g_switch_value)                                                \
2830+    switch_to_section (sbss_section);                                  \
2831+  else                                                                 \
2832+    switch_to_section (bss_section);                                   \
2833+  ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");                    \
2834+  if (!flag_inhibit_size_directive)                                    \
2835+    ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE);                      \
2836+  ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));      \
2837+  ASM_OUTPUT_LABEL(FILE, NAME);                                                \
2838+  ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1);                                \
2839+} while (0)
2840+
2841+/* Override default implementation in elfos.h to support -G.  */
2842+#undef  ASM_OUTPUT_ALIGNED_COMMON
2843+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)             \
2844+do                                                                     \
2845+{                                                                      \
2846+  if ((SIZE) <= g_switch_value)                                                \
2847+    {                                                                  \
2848+      switch_to_section (sbss_section);                                        \
2849+      (*targetm.asm_out.globalize_label) (FILE, NAME);                 \
2850+      ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");                        \
2851+      if (!flag_inhibit_size_directive)                                        \
2852+       ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE);                   \
2853+      ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));  \
2854+      ASM_OUTPUT_LABEL(FILE, NAME);                                    \
2855+      ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1);                    \
2856+    }                                                                  \
2857+  else                                                                 \
2858+    {                                                                  \
2859+      switch_to_section (bss_section);                                 \
2860+      fprintf ((FILE), "%s", COMMON_ASM_OP);                           \
2861+      assemble_name ((FILE), (NAME));                                  \
2862+      fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);       \
2863+    }                                                                  \
2864+}                                                                      \
2865+while (0)
2866+
2867+#define ASM_OUTPUT_LABEL(FILE, NAME) \
2868+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2869+
2870+#define ASM_OUTPUT_LABELREF(FILE,NAME) \
2871+  do {                                 \
2872+    const char *xname = (NAME);                \
2873+    if (xname[0] == '@')               \
2874+      xname += 1;                      \
2875+    if (xname[0] == '*')               \
2876+      xname += 1;                      \
2877+    fputs (xname, FILE);               \
2878+  } while (0)
2879+
2880+#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)                          \
2881+  do {                                                                                     \
2882+    assemble_name (STREAM, XSTR (SYMBOL, 0));                          \
2883+  } while (0)
2884+
2885+#define GLOBAL_ASM_OP "\t.global\t"
2886+
2887+#define REGISTER_NAMES                                          \
2888+{                                                        \
2889+ "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",         \
2890+ "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15", \
2891+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2892+ "r24", "r25",  "gp",  "fp",  "sp",  "ra",  "ea",  "ba"}
2893+
2894+#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2895+  (((CHAR) == '&') || ((CHAR) == '@') || ((CHAR) == '*'))
2896+
2897+#define PRINT_OPERAND(FILE, X, CODE)                    \
2898+  lm32_print_operand (FILE, X, CODE)
2899+
2900+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)                              \
2901+  lm32_print_operand_address (FILE, ADDR)
2902+
2903+#ifndef LOCAL_LABEL_PREFIX
2904+#define LOCAL_LABEL_PREFIX     "."
2905+#endif
2906+
2907+#define ASM_OUTPUT_ALIGN(FILE,LOG)                                     \
2908+  do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", (1 << (LOG))); } while (0)
2909+
2910+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)                    \
2911+do {                                                            \
2912+  char label[64];                                               \
2913+  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);              \
2914+  fprintf (FILE, "\n\t.word\t");                                \
2915+  assemble_name (FILE, label);                                  \
2916+  fprintf (FILE, "\n");                                         \
2917+} while (0)
2918+
2919+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)        \
2920+do {                                                            \
2921+  char label[64];                                               \
2922+  fprintf (FILE, "\t.word\t(");                                 \
2923+  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);             \
2924+  assemble_name (FILE, label);                                  \
2925+  fprintf (FILE, "-");                                          \
2926+  ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);                \
2927+  assemble_name (FILE, label);                                  \
2928+  fprintf (FILE, ")\n");                                        \
2929+} while (0)
2930+
2931+/*-------------*/
2932+/* Debugging.  */
2933+/*-------------*/
2934+
2935+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2936+
2937+#define CAN_DEBUG_WITHOUT_FP
2938+     
2939+#define DEFAULT_GDB_EXTENSIONS 1
2940+
2941+/*--------*/
2942+/* Misc.  */
2943+/*--------*/
2944+
2945+#define CASE_VECTOR_MODE Pmode
2946+
2947+#define WORD_REGISTER_OPERATIONS
2948+
2949+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2950+
2951+#define SHORT_IMMEDIATES_SIGN_EXTEND
2952+
2953+#define MOVE_MAX        UNITS_PER_WORD
2954+#define MAX_MOVE_MAX    4
2955+
2956+#define SHIFT_COUNT_TRUNCATED 1
2957+
2958+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2959+
2960+#define Pmode SImode
2961+
2962+#define FUNCTION_MODE SImode
2963+
2964+#ifndef NO_IMPLICIT_EXTERN_C
2965+#define NO_IMPLICIT_EXTERN_C
2966+#endif
2967+
2968+#define STORE_FLAG_VALUE 1
2969diff -Naur gcc-4.4.6.orig/gcc/config/lm32/lm32.md gcc-4.4.6/gcc/config/lm32/lm32.md
2970--- gcc-4.4.6.orig/gcc/config/lm32/lm32.md      1970-01-01 01:00:00.000000000 +0100
2971+++ gcc-4.4.6/gcc/config/lm32/lm32.md   2011-04-20 17:27:23.065805908 +0200
2972@@ -0,0 +1,1233 @@
2973+;; Machine description of the Lattice Mico32 architecture for GNU C compiler.
2974+;; Contributed by Jon Beniston <jon@beniston.com>
2975+
2976+;; This file is part of GCC.
2977+
2978+;; GCC is free software; you can redistribute it and/or modify it
2979+;; under the terms of the GNU General Public License as published
2980+;; by the Free Software Foundation; either version 3, or (at your
2981+;; option) any later version.
2982+
2983+;; GCC is distributed in the hope that it will be useful, but WITHOUT
2984+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2985+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
2986+;; License for more details.
2987+
2988+;; You should have received a copy of the GNU General Public License
2989+;; along with GCC; see the file COPYING3.  If not see
2990+;; <http://www.gnu.org/licenses/>. 
2991+
2992+;; Include predicate definitions
2993+(include "predicates.md")
2994+
2995+;; Register numbers
2996+(define_constants
2997+  [(RA_REGNUM           29)            ; return address register.
2998+  ]
2999+)
3000+
3001+;; LM32 specific volatile operations
3002+(define_constants
3003+  [(UNSPECV_BLOCKAGE    1)]     ; use to prevent scheduler from optimising accross bounaries
3004+)
3005+
3006+;; LM32 specific operations
3007+(define_constants
3008+  [(UNSPEC_GOT          2)
3009+   (UNSPEC_GOTOFF_HI16  3)
3010+   (UNSPEC_GOTOFF_LO16  4)]     
3011+)
3012+
3013+;; ---------------------------------
3014+;;      instruction types
3015+;; ---------------------------------
3016+
3017+(define_attr "type"
3018+  "unknown,load,store,arith,compare,shift,multiply,divide,call,icall,ubranch,uibranch,cbranch"
3019+  (const_string "unknown"))
3020
3021+;; ---------------------------------
3022+;;      instruction lengths
3023+;; ---------------------------------
3024
3025+; All instructions are 4 bytes
3026+; Except for branches that are out of range, and have to be implemented
3027+; as two instructions
3028+(define_attr "length" ""
3029+        (cond [
3030+                (eq_attr "type" "cbranch")
3031+                (if_then_else
3032+                        (lt (abs (minus (match_dup 2) (pc)))
3033+                                (const_int 32768)
3034+                        )
3035+                        (const_int 4)
3036+                        (const_int 8)               
3037+                )
3038+              ]
3039+        (const_int 4))
3040+)
3041+                   
3042+;; ---------------------------------
3043+;;           scheduling
3044+;; ---------------------------------
3045+
3046+(define_automaton "lm32")
3047+
3048+(define_cpu_unit "x" "lm32")
3049+(define_cpu_unit "m" "lm32")
3050+(define_cpu_unit "w" "lm32")
3051+
3052+(define_insn_reservation "singlecycle" 1
3053+  (eq_attr "type" "store,arith,call,icall,ubranch,uibranch,cbranch")
3054+ "x")
3055+
3056+(define_insn_reservation "twocycle" 2
3057+  (eq_attr "type" "compare,shift,divide")
3058+ "x,m")
3059+
3060+(define_insn_reservation "threecycle" 3
3061+  (eq_attr "type" "load,multiply")
3062+ "x,m,w")
3063+
3064+;; ---------------------------------
3065+;;               mov
3066+;; ---------------------------------
3067+
3068+(define_expand "movqi"
3069+  [(set (match_operand:QI 0 "general_operand" "")
3070+        (match_operand:QI 1 "general_operand" ""))]
3071+  ""
3072+  "
3073+{
3074+  if (can_create_pseudo_p ())
3075+    {
3076+      if (GET_CODE (operand0) == MEM)
3077+        {
3078+          /* Source operand for store must be in a register */
3079+          operands[1] = force_reg (QImode, operands[1]);
3080+        }
3081+    }
3082+  if (   GET_CODE (operands[1]) == CONST_INT
3083+      && GET_CODE (operands[0]) == REG)
3084+    {
3085+      operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
3086+      emit_insn (gen_movsi (operands[0], operands[1]));
3087+      DONE;
3088+    }
3089+}")
3090+
3091+(define_expand "movhi"
3092+  [(set (match_operand:HI 0 "general_operand" "")
3093+        (match_operand:HI 1 "general_operand" ""))]
3094+  ""
3095+  "
3096+{
3097+  if (can_create_pseudo_p ())
3098+    {
3099+      if (GET_CODE (operands[0]) == MEM)
3100+        {
3101+          /* Source operand for store must be in a register */
3102+          operands[1] = force_reg (HImode, operands[1]);
3103+        }
3104+    }
3105+  if (GET_CODE (operands[1]) == CONST_INT)
3106+    {
3107+      operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);         
3108+      if (MEDIUM_INT (INTVAL (operands[1])))     
3109+        emit_insn (gen_movsi_kimm (operands[0], operands[1]));
3110+      else if (MEDIUM_UINT (INTVAL (operands[1])))   
3111+        emit_insn (gen_movsi_limm (operands[0], operands[1]));
3112+      else
3113+        {
3114+          emit_insn (gen_movsi_imm_hi (operands[0], GEN_INT (INTVAL (operands[1]))));
3115+          emit_insn (gen_movsi_imm_lo (operands[0], operands[0], GEN_INT (INTVAL (operands[1]))));
3116+        }
3117+      DONE;
3118+    }
3119+}")
3120+
3121+(define_expand "movsi"
3122+  [(set (match_operand:SI 0 "general_operand" "")
3123+        (match_operand:SI 1 "general_operand" ""))]
3124+  ""
3125+  "
3126+{
3127+  if (can_create_pseudo_p ())
3128+    {
3129+      if (GET_CODE (operands[0]) == MEM
3130+         || (GET_CODE (operands[0]) == SUBREG
3131+             && GET_CODE (SUBREG_REG (operands[0])) == MEM))
3132+        {
3133+          /* Source operand for store must be in a register */
3134+          operands[1] = force_reg (SImode, operands[1]);
3135+        }
3136+    }
3137+
3138+  if (flag_pic && symbolic_operand (operands[1], SImode))
3139+    {
3140+      if (GET_CODE (operands[1]) == LABEL_REF
3141+          || (GET_CODE (operands[1]) == SYMBOL_REF
3142+              && SYMBOL_REF_LOCAL_P (operands[1])
3143+              && !SYMBOL_REF_WEAK (operands[1])))
3144+        {
3145+          emit_insn (gen_movsi_gotoff_hi16 (operands[0], operands[1]));
3146+          emit_insn (gen_addsi3 (operands[0], operands[0], pic_offset_table_rtx));
3147+          emit_insn (gen_movsi_gotoff_lo16 (operands[0], operands[0], operands[1]));
3148+        }
3149+      else
3150+        {
3151+          emit_insn (gen_movsi_got (operands[0], operands[1]));
3152+        }
3153+      crtl->uses_pic_offset_table = 1;
3154+      DONE;
3155+    }
3156+  else if (flag_pic && GET_CODE (operands[1]) == CONST)
3157+    {
3158+      rtx op = XEXP (operands[1], 0);
3159+      if (GET_CODE (op) == PLUS)
3160+        {
3161+          rtx arg0 = XEXP (op, 0);
3162+          rtx arg1 = XEXP (op, 1);
3163+          if (GET_CODE (arg0) == LABEL_REF
3164+              || (GET_CODE (arg0) == SYMBOL_REF
3165+                  && SYMBOL_REF_LOCAL_P (arg0)
3166+                  && !SYMBOL_REF_WEAK (arg0)))
3167+            {
3168+              emit_insn (gen_movsi_gotoff_hi16 (operands[0], arg0));
3169+              emit_insn (gen_addsi3 (operands[0], operands[0], pic_offset_table_rtx));
3170+              emit_insn (gen_movsi_gotoff_lo16 (operands[0], operands[0], arg0));
3171+            }
3172+          else
3173+            {
3174+              emit_insn (gen_movsi_got (operands[0], arg0));
3175+            }
3176+          emit_insn (gen_addsi3 (operands[0], operands[0], arg1));
3177+          crtl->uses_pic_offset_table = 1;
3178+          DONE;
3179+        }     
3180+    }
3181+  else if (!flag_pic && (   GET_CODE (operands[1]) == SYMBOL_REF
3182+                         && SYMBOL_REF_SMALL_P (operands[1])
3183+                        )
3184+          )
3185+    {
3186+      emit_insn (gen_movsi_reloc_gprel (operands[0], operands[1]));
3187+      DONE;
3188+    }
3189+  else if (!flag_pic && (   GET_CODE (operands[1]) == LABEL_REF
3190+                         || GET_CODE (operands[1]) == SYMBOL_REF
3191+                         || GET_CODE (operands[1]) == CONST                         
3192+                        )
3193+          )
3194+    {
3195+      emit_insn (gen_movsi_reloc_hi (operands[0], operands[1]));
3196+      emit_insn (gen_movsi_reloc_lo (operands[0], operands[0], operands[1]));
3197+      DONE;
3198+    }
3199+  else if (GET_CODE (operands[1]) == CONST_INT)
3200+    {
3201+      if (MEDIUM_INT (INTVAL (operands[1])))     
3202+        emit_insn (gen_movsi_kimm (operands[0], operands[1]));
3203+      else if (MEDIUM_UINT (INTVAL (operands[1])))   
3204+        emit_insn (gen_movsi_limm (operands[0], operands[1]));
3205+      else
3206+        {
3207+          emit_insn (gen_movsi_imm_hi (operands[0], GEN_INT (INTVAL (operands[1]))));
3208+          emit_insn (gen_movsi_imm_lo (operands[0], operands[0], GEN_INT (INTVAL (operands[1]))));
3209+        }
3210+      DONE;
3211+    }   
3212+}")
3213+
3214+;;(define_expand "movmemsi"
3215+;;  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
3216+;;                (match_operand:BLK 1 "general_operand" ""))
3217+;;           (use (match_operand:SI 2 "" ""))
3218+;;           (use (match_operand:SI 3 "const_int_operand" ""))])]
3219+;;  ""
3220+;;{
3221+;;  if (!lm32_expand_block_move (operands))
3222+;;    FAIL;
3223+;;  DONE;
3224+;;})
3225+
3226+;; ---------------------------------
3227+;;        load/stores/moves
3228+;; ---------------------------------
3229+
3230+(define_insn "movsi_kimm"
3231+  [(set (match_operand:SI 0 "register_operand" "=r")
3232+        (match_operand:SI 1 "constant_K_operand" "K"))]
3233+  ""
3234+  "addi     %0, r0, %1"
3235+  [(set_attr "type" "arith")]
3236+)
3237+
3238+(define_insn "movsi_limm"
3239+  [(set (match_operand:SI 0 "register_operand" "=r")
3240+        (match_operand:SI 1 "constant_L_operand" "L"))]
3241+  ""
3242+  "ori      %0, r0, %1"
3243+  [(set_attr "type" "arith")]
3244+)
3245+
3246+(define_insn "movsi_imm_hi"
3247+  [(set (match_operand:SI 0 "register_operand" "=r")
3248+        (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
3249+  ""
3250+  "orhi     %0, r0, hi(%1)"
3251+  [(set_attr "type" "arith")]
3252+)
3253+
3254+(define_insn "movsi_imm_lo"
3255+  [(set (match_operand:SI 0 "register_operand" "=r")
3256+        (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
3257+                   (match_operand:SI 2 "immediate_operand" "i")))]
3258+  ""
3259+  "ori      %0, %0, lo(%2)"
3260+  [(set_attr "type" "arith")]
3261+)
3262+
3263+(define_insn "movsi_reloc_gprel"
3264+  [(set (match_operand:SI 0 "register_operand" "=r")
3265+        (match_operand:SI 1 "reloc_operand" "i"))]
3266+  "GET_CODE (operands[1]) == SYMBOL_REF && SYMBOL_REF_SMALL_P (operands[1])"
3267+  "mva      %0, gp(%1)"
3268+  [(set_attr "type" "arith")]
3269+)
3270+
3271+(define_insn "movsi_got"
3272+  [(set (match_operand:SI 0 "register_operand" "=r")
3273+        (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOT))]
3274+  "flag_pic"
3275+  "lw       %0, (gp+got(%1))"
3276+  [(set_attr "type" "load")]
3277+)
3278+
3279+(define_insn "movsi_gotoff_hi16"
3280+  [(set (match_operand:SI 0 "register_operand" "=r")
3281+        (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF_HI16))]
3282+  "flag_pic"
3283+  "orhi     %0, r0, gotoffhi16(%1)"
3284+  [(set_attr "type" "load")]
3285+)
3286+
3287+(define_insn "movsi_gotoff_lo16"
3288+  [(set (match_operand:SI 0 "register_operand" "=r")
3289+        (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "0")
3290+                             (match_operand 2 "" ""))] UNSPEC_GOTOFF_LO16))]       
3291+  "flag_pic"
3292+  "addi     %0, %1, gotofflo16(%2)"
3293+  [(set_attr "type" "arith")]
3294+)
3295
3296+(define_insn "movsi_reloc_hi"
3297+  [(set (match_operand:SI 0 "register_operand" "=r")
3298+        (high:SI (match_operand:SI 1 "reloc_operand" "i")))]
3299+  "!flag_pic"
3300+  "orhi     %0, r0, hi(%1)"
3301+  [(set_attr "type" "arith")]
3302+)
3303+
3304+(define_insn "movsi_reloc_lo"
3305+  [(set (match_operand:SI 0 "register_operand" "=r")
3306+        (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
3307+                   (match_operand:SI 2 "reloc_operand" "i")))]
3308+  "!flag_pic"
3309+  "ori      %0, %0, lo(%2)"
3310+  [(set_attr "type" "arith")]
3311+)
3312+
3313+(define_insn "*movqi_insn"
3314+  [(set (match_operand:QI 0 "register_or_memory_operand" "=r,r,m")
3315+        (match_operand:QI 1 "register_or_memory_operand" "m,r,r"))]
3316+  ""
3317+  "@
3318+   lbu      %0, %1
3319+   or       %0, %1, r0
3320+   sb       %0, %1"
3321+  [(set_attr "type" "load,arith,store")]   
3322+)
3323+   
3324+(define_insn "*movhi_insn"
3325+  [(set (match_operand:HI 0 "register_or_memory_operand" "=r,r,m")
3326+        (match_operand:HI 1 "register_or_memory_operand" "m,r,r"))]
3327+  ""
3328+  "@
3329+   lhu      %0, %1
3330+   or       %0, %1, r0
3331+   sh       %0, %1"
3332+  [(set_attr "type" "load,arith,store")]   
3333+)
3334+
3335+(define_insn "*movsi_insn"
3336+  [(set (match_operand:SI 0 "register_or_memory_operand" "=r,r,m")
3337+        (match_operand:SI 1 "register_or_memory_operand" "m,r,r"))]
3338+  ""
3339+  "@
3340+   lw       %0, %1
3341+   or       %0, %1, r0
3342+   sw       %0, %1"
3343+  [(set_attr "type" "load,arith,store")]   
3344+)
3345+
3346+;; ---------------------------------
3347+;;      sign and zero extension
3348+;; ---------------------------------
3349+
3350+(define_insn "*extendqihi2"
3351+  [(set (match_operand:HI 0 "register_operand" "=r,r")
3352+        (sign_extend:HI (match_operand:QI 1 "register_or_memory_operand" "m,r")))]
3353+  "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
3354+  "@
3355+   lb       %0, %1
3356+   sextb    %0, %1"
3357+  [(set_attr "type" "load,arith")]
3358+)
3359+
3360+(define_insn "zero_extendqihi2"
3361+  [(set (match_operand:HI 0 "register_operand" "=r,r")
3362+        (zero_extend:HI (match_operand:QI 1 "register_or_memory_operand" "m,r")))]
3363+  ""
3364+  "@
3365+   lbu      %0, %1
3366+   andi     %0, %1, 0xff"
3367+  [(set_attr "type" "load,arith")] 
3368+)
3369+
3370+(define_insn "*extendqisi2"
3371+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3372+        (sign_extend:SI (match_operand:QI 1 "register_or_memory_operand" "m,r")))]
3373+  "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
3374+  "@
3375+   lb       %0, %1
3376+   sextb    %0, %1"
3377+  [(set_attr "type" "load,arith")]
3378+)
3379+
3380+(define_insn "zero_extendqisi2"
3381+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3382+           (zero_extend:SI (match_operand:QI 1 "register_or_memory_operand" "m,r")))]
3383+  ""
3384+  "@
3385+   lbu      %0, %1
3386+   andi     %0, %1, 0xff"
3387+  [(set_attr "type" "load,arith")] 
3388+)
3389+
3390+(define_insn "*extendhisi2"
3391+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3392+        (sign_extend:SI (match_operand:HI 1 "register_or_memory_operand" "m,r")))]
3393+  "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
3394+  "@
3395+   lh       %0, %1
3396+   sexth    %0, %1"
3397+  [(set_attr "type" "load,arith")]
3398+)
3399+
3400+(define_insn "zero_extendhisi2"
3401+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3402+        (zero_extend:SI (match_operand:HI 1 "register_or_memory_operand" "m,r")))]
3403+  ""
3404+  "@
3405+   lhu      %0, %1
3406+   andi     %0, %1, 0xffff"
3407+  [(set_attr "type" "load,arith")] 
3408+)
3409+
3410+;; ---------------------------------
3411+;;             compare
3412+;; ---------------------------------
3413+
3414+(define_expand "cmpsi"
3415+  [(set (cc0)
3416+   (compare:CC (match_operand:SI 0 "register_operand" "")
3417+               (match_operand:SI 1 "register_or_K_operand" "")))]
3418+  ""
3419+  "
3420+{
3421+  lm32_compare_op0 = operands[0];
3422+  lm32_compare_op1 = operands[1];
3423+  DONE;
3424+}")
3425+
3426+
3427+(define_expand "tstsi"
3428+  [(set (cc0)
3429+   (match_operand:SI 0 "register_operand" ""))]
3430+  ""
3431+  "
3432+{
3433+  lm32_compare_op0 = operands[0];
3434+  lm32_compare_op1 = const0_rtx;
3435+  DONE;
3436+}")
3437+
3438+(define_expand "seq"
3439+  [(set (match_operand:SI 0 "register_operand" "=r")
3440+       (eq:SI (match_dup 1)
3441+              (match_dup 2)))]
3442+  ""
3443+{
3444+  operands[1] = lm32_compare_op0;
3445+  operands[2] = lm32_compare_op1;
3446+  gen_int_relational (EQ, operands[0], operands[1], operands[2], NULL_RTX);
3447+  DONE;
3448+})
3449+
3450+(define_insn "*seq"
3451+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3452+        (eq:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3453+               (match_operand:SI 2 "register_or_K_operand" "r,K")))]
3454+  ""
3455+  "@
3456+   cmpe     %0, %z1, %2
3457+   cmpei    %0, %z1, %2"
3458+  [(set_attr "type" "compare")]
3459+)
3460+
3461+(define_expand "sne"
3462+  [(set (match_operand:SI 0 "register_operand" "=r")
3463+       (ne:SI (match_dup 1)
3464+              (match_dup 2)))]
3465+  ""
3466+{
3467+  operands[1] = lm32_compare_op0;
3468+  operands[2] = lm32_compare_op1;
3469+  gen_int_relational (NE, operands[0], operands[1], operands[2], NULL_RTX);
3470+  DONE;
3471+})
3472+
3473+(define_insn "*sne"
3474+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3475+        (ne:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3476+               (match_operand:SI 2 "register_or_K_operand" "r,K")))]
3477+  ""
3478+  "@
3479+   cmpne    %0, %z1, %2
3480+   cmpnei   %0, %z1, %2"
3481+  [(set_attr "type" "compare")]
3482+)
3483+
3484+(define_expand "sgt"
3485+  [(set (match_operand:SI 0 "register_operand" "=r")
3486+       (gt:SI (match_dup 1)
3487+              (match_dup 2)))]
3488+  ""
3489+{
3490+  operands[1] = lm32_compare_op0;
3491+  operands[2] = lm32_compare_op1;
3492+  gen_int_relational (GT, operands[0], operands[1], operands[2], NULL_RTX);
3493+  DONE;
3494+})
3495+
3496+(define_insn "*sgt"
3497+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3498+        (gt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3499+               (match_operand:SI 2 "register_or_K_operand" "r,K")))]
3500+  ""
3501+  "@
3502+   cmpg     %0, %z1, %2
3503+   cmpgi    %0, %z1, %2"
3504+  [(set_attr "type" "compare")]
3505+)
3506+
3507+(define_expand "slt"
3508+  [(set (match_operand:SI 0 "register_operand" "=r")
3509+       (lt:SI (match_dup 1)
3510+              (match_dup 2)))]
3511+  ""
3512+{
3513+  operands[1] = lm32_compare_op0;
3514+  operands[2] = lm32_compare_op1;
3515+  gen_int_relational (LT, operands[0], operands[1], operands[2], NULL_RTX);
3516+  DONE;
3517+})
3518+
3519+(define_expand "sge"
3520+  [(set (match_operand:SI 0 "register_operand" "=r")
3521+       (ge:SI (match_dup 1)
3522+              (match_dup 2)))]
3523+  ""
3524+{
3525+  operands[1] = lm32_compare_op0;
3526+  operands[2] = lm32_compare_op1;
3527+  gen_int_relational (GE, operands[0], operands[1], operands[2], NULL_RTX);
3528+  DONE;
3529+})
3530+
3531+(define_insn "*sge"
3532+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3533+        (ge:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3534+               (match_operand:SI 2 "register_or_K_operand" "r,K")))]
3535+  ""
3536+  "@
3537+   cmpge    %0, %z1, %2
3538+   cmpgei   %0, %z1, %2"
3539+  [(set_attr "type" "compare")]
3540+)
3541+
3542+(define_expand "sle"
3543+  [(set (match_operand:SI 0 "register_operand" "=r")
3544+       (le:SI (match_dup 1)
3545+              (match_dup 2)))]
3546+  ""
3547+{
3548+  operands[1] = lm32_compare_op0;
3549+  operands[2] = lm32_compare_op1;
3550+  gen_int_relational (LE, operands[0], operands[1], operands[2], NULL_RTX);
3551+  DONE;
3552+})
3553+
3554+(define_expand "sgtu"
3555+  [(set (match_operand:SI 0 "register_operand" "=r")
3556+       (gtu:SI (match_dup 1)
3557+               (match_dup 2)))]
3558+  ""
3559+{
3560+  operands[1] = lm32_compare_op0;
3561+  operands[2] = lm32_compare_op1;
3562+  gen_int_relational (GTU, operands[0], operands[1], operands[2], NULL_RTX);
3563+  DONE;
3564+})
3565+
3566+(define_insn "*sgtu"
3567+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3568+        (gtu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3569+                (match_operand:SI 2 "register_or_K_operand" "r,L")))]
3570+  ""
3571+  "@
3572+   cmpgu    %0, %z1, %2
3573+   cmpgui   %0, %z1, %2"
3574+  [(set_attr "type" "compare")]
3575+)
3576+
3577+(define_expand "sltu"
3578+  [(set (match_operand:SI 0 "register_operand" "=r")
3579+       (ltu:SI (match_dup 1)
3580+               (match_dup 2)))]
3581+  ""
3582+{
3583+  operands[1] = lm32_compare_op0;
3584+  operands[2] = lm32_compare_op1;
3585+  gen_int_relational (LTU, operands[0], operands[1], operands[2], NULL_RTX);
3586+  DONE;
3587+})
3588+
3589+(define_expand "sgeu"
3590+  [(set (match_operand:SI 0 "register_operand" "=r")
3591+       (geu:SI (match_dup 1)
3592+               (match_dup 2)))]
3593+  ""
3594+{
3595+  operands[1] = lm32_compare_op0;
3596+  operands[2] = lm32_compare_op1;
3597+  gen_int_relational (GEU, operands[0], operands[1], operands[2], NULL_RTX);
3598+  DONE;
3599+})
3600+
3601+(define_insn "*sgeu"
3602+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3603+        (geu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3604+                (match_operand:SI 2 "register_or_K_operand" "r,L")))]
3605+  ""
3606+  "@
3607+   cmpgeu   %0, %z1, %2
3608+   cmpgeui  %0, %z1, %2"
3609+  [(set_attr "type" "compare")]
3610+)
3611+
3612+(define_expand "sleu"
3613+  [(set (match_operand:SI 0 "register_operand" "=r")
3614+       (leu:SI (match_dup 1)
3615+               (match_dup 2)))]
3616+  ""
3617+{
3618+  operands[1] = lm32_compare_op0;
3619+  operands[2] = lm32_compare_op1;
3620+  gen_int_relational (LEU, operands[0], operands[1], operands[2], NULL_RTX);
3621+  DONE;
3622+})
3623+
3624+;; ---------------------------------
3625+;;       unconditional branch
3626+;; ---------------------------------
3627+
3628+(define_insn "jump"
3629+  [(set (pc) (label_ref (match_operand 0 "" "")))]
3630+  ""
3631+  "bi       %0"
3632+  [(set_attr "type" "ubranch")]
3633+)
3634+
3635+(define_expand "indirect_jump"
3636+  [(set (pc) (match_operand 0 "register_operand" ""))]
3637+  ""
3638+  "
3639+{
3640+  emit_jump_insn (gen_indirect_jumpsi (operands[0]));
3641+  DONE;
3642+}")
3643+
3644+(define_insn "indirect_jumpsi"
3645+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3646+  ""
3647+  "b        %0"
3648+  [(set_attr "type" "uibranch")]
3649+)
3650+
3651+;; ---------------------------------
3652+;;        conditional branch
3653+;; ---------------------------------
3654+
3655+(define_expand "beq"
3656+  [(set (pc)
3657+   (if_then_else (eq:CC (cc0)
3658+                        (const_int 0))
3659+                 (label_ref (match_operand 0 "" ""))
3660+                 (pc)))]
3661+  ""
3662+  "
3663+{   
3664+  gen_int_relational (EQ, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3665+  DONE;
3666+}")
3667+
3668+(define_expand "bne"
3669+  [(set (pc)
3670+   (if_then_else (ne:CC (cc0)
3671+                        (const_int 0))
3672+                 (label_ref (match_operand 0 "" ""))
3673+                 (pc)))]
3674+  ""
3675+  "
3676+{
3677+  gen_int_relational (NE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3678+  DONE;
3679+}")
3680+
3681+(define_expand "bgt"
3682+  [(set (pc)
3683+   (if_then_else (gt:CC (cc0)
3684+                        (const_int 0))
3685+                 (label_ref (match_operand 0 "" ""))
3686+                 (pc)))]
3687+  ""
3688+  "
3689+{
3690+  gen_int_relational (GT, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3691+  DONE;
3692+}")
3693+
3694+(define_expand "bge"
3695+  [(set (pc)
3696+   (if_then_else (ge:CC (cc0)
3697+                        (const_int 0))
3698+                 (label_ref (match_operand 0 "" ""))
3699+                 (pc)))]
3700+  ""
3701+  "
3702+{
3703+  gen_int_relational (GE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3704+  DONE;
3705+}")
3706+
3707+(define_expand "ble"
3708+  [(set (pc)
3709+   (if_then_else (le:CC (cc0)
3710+                        (const_int 0))
3711+                 (label_ref (match_operand 0 "" ""))
3712+                 (pc)))]
3713+  ""
3714+  "
3715+{
3716+  gen_int_relational (LE, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3717+  DONE;
3718+}")
3719+
3720+(define_expand "blt"
3721+  [(set (pc)
3722+   (if_then_else (lt:CC (cc0)
3723+                        (const_int 0))
3724+                 (label_ref (match_operand 0 "" ""))
3725+                 (pc)))]
3726+  ""
3727+  "
3728+{
3729+  gen_int_relational (LT, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3730+  DONE;
3731+}")
3732+
3733+(define_expand "bgtu"
3734+  [(set (pc)
3735+   (if_then_else (gtu:CC (cc0)
3736+                         (const_int 0))
3737+                 (label_ref (match_operand 0 "" ""))
3738+                 (pc)))]
3739+  ""
3740+  "
3741+{
3742+  gen_int_relational (GTU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3743+  DONE;
3744+}")
3745+
3746+(define_expand "bgeu"
3747+  [(set (pc)
3748+   (if_then_else (geu:CC (cc0)
3749+                         (const_int 0))
3750+                 (label_ref (match_operand 0 "" ""))
3751+                 (pc)))]
3752+  ""
3753+  "
3754+{
3755+  gen_int_relational (GEU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3756+  DONE;
3757+}")
3758+
3759+(define_expand "bleu"
3760+  [(set (pc)
3761+   (if_then_else (leu:CC (cc0)
3762+                         (const_int 0))
3763+                 (label_ref (match_operand 0 "" ""))
3764+                 (pc)))]
3765+  ""
3766+  "
3767+{
3768+  gen_int_relational (LEU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3769+  DONE;
3770+}")
3771+
3772+(define_expand "bltu"
3773+  [(set (pc)
3774+   (if_then_else (ltu:CC (cc0)
3775+                         (const_int 0))
3776+                 (label_ref (match_operand 0 "" ""))
3777+                 (pc)))]
3778+  ""
3779+  "
3780+{
3781+  gen_int_relational (LTU, NULL_RTX, lm32_compare_op0, lm32_compare_op1, operands[0]);
3782+  DONE;
3783+}")
3784+
3785+(define_insn "*beq"
3786+  [(set (pc)
3787+        (if_then_else (eq:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3788+                             (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3789+                      (label_ref (match_operand 2 "" ""))
3790+                      (pc)))]
3791+  ""
3792+{
3793+  return get_attr_length (insn) == 4
3794+        ? "be     %z0,%z1,%2"
3795+        : "bne    %z0,%z1,8\n\tbi     %2";
3796+} 
3797+  [(set_attr "type" "cbranch")])
3798+
3799+(define_insn "*bne"
3800+  [(set (pc)
3801+        (if_then_else (ne:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3802+                             (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3803+                      (label_ref (match_operand 2 "" ""))
3804+                      (pc)))]
3805+  ""
3806+{
3807+  return get_attr_length (insn) == 4
3808+        ? "bne    %z0,%z1,%2"
3809+        : "be     %z0,%z1,8\n\tbi     %2";
3810+} 
3811+  [(set_attr "type" "cbranch")])
3812+
3813+(define_insn "*bgt"
3814+  [(set (pc)
3815+        (if_then_else (gt:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3816+                             (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3817+                      (label_ref (match_operand 2 "" ""))
3818+                      (pc)))]
3819+  ""
3820+{
3821+  return get_attr_length (insn) == 4
3822+        ? "bg     %z0,%z1,%2"
3823+        : "bge    %z1,%z0,8\n\tbi     %2";
3824+} 
3825+  [(set_attr "type" "cbranch")])
3826+
3827+(define_insn "*bge"
3828+  [(set (pc)
3829+        (if_then_else (ge:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3830+                             (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3831+                      (label_ref (match_operand 2 "" ""))
3832+                      (pc)))]
3833+  ""
3834+{
3835+  return get_attr_length (insn) == 4
3836+        ? "bge    %z0,%z1,%2"
3837+        : "bg     %z1,%z0,8\n\tbi     %2";
3838+} 
3839+  [(set_attr "type" "cbranch")])
3840+
3841+(define_insn "*bgtu"
3842+  [(set (pc)
3843+        (if_then_else (gtu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3844+                              (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3845+                      (label_ref (match_operand 2 "" ""))
3846+                      (pc)))]
3847+  ""
3848+{
3849+  return get_attr_length (insn) == 4
3850+        ? "bgu    %z0,%z1,%2"
3851+        : "bgeu   %z1,%z0,8\n\tbi     %2";
3852+} 
3853+  [(set_attr "type" "cbranch")])
3854+
3855+(define_insn "*bgeu"
3856+  [(set (pc)
3857+        (if_then_else (geu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
3858+                              (match_operand:SI 1 "register_or_zero_operand" "rJ"))
3859+                      (label_ref (match_operand 2 "" ""))
3860+                      (pc)))]
3861+  ""
3862+{
3863+  return get_attr_length (insn) == 4
3864+        ? "bgeu   %z0,%z1,%2"
3865+        : "bgu    %z1,%z0,8\n\tbi     %2";
3866+} 
3867+  [(set_attr "type" "cbranch")])
3868+
3869+;; ---------------------------------
3870+;;               call
3871+;; ---------------------------------
3872+
3873+(define_expand "call"
3874+  [(parallel [(call (match_operand 0 "memory_operand" "m")
3875+                    (match_operand 1 "" ""))
3876+              (clobber (reg:SI RA_REGNUM))
3877+             ])]
3878+  ""
3879+  "
3880+{
3881+  rtx addr = XEXP (operands[0], 0);
3882+  if (!CONSTANT_ADDRESS_P (addr))
3883+    {
3884+      emit_call_insn (gen_call_via_regsi (addr, operands[1]));
3885+      DONE;
3886+    }
3887+}")
3888+
3889+(define_insn "call_via_regsi"
3890+  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
3891+         (match_operand 1 "" ""))
3892+   (clobber (reg:SI RA_REGNUM))]
3893+  ""
3894+  "call     %0"
3895+  [(set_attr "type" "icall")] 
3896+)
3897+
3898+(define_insn "*call_via_labelsi"
3899+  [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "X"))
3900+         (match_operand 1 "" ""))
3901+   (clobber (reg:SI RA_REGNUM))]
3902+  ""
3903+  "calli    %0"
3904+  [(set_attr "type" "call")] 
3905+)
3906+
3907+(define_expand "call_value"
3908+  [(parallel [(set (match_operand 0 "register_operand" "=r")
3909+                   (call (match_operand 1 "memory_operand" "m")
3910+                         (match_operand 2 "" "")))
3911+              (clobber (reg:SI RA_REGNUM))
3912+             ])]
3913+  ""
3914+  "
3915+{
3916+  rtx addr = XEXP (operands[1], 0);
3917+  if (!CONSTANT_ADDRESS_P (addr))
3918+    {
3919+      emit_call_insn (gen_call_value_via_regsi (operands[0], addr, operands[2]));
3920+      DONE;
3921+    }
3922+}")
3923+
3924+(define_insn "call_value_via_regsi"
3925+  [(set (match_operand 0 "register_operand" "=r")
3926+        (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
3927+              (match_operand 2 "" "")))
3928+   (clobber (reg:SI RA_REGNUM))]
3929+  ""
3930+  "call      %1"
3931+  [(set_attr "type" "icall")] 
3932+)
3933+
3934+(define_insn "*call_value_via_labelsi"
3935+  [(set (match_operand 0 "register_operand" "=r")
3936+        (call (mem:SI (match_operand:SI 1 "symbolic_operand" "X"))
3937+              (match_operand 2 "" "")))
3938+   (clobber (reg:SI RA_REGNUM))]
3939+  ""
3940+  "calli    %1"
3941+  [(set_attr "type" "call")] 
3942+)
3943+
3944+(define_insn "return_internalsi"
3945+  [(use (match_operand:SI 0 "register_operand" "r"))
3946+   (return)]
3947+  ""
3948+  "b        %0"
3949+  [(set_attr "type" "uibranch")] 
3950+)
3951+
3952+(define_insn "return"
3953+  [(return)]
3954+  "lm32_can_use_return ()"
3955+  "ret"
3956+  [(set_attr "type" "uibranch")] 
3957+)
3958+
3959+;; ---------------------------------
3960+;;       switch/case statements
3961+;; ---------------------------------
3962
3963+(define_expand "tablejump"
3964+  [(set (pc) (match_operand 0 "register_operand" ""))
3965+   (use (label_ref (match_operand 1 "" "")))]
3966+  ""
3967+  "
3968+{
3969+  rtx target = operands[0];
3970+  if (flag_pic)
3971+    {
3972+      /* For PIC, the table entry is relative to the start of the table.  */
3973+      rtx label = gen_reg_rtx (SImode);
3974+      target = gen_reg_rtx (SImode);
3975+      emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
3976+      emit_insn (gen_addsi3 (target, operands[0], label));
3977+    }
3978+  emit_jump_insn (gen_tablejumpsi (target, operands[1]));
3979+  DONE;
3980+}")
3981+
3982+(define_insn "tablejumpsi"
3983+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
3984+   (use (label_ref (match_operand 1 "" "")))]
3985+  ""
3986+  "b        %0"
3987+  [(set_attr "type" "ubranch")] 
3988+)
3989+
3990+;; ---------------------------------
3991+;;            arithmetic
3992+;; ---------------------------------
3993+
3994+(define_insn "addsi3"
3995+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3996+        (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
3997+                 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
3998+  ""
3999+  "@
4000+   add      %0, %z1, %2
4001+   addi     %0, %z1, %2"
4002+  [(set_attr "type" "arith")] 
4003+)
4004+
4005+(define_insn "subsi3"
4006+  [(set (match_operand:SI 0 "register_operand" "=r")
4007+        (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4008+                  (match_operand:SI 2 "register_or_zero_operand" "rJ")))]
4009+  ""
4010+  "sub      %0, %z1, %z2"
4011+  [(set_attr "type" "arith")] 
4012+)
4013+
4014+(define_insn "mulsi3"
4015+  [(set (match_operand:SI 0 "register_operand" "=r,r")
4016+        (mult:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
4017+                 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
4018+  "TARGET_MULTIPLY_ENABLED"
4019+  "@
4020+   mul      %0, %z1, %2
4021+   muli     %0, %z1, %2"
4022+  [(set_attr "type" "multiply")]
4023+)
4024+
4025+(define_insn "udivsi3"
4026+  [(set (match_operand:SI 0 "register_operand" "=r")
4027+        (udiv:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4028+                 (match_operand:SI 2 "register_operand" "r")))]
4029+  "TARGET_DIVIDE_ENABLED"
4030+  "divu     %0, %z1, %2"
4031+  [(set_attr "type" "divide")]
4032+)
4033+
4034+(define_insn "umodsi3"
4035+  [(set (match_operand:SI 0 "register_operand" "=r")
4036+        (umod:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4037+                 (match_operand:SI 2 "register_operand" "r")))]
4038+  "TARGET_DIVIDE_ENABLED"
4039+  "modu     %0, %z1, %2"
4040+  [(set_attr "type" "divide")]
4041+)
4042+
4043+;; ---------------------------------
4044+;;      negation and inversion
4045+;; ---------------------------------
4046+               
4047+(define_insn "negsi2"
4048+  [(set (match_operand:SI 0 "register_operand" "=r")
4049+        (neg:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
4050+  ""
4051+  "sub      %0, r0, %z1"
4052+  [(set_attr "type" "arith")]
4053+)     
4054+
4055+(define_insn "one_cmplsi2"
4056+  [(set (match_operand:SI 0 "register_operand" "=r")
4057+        (not:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
4058+  ""
4059+  "not      %0, %z1"
4060+  [(set_attr "type" "arith")]
4061+)
4062+
4063+;; ---------------------------------
4064+;;             logical
4065+;; ---------------------------------
4066+
4067+(define_insn "andsi3"
4068+  [(set (match_operand:SI 0 "register_operand" "=r,r")
4069+        (and:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
4070+                (match_operand:SI 2 "register_or_L_operand" "r,L")))]
4071+  ""
4072+  "@
4073+   and      %0, %z1, %2
4074+   andi     %0, %z1, %2"
4075+  [(set_attr "type" "arith")]
4076+)
4077+
4078+(define_insn "iorsi3"
4079+  [(set (match_operand:SI 0 "register_operand" "=r,r")
4080+        (ior:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
4081+                (match_operand:SI 2 "register_or_L_operand" "r,L")))]
4082+  ""
4083+  "@
4084+   or       %0, %z1, %2
4085+   ori      %0, %z1, %2"
4086+  [(set_attr "type" "arith")]
4087+)
4088+
4089+(define_insn "xorsi3"
4090+  [(set (match_operand:SI 0 "register_operand" "=r,r")
4091+        (xor:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
4092+                (match_operand:SI 2 "register_or_L_operand" "r,L")))]
4093+  ""
4094+  "@
4095+   xor      %0, %z1, %2
4096+   xori     %0, %z1, %2"
4097+  [(set_attr "type" "arith")]
4098+)
4099+
4100+(define_insn "*norsi3"
4101+  [(set (match_operand:SI 0 "register_operand" "=r,r")
4102+       (not:SI (ior:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
4103+                       (match_operand:SI 2 "register_or_L_operand" "r,L"))))]
4104+  ""
4105+  "@
4106+   nor      %0, %z1, %2
4107+   nori     %0, %z1, %2"               
4108+  [(set_attr "type" "arith")]
4109+)               
4110+