source: rtems/c/src/librdbg/src/powerpc/rdbg_cpu_asm.S @ 133dcd92

4.104.114.84.95
Last change on this file since 133dcd92 was 133dcd92, checked in by Joel Sherrill <joel.sherrill@…>, on 10/05/99 at 14:02:57

Patch from Eric Valette <valette@…> with two small
fixes related to GDB over TCP/IP debug.

  • Property mode set to 100644
File size: 1.9 KB
Line 
1/*  cpu_asm.s
2 *
3 *  This file contains all assembly code for the Intel i386 implementation
4 *  of RDBG.
5 *
6 * $Id$
7 *
8 */
9
10#include <libcpu/cpu.h>
11#include <libcpu/io.h>
12#include <rtems/score/targopts.h>
13#include <asm.h>
14
15        BEGIN_CODE
16
17/*
18 *  void copyback_data_cache_and_invalidate_instr_cache(addr, size)
19 *
20 *  This routine performs a copy of the data cache
21 *  and invalidate the instruction cache
22 */
23
24        .p2align  5
25        PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
26
27SYM (copyback_data_cache_and_invalidate_instr_cache):
28        /* make sure the data changed is in the cache */
29        sync
30        /* r3 address to handle, r4 length in bytes */
31        addi    r6, r0, PPC_CACHE_ALIGNMENT
32        /* r5 = last address to handle */
33        add     r5,r3,r4
34        /* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) */
35        subi    r0,r6,1
36        andc    r3,r3,r0
37        /* R4 = R3 = copy of first address */
38        mr      r4,r3
39        /*
40         * Copyback data cache
41         */
421:      cmplw   r4,r5    /* r4 >= r5 then done */
43        dcbst   0,r4     /* flush (data cache bloc store) */
44        add     r4,r4,r6 /* r4 = next cache line addr */
45        blt     1b       /* end r4 >= r5 then done */
46        sync            /* Wait for all dcbst to complete on bus */
47        /*
48         * invalidate instruction cache
49         */
50        /* R4 = fisrt address */
51        mr      r4,r3
522:      cmplw   r4,r5    /* r4 >= r5 then done */
53        icbi    0,r4     /* invalidate (instruction cache bloc invalidate) */
54        add     r4,r4,r6 /* r4 = next cache line addr */
55        blt     2b       /* end r4 >= r5 then done */
56        sync             /* Wait for all icbi to complete on bus */
57        isync
58        blr
59
60       
61/*
62 * void enterRdbg(void)
63 *     
64 * This function perform a call to the exception SYSTEM call
65 * It is used :
66 *   1 - in the user code, to simulate a Breakpoint.
67 *       (with justSaveContext = 0)
68 *   2 - in the RDBG code, to push a ctx in the list.
69 *       (with justSaveContext = 1)
70 *
71 * In most of case, it will be use as described in 1.
72 * The 2nd possibility will be used by RDBG to obtain
73 * its own ctx
74 */
75
76        PUBLIC_VAR (enterRdbg)
77
78SYM (enterRdbg):
79        sc
80        blr
81       
82END_CODE
83
84END
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