source: rtems/c/src/librdbg/src/m68k/rdbg_f.c @ 145fc8c

4.104.114.84.95
Last change on this file since 145fc8c was 145fc8c, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 4, 2002 at 10:19:11 PM

2002-11-04 Joel Sherrill <joel@…>

  • src/_servtgt.c: Removed warning by adding support for ITRON tasks and rolling multiple loops into 1.
  • src/m68k/rdbg_f.c: Removed warning.
  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 **************************************************************************
3 *
4 * Component =   
5 *
6 * Synopsis  =   rdbg/m68k/rdbg_f.c
7 *
8 * $Id$
9 *
10 **************************************************************************
11 */
12
13#include <assert.h>
14#include <errno.h>
15#include <rdbg/reg.h>
16#include <rdbg/remdeb.h>
17#include <rdbg/rdbg.h>
18#include <rtems/score/cpu.h>
19#include <rtems/score/thread.h>
20
21m68k_isr_entry set_vector(
22  rtems_isr_entry     handler,
23  rtems_vector_number vector,
24  int                 type
25);
26
27void CtxToRegs (const CPU_Exception_frame * ctx, xdr_regs * regs)
28{
29  regs->r_dreg[0] = ctx->d0;
30  regs->r_dreg[1] = ctx->d1;
31  regs->r_dreg[2] = ctx->d2;
32  regs->r_dreg[3] = ctx->d3;
33  regs->r_dreg[4] = ctx->d4;
34  regs->r_dreg[5] = ctx->d5;
35  regs->r_dreg[6] = ctx->d6;
36  regs->r_dreg[7] = ctx->d7;
37
38  regs->r_areg[0] = ctx->a0;
39  regs->r_areg[1] = ctx->a1;
40  regs->r_areg[2] = ctx->a2;
41  regs->r_areg[3] = ctx->a3;
42  regs->r_areg[4] = ctx->a4;
43  regs->r_areg[5] = ctx->a5;
44  regs->r_areg[6] = ctx->a6;
45  regs->r_areg[7] = ctx->a7;
46
47  regs->r_sr = ctx->sr;
48  regs->r_pc = ctx->pc;
49  regs->r_vec = ctx->vecnum;
50}
51
52  void
53RegsToCtx (const xdr_regs * regs, CPU_Exception_frame * ctx)
54{
55  ctx->d0 = regs->r_dreg[0];
56  ctx->d1 = regs->r_dreg[1];
57  ctx->d2 = regs->r_dreg[2];
58  ctx->d3 = regs->r_dreg[3];
59  ctx->d4 = regs->r_dreg[4];
60  ctx->d5 = regs->r_dreg[5];
61  ctx->d6 = regs->r_dreg[6];
62  ctx->d7 = regs->r_dreg[7];
63
64  ctx->a0 = regs->r_areg[0];
65  ctx->a1 = regs->r_areg[1];
66  ctx->a2 = regs->r_areg[2];
67  ctx->a3 = regs->r_areg[3];
68  ctx->a4 = regs->r_areg[4];
69  ctx->a5 = regs->r_areg[5];
70  ctx->a6 = regs->r_areg[6];
71  ctx->a7 = regs->r_areg[7];
72
73  ctx->sr = regs->r_sr;
74  ctx->pc = regs->r_pc;
75  ctx->vecnum = regs->r_vec;
76}
77
78  void
79get_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
80{
81  /*
82   * ISR stores d0-d1/a0-a1, calls _Thread_Dispatch
83   * _Thread_Dispatch calls _Context_Switch == _CPU_Context_switch
84   * _CPU_Context_switch stores/restores sr,d2-d7,a2-a7
85   * so if my reasoning is correct, *sp points to a location in
86   * _Thread_Dispatch
87   */
88  ctx->vecnum = 0xdeadbeef;
89  ctx->sr = thread->Registers.sr;
90  ctx->pc = *(unsigned32 *) thread->Registers.a7_msp;
91  ctx->d0 = 0xdeadbeef;
92  ctx->d1 = 0xdeadbeef;
93  ctx->a0 = 0xdeadbeef;
94  ctx->a1 = 0xdeadbeef;
95
96  ctx->a2 = (unsigned32) thread->Registers.a2;
97  ctx->a3 = (unsigned32) thread->Registers.a3;
98  ctx->a4 = (unsigned32) thread->Registers.a4;
99  ctx->a5 = (unsigned32) thread->Registers.a5;
100  ctx->a6 = (unsigned32) thread->Registers.a6;
101  ctx->a7 = (unsigned32) thread->Registers.a7_msp;
102  ctx->d2 = thread->Registers.d2;
103  ctx->d3 = thread->Registers.d3;
104  ctx->d4 = thread->Registers.d4;
105  ctx->d5 = thread->Registers.d5;
106  ctx->d6 = thread->Registers.d6;
107  ctx->d7 = thread->Registers.d7;
108}
109
110  void
111set_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
112{
113  thread->Registers.sr = ctx->sr;
114  thread->Registers.d2 = ctx->d2;
115  thread->Registers.d3 = ctx->d3;
116  thread->Registers.d4 = ctx->d4;
117  thread->Registers.d5 = ctx->d5;
118  thread->Registers.d6 = ctx->d6;
119  thread->Registers.d7 = ctx->d7;
120  thread->Registers.a2 = (void *) ctx->a2;
121  thread->Registers.a3 = (void *) ctx->a3;
122  thread->Registers.a4 = (void *) ctx->a4;
123  thread->Registers.a5 = (void *) ctx->a5;
124  thread->Registers.a6 = (void *) ctx->a6;
125  thread->Registers.a7_msp = (void *) ctx->a7;
126}
127
128  int
129Single_Step (CPU_Exception_frame * ctx)
130{
131  if ((ctx->sr & (1 << 15)) != 0 || ExitForSingleStep != 0) {
132    /*
133     * Check coherency
134     */
135    assert ((ctx->sr & (1 << 15)) != 0);
136    assert (ExitForSingleStep != 0);
137    return 0;
138  }
139  ctx->sr |= 1 << 15;
140  ++ExitForSingleStep;
141  return 0;
142}
143
144  int
145CheckForSingleStep (CPU_Exception_frame * ctx)
146{
147  if (ExitForSingleStep) {
148    ctx->sr &= ~(1 << 15);
149    ExitForSingleStep = 0;
150    return 1;
151  }
152  return 0;
153}
154
155  void
156CancelSingleStep (CPU_Exception_frame * ctx)
157{
158  /*
159   * Cancel scheduled SS
160   */
161  ctx->sr &= ~(1 << 15);
162  ExitForSingleStep--;
163}
164
165extern rtems_isr excHandler ();
166
167  void
168connect_rdbg_exception (void)
169{
170  set_vector (excHandler, 9, 0);
171  set_vector (excHandler, 47, 0);
172  set_vector (excHandler, 36, 0);
173}
174
175void
176disconnect_rdbg_exception (void)
177{
178}
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