[c92fb641] | 1 | /* |
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| 2 | ************************************************************************** |
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| 3 | * |
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| 4 | * Component = |
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| 5 | * |
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| 6 | * Synopsis = rdbg/m68k/rdbg_f.c |
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| 7 | * |
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| 8 | * $Id$ |
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| 9 | * |
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| 10 | ************************************************************************** |
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| 11 | */ |
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| 12 | |
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| 13 | #include <assert.h> |
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| 14 | #include <errno.h> |
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[40cf43ea] | 15 | #include <rdbg/reg.h> |
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[c92fb641] | 16 | #include <rdbg/remdeb.h> |
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| 17 | #include <rdbg/rdbg.h> |
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[40cf43ea] | 18 | #include <rtems/score/cpu.h> |
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| 19 | #include <rtems/score/thread.h> |
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[c92fb641] | 20 | |
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[40cf43ea] | 21 | void |
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| 22 | CtxToRegs (const CPU_Exception_frame * ctx, xdr_regs * regs) |
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[c92fb641] | 23 | { |
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| 24 | regs->r_dreg[0] = ctx->d0; |
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| 25 | regs->r_dreg[1] = ctx->d1; |
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| 26 | regs->r_dreg[2] = ctx->d2; |
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| 27 | regs->r_dreg[3] = ctx->d3; |
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| 28 | regs->r_dreg[4] = ctx->d4; |
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| 29 | regs->r_dreg[5] = ctx->d5; |
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| 30 | regs->r_dreg[6] = ctx->d6; |
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| 31 | regs->r_dreg[7] = ctx->d7; |
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| 32 | |
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| 33 | regs->r_areg[0] = ctx->a0; |
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| 34 | regs->r_areg[1] = ctx->a1; |
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| 35 | regs->r_areg[2] = ctx->a2; |
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| 36 | regs->r_areg[3] = ctx->a3; |
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| 37 | regs->r_areg[4] = ctx->a4; |
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| 38 | regs->r_areg[5] = ctx->a5; |
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| 39 | regs->r_areg[6] = ctx->a6; |
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| 40 | regs->r_areg[7] = ctx->a7; |
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| 41 | |
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| 42 | regs->r_sr = ctx->sr; |
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| 43 | regs->r_pc = ctx->pc; |
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| 44 | regs->r_vec = ctx->vecnum; |
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| 45 | } |
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| 46 | |
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[40cf43ea] | 47 | void |
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| 48 | RegsToCtx (const xdr_regs * regs, CPU_Exception_frame * ctx) |
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[c92fb641] | 49 | { |
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| 50 | ctx->d0 = regs->r_dreg[0]; |
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| 51 | ctx->d1 = regs->r_dreg[1]; |
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| 52 | ctx->d2 = regs->r_dreg[2]; |
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| 53 | ctx->d3 = regs->r_dreg[3]; |
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| 54 | ctx->d4 = regs->r_dreg[4]; |
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| 55 | ctx->d5 = regs->r_dreg[5]; |
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| 56 | ctx->d6 = regs->r_dreg[6]; |
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| 57 | ctx->d7 = regs->r_dreg[7]; |
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| 58 | |
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| 59 | ctx->a0 = regs->r_areg[0]; |
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| 60 | ctx->a1 = regs->r_areg[1]; |
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| 61 | ctx->a2 = regs->r_areg[2]; |
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| 62 | ctx->a3 = regs->r_areg[3]; |
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| 63 | ctx->a4 = regs->r_areg[4]; |
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| 64 | ctx->a5 = regs->r_areg[5]; |
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| 65 | ctx->a6 = regs->r_areg[6]; |
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| 66 | ctx->a7 = regs->r_areg[7]; |
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| 67 | |
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| 68 | ctx->sr = regs->r_sr; |
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| 69 | ctx->pc = regs->r_pc; |
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| 70 | ctx->vecnum = regs->r_vec; |
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| 71 | } |
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| 72 | |
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[40cf43ea] | 73 | void |
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| 74 | get_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx) |
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[c92fb641] | 75 | { |
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[40cf43ea] | 76 | /* |
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[c92fb641] | 77 | * ISR stores d0-d1/a0-a1, calls _Thread_Dispatch |
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| 78 | * _Thread_Dispatch calls _Context_Switch == _CPU_Context_switch |
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| 79 | * _CPU_Context_switch stores/restores sr,d2-d7,a2-a7 |
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| 80 | * so if my reasoning is correct, *sp points to a location in |
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| 81 | * _Thread_Dispatch |
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| 82 | */ |
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[40cf43ea] | 83 | ctx->vecnum = 0xdeadbeef; |
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| 84 | ctx->sr = thread->Registers.sr; |
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| 85 | ctx->pc = *(unsigned32 *) thread->Registers.a7_msp; |
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| 86 | ctx->d0 = 0xdeadbeef; |
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| 87 | ctx->d1 = 0xdeadbeef; |
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| 88 | ctx->a0 = 0xdeadbeef; |
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| 89 | ctx->a1 = 0xdeadbeef; |
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| 90 | |
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| 91 | ctx->a2 = (unsigned32) thread->Registers.a2; |
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| 92 | ctx->a3 = (unsigned32) thread->Registers.a3; |
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| 93 | ctx->a4 = (unsigned32) thread->Registers.a4; |
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| 94 | ctx->a5 = (unsigned32) thread->Registers.a5; |
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| 95 | ctx->a6 = (unsigned32) thread->Registers.a6; |
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| 96 | ctx->a7 = (unsigned32) thread->Registers.a7_msp; |
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| 97 | ctx->d2 = thread->Registers.d2; |
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| 98 | ctx->d3 = thread->Registers.d3; |
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| 99 | ctx->d4 = thread->Registers.d4; |
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| 100 | ctx->d5 = thread->Registers.d5; |
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| 101 | ctx->d6 = thread->Registers.d6; |
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| 102 | ctx->d7 = thread->Registers.d7; |
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[c92fb641] | 103 | } |
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| 104 | |
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[40cf43ea] | 105 | void |
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| 106 | set_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx) |
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[c92fb641] | 107 | { |
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[40cf43ea] | 108 | thread->Registers.sr = ctx->sr; |
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| 109 | thread->Registers.d2 = ctx->d2; |
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| 110 | thread->Registers.d3 = ctx->d3; |
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| 111 | thread->Registers.d4 = ctx->d4; |
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| 112 | thread->Registers.d5 = ctx->d5; |
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| 113 | thread->Registers.d6 = ctx->d6; |
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| 114 | thread->Registers.d7 = ctx->d7; |
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| 115 | thread->Registers.a2 = (void *) ctx->a2; |
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| 116 | thread->Registers.a3 = (void *) ctx->a3; |
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| 117 | thread->Registers.a4 = (void *) ctx->a4; |
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| 118 | thread->Registers.a5 = (void *) ctx->a5; |
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| 119 | thread->Registers.a6 = (void *) ctx->a6; |
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| 120 | thread->Registers.a7_msp = (void *) ctx->a7; |
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[c92fb641] | 121 | } |
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| 122 | |
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[40cf43ea] | 123 | int |
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| 124 | Single_Step (CPU_Exception_frame * ctx) |
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[c92fb641] | 125 | { |
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[40cf43ea] | 126 | if ((ctx->sr & (1 << 15)) != 0 || ExitForSingleStep != 0) { |
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| 127 | /* |
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| 128 | * Check coherency |
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| 129 | */ |
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| 130 | assert ((ctx->sr & (1 << 15)) != 0); |
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[c92fb641] | 131 | assert (ExitForSingleStep != 0); |
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| 132 | return 0; |
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| 133 | } |
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[40cf43ea] | 134 | ctx->sr |= 1 << 15; |
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[c92fb641] | 135 | ++ExitForSingleStep; |
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| 136 | return 0; |
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| 137 | } |
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| 138 | |
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[40cf43ea] | 139 | int |
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| 140 | CheckForSingleStep (CPU_Exception_frame * ctx) |
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[c92fb641] | 141 | { |
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[40cf43ea] | 142 | if (ExitForSingleStep) { |
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| 143 | ctx->sr &= ~(1 << 15); |
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| 144 | ExitForSingleStep = 0; |
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| 145 | return 1; |
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| 146 | } |
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| 147 | return 0; |
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[c92fb641] | 148 | } |
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| 149 | |
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[40cf43ea] | 150 | void |
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| 151 | CancelSingleStep (CPU_Exception_frame * ctx) |
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[c92fb641] | 152 | { |
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[40cf43ea] | 153 | /* |
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| 154 | * Cancel scheduled SS |
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| 155 | */ |
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| 156 | ctx->sr &= ~(1 << 15); |
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| 157 | ExitForSingleStep--; |
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[c92fb641] | 158 | } |
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| 159 | |
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[40cf43ea] | 160 | extern rtems_isr excHandler (); |
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[c92fb641] | 161 | |
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[40cf43ea] | 162 | void |
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| 163 | connect_rdbg_exception (void) |
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| 164 | { |
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| 165 | set_vector (excHandler, 9, 0); |
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| 166 | set_vector (excHandler, 47, 0); |
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| 167 | set_vector (excHandler, 36, 0); |
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| 168 | } |
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| 169 | |
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| 170 | void |
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| 171 | disconnect_rdbg_exception (void) |
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[c92fb641] | 172 | { |
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| 173 | } |
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