source: rtems/c/src/librdbg/src/m68k/rdbg_f.c @ 224a646a

4.104.114.84.95
Last change on this file since 224a646a was 224a646a, checked in by Joel Sherrill <joel.sherrill@…>, on 10/31/02 at 20:14:18

2002-10-31 Joel Sherrill <joel@…>

  • src/rdbg.c, src/servtsp.c, src/m68k/rdbg_f.c, src/m68k/any/remdeb_xdr.c, src/powerpc/new_exception_processing/remdeb_xdr.c: Removed warnings.
  • Property mode set to 100644
File size: 4.0 KB
RevLine 
[c92fb641]1/*
2 **************************************************************************
3 *
4 * Component =   
5 *
6 * Synopsis  =   rdbg/m68k/rdbg_f.c
7 *
8 * $Id$
9 *
10 **************************************************************************
11 */
12
13#include <assert.h>
14#include <errno.h>
[40cf43ea]15#include <rdbg/reg.h>
[c92fb641]16#include <rdbg/remdeb.h>
17#include <rdbg/rdbg.h>
[40cf43ea]18#include <rtems/score/cpu.h>
19#include <rtems/score/thread.h>
[c92fb641]20
[40cf43ea]21  void
22CtxToRegs (const CPU_Exception_frame * ctx, xdr_regs * regs)
[c92fb641]23{
24  regs->r_dreg[0] = ctx->d0;
25  regs->r_dreg[1] = ctx->d1;
26  regs->r_dreg[2] = ctx->d2;
27  regs->r_dreg[3] = ctx->d3;
28  regs->r_dreg[4] = ctx->d4;
29  regs->r_dreg[5] = ctx->d5;
30  regs->r_dreg[6] = ctx->d6;
31  regs->r_dreg[7] = ctx->d7;
32
33  regs->r_areg[0] = ctx->a0;
34  regs->r_areg[1] = ctx->a1;
35  regs->r_areg[2] = ctx->a2;
36  regs->r_areg[3] = ctx->a3;
37  regs->r_areg[4] = ctx->a4;
38  regs->r_areg[5] = ctx->a5;
39  regs->r_areg[6] = ctx->a6;
40  regs->r_areg[7] = ctx->a7;
41
42  regs->r_sr = ctx->sr;
43  regs->r_pc = ctx->pc;
44  regs->r_vec = ctx->vecnum;
45}
46
[40cf43ea]47  void
48RegsToCtx (const xdr_regs * regs, CPU_Exception_frame * ctx)
[c92fb641]49{
50  ctx->d0 = regs->r_dreg[0];
51  ctx->d1 = regs->r_dreg[1];
52  ctx->d2 = regs->r_dreg[2];
53  ctx->d3 = regs->r_dreg[3];
54  ctx->d4 = regs->r_dreg[4];
55  ctx->d5 = regs->r_dreg[5];
56  ctx->d6 = regs->r_dreg[6];
57  ctx->d7 = regs->r_dreg[7];
58
59  ctx->a0 = regs->r_areg[0];
60  ctx->a1 = regs->r_areg[1];
61  ctx->a2 = regs->r_areg[2];
62  ctx->a3 = regs->r_areg[3];
63  ctx->a4 = regs->r_areg[4];
64  ctx->a5 = regs->r_areg[5];
65  ctx->a6 = regs->r_areg[6];
66  ctx->a7 = regs->r_areg[7];
67
68  ctx->sr = regs->r_sr;
69  ctx->pc = regs->r_pc;
70  ctx->vecnum = regs->r_vec;
71}
72
[40cf43ea]73  void
74get_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
[c92fb641]75{
[40cf43ea]76  /*
[c92fb641]77   * ISR stores d0-d1/a0-a1, calls _Thread_Dispatch
78   * _Thread_Dispatch calls _Context_Switch == _CPU_Context_switch
79   * _CPU_Context_switch stores/restores sr,d2-d7,a2-a7
80   * so if my reasoning is correct, *sp points to a location in
81   * _Thread_Dispatch
82   */
[40cf43ea]83  ctx->vecnum = 0xdeadbeef;
84  ctx->sr = thread->Registers.sr;
85  ctx->pc = *(unsigned32 *) thread->Registers.a7_msp;
86  ctx->d0 = 0xdeadbeef;
87  ctx->d1 = 0xdeadbeef;
88  ctx->a0 = 0xdeadbeef;
89  ctx->a1 = 0xdeadbeef;
90
91  ctx->a2 = (unsigned32) thread->Registers.a2;
92  ctx->a3 = (unsigned32) thread->Registers.a3;
93  ctx->a4 = (unsigned32) thread->Registers.a4;
94  ctx->a5 = (unsigned32) thread->Registers.a5;
95  ctx->a6 = (unsigned32) thread->Registers.a6;
96  ctx->a7 = (unsigned32) thread->Registers.a7_msp;
97  ctx->d2 = thread->Registers.d2;
98  ctx->d3 = thread->Registers.d3;
99  ctx->d4 = thread->Registers.d4;
100  ctx->d5 = thread->Registers.d5;
101  ctx->d6 = thread->Registers.d6;
102  ctx->d7 = thread->Registers.d7;
[c92fb641]103}
104
[40cf43ea]105  void
106set_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
[c92fb641]107{
[40cf43ea]108  thread->Registers.sr = ctx->sr;
109  thread->Registers.d2 = ctx->d2;
110  thread->Registers.d3 = ctx->d3;
111  thread->Registers.d4 = ctx->d4;
112  thread->Registers.d5 = ctx->d5;
113  thread->Registers.d6 = ctx->d6;
114  thread->Registers.d7 = ctx->d7;
115  thread->Registers.a2 = (void *) ctx->a2;
116  thread->Registers.a3 = (void *) ctx->a3;
117  thread->Registers.a4 = (void *) ctx->a4;
118  thread->Registers.a5 = (void *) ctx->a5;
119  thread->Registers.a6 = (void *) ctx->a6;
120  thread->Registers.a7_msp = (void *) ctx->a7;
[c92fb641]121}
122
[40cf43ea]123  int
124Single_Step (CPU_Exception_frame * ctx)
[c92fb641]125{
[40cf43ea]126  if ((ctx->sr & (1 << 15)) != 0 || ExitForSingleStep != 0) {
127    /*
128     * Check coherency
129     */
130    assert ((ctx->sr & (1 << 15)) != 0);
[c92fb641]131    assert (ExitForSingleStep != 0);
132    return 0;
133  }
[40cf43ea]134  ctx->sr |= 1 << 15;
[c92fb641]135  ++ExitForSingleStep;
136  return 0;
137}
138
[40cf43ea]139  int
140CheckForSingleStep (CPU_Exception_frame * ctx)
[c92fb641]141{
[40cf43ea]142  if (ExitForSingleStep) {
143    ctx->sr &= ~(1 << 15);
144    ExitForSingleStep = 0;
145    return 1;
146  }
147  return 0;
[c92fb641]148}
149
[40cf43ea]150  void
151CancelSingleStep (CPU_Exception_frame * ctx)
[c92fb641]152{
[40cf43ea]153  /*
154   * Cancel scheduled SS
155   */
156  ctx->sr &= ~(1 << 15);
157  ExitForSingleStep--;
[c92fb641]158}
159
[40cf43ea]160extern rtems_isr excHandler ();
[c92fb641]161
[40cf43ea]162  void
163connect_rdbg_exception (void)
164{
165  set_vector (excHandler, 9, 0);
166  set_vector (excHandler, 47, 0);
167  set_vector (excHandler, 36, 0);
168}
169
170void
171disconnect_rdbg_exception (void)
[c92fb641]172{
173}
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