source: rtems/c/src/libchip/shmdr/shm_driver.h @ ac7d5ef0

4.104.114.84.95
Last change on this file since ac7d5ef0 was ac7d5ef0, checked in by Joel Sherrill <joel.sherrill@…>, on May 11, 1995 at 5:39:37 PM

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1/*  shm.h
2 *
3 *  This include file contains all the constants, structures,
4 *  and global variables for this RTEMS based shared memory
5 *  communications interface driver.
6 *
7 *  Processor board dependencies are in other files.
8 *
9 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
10 *  On-Line Applications Research Corporation (OAR).
11 *  All rights assigned to U.S. Government, 1994.
12 *
13 *  This material may be reproduced by or for the U.S. Government pursuant
14 *  to the copyright license under the clause at DFARS 252.227-7013.  This
15 *  notice must appear in all copies of this file and its derivatives.
16 *
17 *  $Id$
18 */
19
20#ifndef __SHM_h
21#define __SHM_h
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <cpu.h>
28
29/*  The information contained in the Node Status, Locked Queue, and
30 *  Envelope Control Blocks must be maintained in a NEUTRAL format.
31 *  Currently the neutral format may be selected as big or little
32 *  endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
33 *
34 *  It is CRITICAL to note that the neutral format can ONLY be
35 *  changed by modifying this file and recompiling the ENTIRE
36 *  SHM driver including ALL target specific support files.
37 *
38 *  The following table details the memory contents for the endian
39 *  field of the Node Status Control Block in the various
40 *  data format configurations (data is in hexadecimal):
41 *
42 *   NEUTRAL NATIVE BYTE 0  BYTE 1  BYTE 2  BYTE 3
43 *   ======= ====== ======  ======  ======  ======
44 *    BIG     BIG     00      00      00      01
45 *    BIG    LITTLE   10      00      00      00
46 *   LITTLE   BIG     01      00      00      00
47 *   LITTLE  LITTLE   00      00      00      10
48 *
49 *
50 *  NOTE: XXX
51 *                PORTABILITY OF LOCKING INSTRUCTIONS
52 *                ===================================
53 *            The locking mechanism described below is not
54 *            general enough.  Where the hardware supports
55 *            it we should use "atomic swap" instructions
56 *            so the values in the lock can be tailored to
57 *            support a CPU with only weak atomic memory
58 *            instructions.  There are combinations of
59 *            CPUs with inflexible atomic memory instructions
60 *            which appear to be incompatible.  For example,
61 *            the SPARClite instruction uses a byte which is
62 *            0xFF when locked.  The PA-RISC uses 1 to indicate
63 *            locked and 0 when unlocked.  These CPUs appear to
64 *            have incompatible lock instructions.  But
65 *            they could be used in a heterogenous system
66 *            with does not mix SPARCs and PA-RISCs.  For
67 *            example, the i386 and SPARC or i386 and SPARC
68 *            could work together.  The bottom line is that
69 *            not every CPU will work together using this
70 *            locking scheme.  There are supposed to be
71 *            algorithms to do this without hardware assist
72 *            and one of these should be incorporated into
73 *            the shared memory driver.
74 *
75 *            The most flexible scheme using the instructions
76 *            of the various CPUs for efficiency would be to use
77 *            "atomic swaps" wherever possible.  Make the lock
78 *            and unlock configurable much like BIG vs LITTLE
79 *            endian use of shared memory is now.  The values
80 *            of the lock could then reflect the "worst"
81 *            CPU in a system.  This still results in mixes
82 *            of CPUs which are incompatible.
83 *
84 *  The current locking mechanism is based upon the MC68020
85 *  "tas" instruction which is atomic.  All ports to other CPUs
86 *  comply with the restrictive placement of lock bit by this
87 *  instruction.  The lock bit is the most significant bit in a
88 *  big-endian rtems_unsigned32.  On other processors, the lock is
89 *  typically implemented via an atomic swap or atomic modify
90 *  bits type instruction.
91 */
92
93#define NEUTRAL_BIG
94
95#ifdef NEUTRAL_BIG
96#define SHM_BIG       0x00000001
97#define SHM_LITTLE    0x10000000
98#endif
99
100#ifdef NEUTRAL_LITTLE
101#define SHM_BIG       0x01000000
102#define SHM_LITTLE    0x00000010
103#endif
104
105/*
106 *  The following are the values used to fill in the lock field.  Some CPUs
107 *  are able to write only a single value into field.  By making the
108 *  lock and unlock values configurable, CPUs which support "atomic swap"
109 *  instructions can generally be made to work in any heterogeneous
110 *  configuration.  However, it is possible for two CPUs to be incompatible
111 *  in regards to the lock field values.  This occurs when two CPUs
112 *  which write only a single value to the field are used in a system
113 *  but the two CPUs write different incompatible values.
114 *
115 *  NOTE:  The following is a first attempt at defining values which
116 *         have a chance at working together.  The m68k should use
117 *         chk2 instead of tas to be less restrictive.  Target endian
118 *         problems (like the Force CPU386 which has (broken) big endian
119 *         view of the VMEbus address space) are not addressed yet.
120 */
121
122#if defined(i960)
123#define SHM_LOCK_VALUE    0x00000080
124#define SHM_UNLOCK_VALUE  0
125#elif defined(m68k)
126#define SHM_LOCK_VALUE    0x80000000
127#define SHM_UNLOCK_VALUE  0
128#define SHM_LOCK_VALUE    0x80000000
129#define SHM_UNLOCK_VALUE  0
130#elif defined(i386)
131#define SHM_LOCK_VALUE    0x80000000
132#define SHM_UNLOCK_VALUE  0
133#elif defined(hppa1_1)
134#define SHM_LOCK_VALUE    0
135#define SHM_UNLOCK_VALUE  1
136#elif defined(unix)
137#define SHM_LOCK_VALUE    0
138#define SHM_UNLOCK_VALUE  1
139#elif defined(no_cpu)               /* for this values are irrelevant */
140#define SHM_LOCK_VALUE    1
141#define SHM_UNLOCK_VALUE  0
142#endif
143
144#define Shm_Convert( value ) \
145  ((Shm_Configuration->convert) ? \
146    (*Shm_Configuration->convert)(value) : (value))
147
148/* constants */
149
150#define SHM_MASTER                  1     /* master initialization node */
151#define SHM_FIRST_NODE              1
152
153/* size constants */
154
155#define KILOBYTE          (1024)
156#define MEGABYTE          (1024*1024)
157
158/* inter-node interrupt values */
159
160#define NO_INTERRUPT            0     /* used for polled nodes */
161#define BYTE                    1
162#define WORD                    2
163#define LONG                    4
164
165/* operational mode constants -- used in SHM Configuration Table */
166#define POLLED_MODE             0
167#define INTR_MODE               1
168
169/* error codes */
170
171#define NO_ERROR                0
172#define SHM_NO_FREE_PKTS        0xf0000
173
174/* null pointers of different types */
175
176#define NULL_ENV_CB             ((Shm_Envelope_control *) 0)
177#define NULL_SHM_INFO           ((struct shm_info *) 0)
178#define NULL_CONVERT            0
179#if 0
180#define NULL_CONVERT            (((rtems_unsigned32 *)())0) /* we want this */
181#endif
182
183/* The following is adjusted so envelopes are 0x80 bytes long. */
184/* It should be >= MIN_PKT_SIZE in rtems.h                     */
185
186#define MAX_PACKET_SIZE          (80)
187
188/* constants pertinent to Locked Queue routines */
189
190#define LQ_UNLOCKED              SHM_UNLOCK_VALUE
191#define LQ_LOCKED                SHM_LOCK_VALUE
192
193/* constants related to the Free Envelope Pool */
194
195#define FREE_ENV_POOL            0
196#define FREE_ENV_CB              (&Shm_Locked_queues[ FREE_ENV_POOL ])
197
198/*  The following are important when dealing with
199 *  the shared memory communications interface area.
200 *
201 *  NOTE: The starting address and length of the shared memory
202 *        is defined in a system dependent file.
203 */
204
205#if 0
206#define START_NS_CBS     ( (rtems_unsigned8 *) START_SHARED_MEM )
207#define START_LQ_CBS     ( ((rtems_unsigned8 *) START_NS_CBS) + \
208        ( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
209#define START_ENVELOPES  ( ((rtems_unsigned8 *) START_LQ_CBS) + \
210        ( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
211#define END_SHMCI_AREA    ( (rtems_unsigned8 *) START_ENVELOPES + \
212        ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
213#define END_SHARED_MEM   ((rtems_unsigned32)START_SHARED_MEM+SHARED_MEM_LEN)
214#endif
215
216#define START_NS_CBS     ((void *)Shm_Configuration->base)
217#define START_LQ_CBS     ((START_NS_CBS) + \
218        ( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
219#define START_ENVELOPES  ( ((void *) START_LQ_CBS) + \
220        ( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
221#define END_SHMCI_AREA    ( (void *) START_ENVELOPES + \
222        ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
223#define END_SHARED_MEM   (START_NS_CBS+Shm_Configuration->length)
224
225/* macros */
226
227#define Shm_Is_master_node() \
228  ( SHM_MASTER == Shm_Local_node )
229
230#define Shm_Free_envelope( ecb ) \
231  Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
232#define Shm_Allocate_envelope() \
233  Shm_Locked_queue_Get(FREE_ENV_CB)
234
235#define Shm_Initialize_receive_queue(node) \
236  Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
237
238#define Shm_Append_to_receive_queue(node, ecb) \
239  Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
240
241#define Shm_Envelope_control_to_packet_prefix_pointer(ecb)  \
242   ((void *)(ecb)->packet)
243
244#define Shm_Packet_prefix_to_envelope_control_pointer( pkt )   \
245   ((Shm_Envelope_control *)((rtems_unsigned8 *)(pkt) - \
246   (sizeof(Shm_Envelope_preamble) + 4*sizeof(vol_u32))))
247
248#define Shm_Build_preamble(ecb, node) \
249       (ecb)->Preamble.endian = Shm_Configuration->format
250
251#define Shm_Build_postamble( ecb )
252
253/* structures */
254
255typedef volatile rtems_unsigned8  vol_u8;
256typedef volatile rtems_unsigned32 vol_u32;
257
258/* shm control information */
259
260struct shm_info {
261  vol_u32 not_currently_used_0;
262  vol_u32 not_currently_used_1;
263  vol_u32 not_currently_used_2;
264  vol_u32 not_currently_used_3;
265};
266
267typedef struct {
268  /*byte start_of_text;*/
269  vol_u32 endian;
270  vol_u32 not_currently_used_0;
271  vol_u32 not_currently_used_1;
272  vol_u32 not_currently_used_2;
273} Shm_Envelope_preamble;
274
275typedef struct {
276  vol_u32 not_currently_used_0;
277  vol_u32 not_currently_used_1;
278  vol_u32 not_currently_used_2;
279  vol_u32 not_currently_used_3;
280  /*byte end_of_text;*/
281} Shm_Envelope_postable;
282
283/* WARNING! If you change this structure, don't forget to change
284 *          Shm_Envelope_control_to_packet_prefix_pointer() and
285 *          Shm_Packet_prefix_to_envelope_control_pointer() above.
286 */
287
288/*  This comment block describes the contents of each field
289 *  of the Envelope Control Block:
290 *
291 *  next      - The index of the next envelope on this queue.
292 *  queue     - The index of the queue this envelope is on.
293 *  index     - The index of this envelope.
294 *  Preamble  - Generic packet preamble.  One day this structure
295 *              could be enhanced to contain routing information.
296 *  packet    - RTEMS MPCI packet.  Untouched by SHM Driver
297 *              other than copying and format conversion as
298 *              documented in the RTEMS User's Guide.
299 *  Postamble - Generic packet postamble.  One day this structure
300 *              could be enhanced to contain checksum information.
301 */
302
303typedef struct {
304  vol_u32           next;     /* next envelope on queue       */
305  vol_u32           queue;    /* queue on which this resides  */
306  vol_u32           index;    /* index into array of envelopes*/
307  vol_u32           pad0;     /* insure the next one is aligned */
308  Shm_Envelope_preamble    Preamble; /* header information           */
309  vol_u8            packet[MAX_PACKET_SIZE]; /* RTEMS INFO    */
310  Shm_Envelope_postable   Postamble;/* trailer information          */
311} Shm_Envelope_control;
312
313/*  This comment block describes the contents of each field
314 *  of the Locked Queue Control Block:
315 *
316 *  lock      - Lock used to insure mutually exclusive access.
317 *  front     - Index of first envelope on queue.  This field
318 *              is used to remove head of queue (receive).
319 *  rear      - Index of last envelope on queue.  This field
320 *              is used to add evelope to queue (send).
321 *  owner     - The node number of the recipient (owning) node.
322 *              RTEMS does not use the node number zero (0).
323 *              The zero node is used by the SHM Driver for the
324 *              Free Envelope Queue shared by all nodes.
325 */
326
327typedef struct {
328  vol_u32 lock;  /* lock field for this queue    */
329  vol_u32 front; /* first envelope on queue      */
330  vol_u32 rear;  /* last envelope on queue       */
331  vol_u32 owner; /* receiving (i.e. owning) node */
332} Shm_Locked_queue_Control;
333
334/*  This comment block describes the contents of each field
335 *  of the Node Status Control Block:
336 *
337 *  status    - Node status.  Current values are Pending Initialization,
338 *              Initialization Complete, and Active Node.  Other values
339 *              could be added to enhance fault tolerance.
340 *  error     - Zero if the node has not failed.  Otherwise,
341 *              this field contains a status indicating the
342 *              failure reason.
343 *  int_address, int_value, and int_length
344 *            - These field are the Interrupt Information table
345 *              for this node in neutral format.  This is how
346 *              each node knows how to generate interrupts.
347 */
348
349typedef struct {
350  vol_u32  status;         /* node status information     */
351  vol_u32  error;          /* fatal error code            */
352  vol_u32  int_address;    /* write here for interrupt    */
353  vol_u32  int_value;      /* this value causes interrupt */
354  vol_u32  int_length;     /* for this length (0,1,2,4)   */
355  vol_u32  not_currently_used_0;
356  vol_u32  not_currently_used_1;
357  vol_u32  not_currently_used_2;
358} Shm_Node_status_control;
359
360/*  This comment block describes the contents of each field
361 *  of the Interrupt Information Table.  This table describes
362 *  how another node can generate an interrupt to this node.
363 *  This information is target board dependent.  If the
364 *  SHM Driver is in POLLED_MODE, then all fields should
365 *  be initialized to NO_INTERRUPT.
366 *
367 *  address   - The address to which another node should
368 *              write to cause an interrupt.
369 *  value     - The value which must be written
370 *  length    - The size of the value to write.  Valid
371 *              values are BYTE, WORD, and LONG.
372 *
373 *  NOTE:  The Node Status Control Block contains this
374 *         information in neutral format and not in a
375 *         structure to avoid potential alignment problems.
376 */
377
378typedef struct {
379  vol_u32 *address;        /* write here for interrupt    */
380  vol_u32  value;          /* this value causes interrupt */
381  vol_u32  length;         /* for this length (0,1,2,4)   */
382} Shm_Interrupt_information;
383
384/*  SHM Configuration Table
385 *
386 *  This comment block describes the contents of each field
387 *  of the SHM Configuration Table.
388 *
389 *  base       - The base address of the shared memory.  This
390 *               address may be specific to this node.
391 *  length     - The length of the shared memory in bytes.
392 *  format     - The natural format for rtems_unsigned32's in the
393 *               shared memory.  Valid values are currently
394 *               only SHM_LITTLE and SHM_BIG.
395 *  convert    - The address of the routine which converts
396 *               between neutral and local format.
397 *  poll_intr  - The operational mode of the driver.  Some
398 *               target boards may not provide hardware for
399 *               an interprocessor interrupt.  If POLLED_MODE
400 *               is selected, the SHM driver will install a
401 *               wrapper around the Clock_isr() to poll for
402 *               incoming packets.  Throughput is dependent
403 *               on the time between clock interrupts.
404 *               Valid values are POLLED_MODE and INTR_MODE.
405 *  cause_intr - This is the address of the routine used to
406 *               write to a particular address and cause an
407 *               interrupt on another node.  This routine
408 *               may need to be target dependent if something
409 *               other than a normal write from C does not work.
410 *  Intr       - This structure describes the operation required
411 *               to cause an interrupt to this node.  The actual
412 *               contents of this structure are described above.
413 */
414
415struct shm_config_info {
416  vol_u32           *base;     /* base address of SHM         */
417  vol_u32            length;   /* length (in bytes) of SHM    */
418  vol_u32            format;   /* SHM is big or little endian */
419  vol_u32          (*convert)();/* neutral conversion routine */
420  vol_u32            poll_intr;/* POLLED or INTR driven mode  */
421  void             (*cause_intr)( rtems_unsigned32 );
422  Shm_Interrupt_information   Intr;     /* cause intr information      */
423};
424
425typedef struct shm_config_info shm_config_table;
426
427/* global variables */
428
429#ifdef _SHM_INIT
430#define SHM_EXTERN
431#else
432#define SHM_EXTERN extern
433#endif
434
435SHM_EXTERN shm_config_table             *Shm_Configuration;
436SHM_EXTERN Shm_Interrupt_information     Shm_Interrupt_table[16];
437SHM_EXTERN Shm_Node_status_control      *Shm_Node_statuses;
438SHM_EXTERN Shm_Locked_queue_Control     *Shm_Locked_queues;
439SHM_EXTERN Shm_Envelope_control         *Shm_Envelopes;
440SHM_EXTERN rtems_configuration_table    *Shm_RTEMS_Configuration;
441SHM_EXTERN rtems_multiprocessing_table  *Shm_RTEMS_MP_Configuration;
442SHM_EXTERN rtems_unsigned32              Shm_Receive_message_count;
443SHM_EXTERN rtems_unsigned32              Shm_Null_message_count;
444SHM_EXTERN rtems_unsigned32              Shm_Interrupt_count;
445SHM_EXTERN rtems_unsigned32              Shm_Local_node;
446SHM_EXTERN Shm_Locked_queue_Control      *Shm_Local_receive_queue;
447SHM_EXTERN Shm_Node_status_control       *Shm_Local_node_status;
448SHM_EXTERN rtems_unsigned32              Shm_isrstat;
449                                                     /* reported by shmdr */
450
451SHM_EXTERN rtems_unsigned32 Shm_Pending_initialization;
452SHM_EXTERN rtems_unsigned32 Shm_Initialization_complete;
453SHM_EXTERN rtems_unsigned32 Shm_Active_node;
454
455SHM_EXTERN rtems_unsigned32 Shm_Maximum_nodes;
456SHM_EXTERN rtems_unsigned32 Shm_Maximum_envelopes;
457
458SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_End_of_list;
459SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_Not_on_list;
460
461/* functions */
462
463/* locked queue routines */
464void           Shm_Locked_queue_Add(
465                  Shm_Locked_queue_Control *, Shm_Envelope_control * );
466Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
467void           Shm_Locked_queue_Initialize(
468                  Shm_Locked_queue_Control *, rtems_unsigned32 );
469            /* Shm_Initialize_lock is CPU dependent */
470            /* Shm_Lock is CPU dependent */
471            /* Shm_Unlock is CPU dependent */
472
473/* portable routines */
474void           Init_env_pool();
475void           Shm_Print_statistics( void );
476void           MPCI_Fatal( rtems_unsigned32 );
477rtems_task     Shm_Cause_interrupt( rtems_unsigned32 );
478void           Shm_Poll();
479void           Shm_setclockvec();
480void           Shm_Convert_packet( rtems_packet_prefix * );
481
482/* CPU specific routines are inlined in shmcpu.h */
483
484/* target specific routines */
485void          *Shm_Convert_address( void * );
486void           Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );
487void           Shm_isr();
488void           Shm_setvec( void );
489
490void           Shm_Initialize_lock( Shm_Locked_queue_Control * );
491void           Shm_Lock( Shm_Locked_queue_Control * );
492void           Shm_Unlock( Shm_Locked_queue_Control * );
493
494/* MPCI entry points */
495rtems_mpci_entry Shm_Get_packet(
496  rtems_packet_prefix **
497);
498
499rtems_mpci_entry Shm_Initialization(
500  rtems_configuration_table   *configuration,
501  rtems_cpu_table             *cpu_configuration,
502  rtems_multiprocessing_table *mp_configuration
503);
504
505rtems_mpci_entry Shm_Receive_packet(
506  rtems_packet_prefix **
507);
508
509rtems_mpci_entry Shm_Return_packet(
510  rtems_packet_prefix *
511);
512
513rtems_mpci_entry Shm_Send_packet(
514  rtems_unsigned32,
515  rtems_packet_prefix *
516);
517
518#ifdef _SHM_INIT
519
520/* multiprocessor communications interface (MPCI) table */
521
522rtems_mpci_table MPCI_table  = {
523  100000,                     /* default timeout value in ticks */
524  Shm_Initialization,         /* initialization procedure   */
525  Shm_Get_packet,             /* get packet procedure       */
526  Shm_Return_packet,          /* return packet procedure    */
527  Shm_Send_packet,            /* packet send procedure      */
528  Shm_Receive_packet          /* packet receive procedure   */
529};
530
531#else
532
533extern rtems_mpci_table MPCI_table;
534
535#endif
536
537#ifdef __cplusplus
538}
539#endif
540
541#endif
542/* end of include file */
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