source: rtems/c/src/libchip/shmdr/shm_driver.h @ 7452b85

4.104.114.84.95
Last change on this file since 7452b85 was 7452b85, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 29, 2004 at 8:36:20 PM

2004-09-29 Joel Sherrill <joel@…>

  • aclocal/rtems-cpu-subdirs.m4, libchip/shmdr/shm_driver.h, libnetworking/pppd/utils.c: i960 obsoleted and all references removed.
  • Property mode set to 100644
File size: 19.4 KB
Line 
1/*  shm_driver.h
2 *
3 *  This include file contains all the constants, structures,
4 *  and global variables for this RTEMS based shared memory
5 *  communications interface driver.
6 *
7 *  Processor board dependencies are in other files.
8 *
9 *  COPYRIGHT (c) 1989-1999.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef __SHM_h
20#define __SHM_h
21
22#include <rtems/clockdrv.h>
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/*  The information contained in the Node Status, Locked Queue, and
29 *  Envelope Control Blocks must be maintained in a NEUTRAL format.
30 *  Currently the neutral format may be selected as big or little
31 *  endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
32 *
33 *  It is CRITICAL to note that the neutral format can ONLY be
34 *  changed by modifying this file and recompiling the ENTIRE
35 *  SHM driver including ALL target specific support files.
36 *
37 *  The following table details the memory contents for the endian
38 *  field of the Node Status Control Block in the various
39 *  data format configurations (data is in hexadecimal):
40 *
41 *   NEUTRAL NATIVE BYTE 0  BYTE 1  BYTE 2  BYTE 3
42 *   ======= ====== ======  ======  ======  ======
43 *    BIG     BIG     00      00      00      01
44 *    BIG    LITTLE   10      00      00      00
45 *   LITTLE   BIG     01      00      00      00
46 *   LITTLE  LITTLE   00      00      00      10
47 *
48 *
49 *  NOTE: XXX
50 *                PORTABILITY OF LOCKING INSTRUCTIONS
51 *                ===================================
52 *            The locking mechanism described below is not
53 *            general enough.  Where the hardware supports
54 *            it we should use "atomic swap" instructions
55 *            so the values in the lock can be tailored to
56 *            support a CPU with only weak atomic memory
57 *            instructions.  There are combinations of
58 *            CPUs with inflexible atomic memory instructions
59 *            which appear to be incompatible.  For example,
60 *            the SPARClite instruction uses a byte which is
61 *            0xFF when locked.  The PA-RISC uses 1 to indicate
62 *            locked and 0 when unlocked.  These CPUs appear to
63 *            have incompatible lock instructions.  But
64 *            they could be used in a heterogenous system
65 *            with does not mix SPARCs and PA-RISCs.  For
66 *            example, the i386 and SPARC or i386 and SPARC
67 *            could work together.  The bottom line is that
68 *            not every CPU will work together using this
69 *            locking scheme.  There are supposed to be
70 *            algorithms to do this without hardware assist
71 *            and one of these should be incorporated into
72 *            the shared memory driver.
73 *
74 *            The most flexible scheme using the instructions
75 *            of the various CPUs for efficiency would be to use
76 *            "atomic swaps" wherever possible.  Make the lock
77 *            and unlock configurable much like BIG vs LITTLE
78 *            endian use of shared memory is now.  The values
79 *            of the lock could then reflect the "worst"
80 *            CPU in a system.  This still results in mixes
81 *            of CPUs which are incompatible.
82 *
83 *  The current locking mechanism is based upon the MC68020
84 *  "tas" instruction which is atomic.  All ports to other CPUs
85 *  comply with the restrictive placement of lock bit by this
86 *  instruction.  The lock bit is the most significant bit in a
87 *  big-endian uint32_t  .  On other processors, the lock is
88 *  typically implemented via an atomic swap or atomic modify
89 *  bits type instruction.
90 */
91
92#define NEUTRAL_BIG
93
94#ifdef NEUTRAL_BIG
95#define SHM_BIG       0x00000001
96#define SHM_LITTLE    0x10000000
97#endif
98
99#ifdef NEUTRAL_LITTLE
100#define SHM_BIG       0x01000000
101#define SHM_LITTLE    0x00000010
102#endif
103
104/*
105 *  The following are the values used to fill in the lock field.  Some CPUs
106 *  are able to write only a single value into field.  By making the
107 *  lock and unlock values configurable, CPUs which support "atomic swap"
108 *  instructions can generally be made to work in any heterogeneous
109 *  configuration.  However, it is possible for two CPUs to be incompatible
110 *  in regards to the lock field values.  This occurs when two CPUs
111 *  which write only a single value to the field are used in a system
112 *  but the two CPUs write different incompatible values.
113 *
114 *  NOTE:  The following is a first attempt at defining values which
115 *         have a chance at working together.  The m68k should use
116 *         chk2 instead of tas to be less restrictive.  Target endian
117 *         problems (like the Force CPU386 which has (broken) big endian
118 *         view of the VMEbus address space) are not addressed yet.
119 */
120
121#if defined(__mc68000__)
122#define SHM_LOCK_VALUE    0x80000000
123#define SHM_UNLOCK_VALUE  0
124#define SHM_LOCK_VALUE    0x80000000
125#define SHM_UNLOCK_VALUE  0
126#elif defined(__i386__)
127#define SHM_LOCK_VALUE    0x80000000
128#define SHM_UNLOCK_VALUE  0
129#elif defined(__mips__)
130#define SHM_LOCK_VALUE    0x80000000
131#define SHM_UNLOCK_VALUE  0
132#elif defined(__hppa__)
133#define SHM_LOCK_VALUE    0
134#define SHM_UNLOCK_VALUE  1
135#elif defined(__PPC__)
136#define SHM_LOCK_VALUE    1
137#define SHM_UNLOCK_VALUE  0
138#elif defined(__unix__)
139#define SHM_LOCK_VALUE    0
140#define SHM_UNLOCK_VALUE  1
141#elif defined(_AM29K)
142#define SHM_LOCK_VALUE    0
143#define SHM_UNLOCK_VALUE  1
144#elif defined(no_cpu)               /* for this values are irrelevant */
145#define SHM_LOCK_VALUE    1
146#define SHM_UNLOCK_VALUE  0
147#else
148#error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture"
149#endif
150
151#define Shm_Convert( value ) \
152  ((Shm_Configuration->convert) ? \
153    (*Shm_Configuration->convert)(value) : (value))
154
155/* constants */
156
157#define SHM_MASTER                  1     /* master initialization node */
158#define SHM_FIRST_NODE              1
159
160/* size constants */
161
162#define KILOBYTE          (1024)
163#define MEGABYTE          (1024*1024)
164
165/* inter-node interrupt values */
166
167#define NO_INTERRUPT            0     /* used for polled nodes */
168#define BYTE                    1
169#define WORD                    2
170#define LONG                    4
171
172/* operational mode constants -- used in SHM Configuration Table */
173#define POLLED_MODE             0
174#define INTR_MODE               1
175
176/* error codes */
177
178#define NO_ERROR                0
179#define SHM_NO_FREE_PKTS        0xf0000
180
181/* null pointers of different types */
182
183#define NULL_ENV_CB             ((Shm_Envelope_control *) 0)
184#define NULL_CONVERT            0
185
186/*
187 * size of stuff before preamble in envelope.
188 * It must be a constant since we will use it to generate MAX_PACKET_SIZE
189 */
190
191#define SHM_ENVELOPE_PREFIX_OVERHEAD    (4 * sizeof(vol_u32))
192
193/*
194 *  The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long.
195 *  It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h.
196 */
197
198#ifndef MAX_ENVELOPE_SIZE
199#define MAX_ENVELOPE_SIZE 0x180
200#endif
201
202#define MAX_PACKET_SIZE  (MAX_ENVELOPE_SIZE -               \
203                          SHM_ENVELOPE_PREFIX_OVERHEAD +    \
204                          sizeof(Shm_Envelope_preamble) +   \
205                          sizeof(Shm_Envelope_postamble))
206
207
208/* constants pertinent to Locked Queue routines */
209
210#define LQ_UNLOCKED              SHM_UNLOCK_VALUE
211#define LQ_LOCKED                SHM_LOCK_VALUE
212
213/* constants related to the Free Envelope Pool */
214
215#define FREE_ENV_POOL            0
216#define FREE_ENV_CB              (&Shm_Locked_queues[ FREE_ENV_POOL ])
217
218/*  The following are important when dealing with
219 *  the shared memory communications interface area.
220 *
221 *  NOTE: The starting address and length of the shared memory
222 *        is defined in a system dependent file.
223 */
224
225#define START_NS_CBS     ((void *)Shm_Configuration->base)
226#define START_LQ_CBS     ((START_NS_CBS) + \
227        ( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
228#define START_ENVELOPES  ( ((void *) START_LQ_CBS) + \
229        ( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
230#define END_SHMCI_AREA    ( (void *) START_ENVELOPES + \
231        ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
232#define END_SHARED_MEM   (START_NS_CBS+Shm_Configuration->length)
233
234/* macros */
235
236#define Shm_Is_master_node()  \
237  ( SHM_MASTER == Shm_Local_node )
238
239#define Shm_Free_envelope( ecb ) \
240  Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
241#define Shm_Allocate_envelope() \
242  Shm_Locked_queue_Get(FREE_ENV_CB)
243
244#define Shm_Initialize_receive_queue(node) \
245  Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
246
247#define Shm_Append_to_receive_queue(node, ecb) \
248  Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
249
250#define Shm_Envelope_control_to_packet_prefix_pointer(ecb)  \
251   ((void *)(ecb)->packet)
252
253#define Shm_Packet_prefix_to_envelope_control_pointer( pkt )   \
254   ((Shm_Envelope_control *)((uint8_t*)(pkt) - \
255   (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD)))
256
257#define Shm_Build_preamble(ecb, node) \
258       (ecb)->Preamble.endian = Shm_Configuration->format
259
260#define Shm_Build_postamble( ecb )
261
262/* volatile types */
263
264typedef volatile uint8_t    vol_u8;
265typedef volatile uint32_t   vol_u32;
266
267/* shm control information */
268
269struct shm_info {
270  vol_u32 not_currently_used_0;
271  vol_u32 not_currently_used_1;
272  vol_u32 not_currently_used_2;
273  vol_u32 not_currently_used_3;
274};
275
276typedef struct {
277  /*byte start_of_text;*/
278  vol_u32 endian;
279  vol_u32 not_currently_used_0;
280  vol_u32 not_currently_used_1;
281  vol_u32 not_currently_used_2;
282} Shm_Envelope_preamble;
283
284typedef struct {
285} Shm_Envelope_postamble;
286
287/* WARNING! If you change this structure, don't forget to change
288 *          SHM_ENVELOPE_PREFIX_OVERHEAD and
289 *          Shm_Packet_prefix_to_envelope_control_pointer() above.
290 */
291
292/*  This comment block describes the contents of each field
293 *  of the Envelope Control Block:
294 *
295 *  next      - The index of the next envelope on this queue.
296 *  queue     - The index of the queue this envelope is on.
297 *  index     - The index of this envelope.
298 *  Preamble  - Generic packet preamble.  One day this structure
299 *              could be enhanced to contain routing information.
300 *  packet    - RTEMS MPCI packet.  Untouched by SHM Driver
301 *              other than copying and format conversion as
302 *              documented in the RTEMS User's Guide.
303 *  Postamble - Generic packet postamble.  One day this structure
304 *              could be enhanced to contain checksum information.
305 */
306
307typedef struct {
308  vol_u32           next;     /* next envelope on queue       */
309  vol_u32           queue;    /* queue on which this resides  */
310  vol_u32           index;    /* index into array of envelopes*/
311  vol_u32           pad0;     /* insure the next one is aligned */
312  Shm_Envelope_preamble    Preamble; /* header information           */
313  vol_u8            packet[MAX_PACKET_SIZE]; /* RTEMS INFO    */
314  Shm_Envelope_postamble   Postamble;/* trailer information          */
315} Shm_Envelope_control;
316
317/*  This comment block describes the contents of each field
318 *  of the Locked Queue Control Block:
319 *
320 *  lock      - Lock used to insure mutually exclusive access.
321 *  front     - Index of first envelope on queue.  This field
322 *              is used to remove head of queue (receive).
323 *  rear      - Index of last envelope on queue.  This field
324 *              is used to add evelope to queue (send).
325 *  owner     - The node number of the recipient (owning) node.
326 *              RTEMS does not use the node number zero (0).
327 *              The zero node is used by the SHM Driver for the
328 *              Free Envelope Queue shared by all nodes.
329 */
330
331typedef struct {
332  vol_u32 lock;  /* lock field for this queue    */
333  vol_u32 front; /* first envelope on queue      */
334  vol_u32 rear;  /* last envelope on queue       */
335  vol_u32 owner; /* receiving (i.e. owning) node */
336} Shm_Locked_queue_Control;
337
338/*  This comment block describes the contents of each field
339 *  of the Node Status Control Block:
340 *
341 *  status    - Node status.  Current values are Pending Initialization,
342 *              Initialization Complete, and Active Node.  Other values
343 *              could be added to enhance fault tolerance.
344 *  error     - Zero if the node has not failed.  Otherwise,
345 *              this field contains a status indicating the
346 *              failure reason.
347 *  int_address, int_value, and int_length
348 *            - These field are the Interrupt Information table
349 *              for this node in neutral format.  This is how
350 *              each node knows how to generate interrupts.
351 */
352
353typedef struct {
354  vol_u32  status;         /* node status information     */
355  vol_u32  error;          /* fatal error code            */
356  vol_u32  int_address;    /* write here for interrupt    */
357  vol_u32  int_value;      /* this value causes interrupt */
358  vol_u32  int_length;     /* for this length (0,1,2,4)   */
359  vol_u32  not_currently_used_0;
360  vol_u32  not_currently_used_1;
361  vol_u32  not_currently_used_2;
362} Shm_Node_status_control;
363
364/*  This comment block describes the contents of each field
365 *  of the Interrupt Information Table.  This table describes
366 *  how another node can generate an interrupt to this node.
367 *  This information is target board dependent.  If the
368 *  SHM Driver is in POLLED_MODE, then all fields should
369 *  be initialized to NO_INTERRUPT.
370 *
371 *  address   - The address to which another node should
372 *              write to cause an interrupt.
373 *  value     - The value which must be written
374 *  length    - The size of the value to write.  Valid
375 *              values are BYTE, WORD, and LONG.
376 *
377 *  NOTE:  The Node Status Control Block contains this
378 *         information in neutral format and not in a
379 *         structure to avoid potential alignment problems.
380 */
381
382typedef struct {
383  vol_u32 *address;        /* write here for interrupt    */
384  vol_u32  value;          /* this value causes interrupt */
385  vol_u32  length;         /* for this length (0,1,2,4)   */
386} Shm_Interrupt_information;
387
388/*  SHM Configuration Table
389 *
390 *  This comment block describes the contents of each field
391 *  of the SHM Configuration Table.
392 *
393 *  base       - The base address of the shared memory.  This
394 *               address may be specific to this node.
395 *  length     - The length of the shared memory in bytes.
396 *  format     - The natural format for uint32_t  's in the
397 *               shared memory.  Valid values are currently
398 *               only SHM_LITTLE and SHM_BIG.
399 *  convert    - The address of the routine which converts
400 *               between neutral and local format.
401 *  poll_intr  - The operational mode of the driver.  Some
402 *               target boards may not provide hardware for
403 *               an interprocessor interrupt.  If POLLED_MODE
404 *               is selected, the SHM driver will install a
405 *               wrapper around the Clock_isr() to poll for
406 *               incoming packets.  Throughput is dependent
407 *               on the time between clock interrupts.
408 *               Valid values are POLLED_MODE and INTR_MODE.
409 *  cause_intr - This is the address of the routine used to
410 *               write to a particular address and cause an
411 *               interrupt on another node.  This routine
412 *               may need to be target dependent if something
413 *               other than a normal write from C does not work.
414 *  Intr       - This structure describes the operation required
415 *               to cause an interrupt to this node.  The actual
416 *               contents of this structure are described above.
417 */
418
419struct shm_config_info {
420  vol_u32           *base;     /* base address of SHM         */
421  vol_u32            length;   /* length (in bytes) of SHM    */
422  vol_u32            format;   /* SHM is big or little endian */
423  vol_u32          (*convert)();/* neutral conversion routine */
424  vol_u32            poll_intr;/* POLLED or INTR driven mode  */
425  void             (*cause_intr)( uint32_t);
426  Shm_Interrupt_information   Intr;     /* cause intr information      */
427};
428
429typedef struct shm_config_info shm_config_table;
430
431/* global variables */
432
433#ifdef _SHM_INIT
434#define SHM_EXTERN
435#else
436#define SHM_EXTERN extern
437#endif
438
439SHM_EXTERN shm_config_table             *Shm_Configuration;
440SHM_EXTERN Shm_Interrupt_information    *Shm_Interrupt_table;
441SHM_EXTERN Shm_Node_status_control      *Shm_Node_statuses;
442SHM_EXTERN Shm_Locked_queue_Control     *Shm_Locked_queues;
443SHM_EXTERN Shm_Envelope_control         *Shm_Envelopes;
444SHM_EXTERN rtems_configuration_table    *Shm_RTEMS_Configuration;
445SHM_EXTERN rtems_multiprocessing_table  *Shm_RTEMS_MP_Configuration;
446SHM_EXTERN uint32_t                Shm_Receive_message_count;
447SHM_EXTERN uint32_t                Shm_Null_message_count;
448SHM_EXTERN uint32_t                Shm_Interrupt_count;
449SHM_EXTERN uint32_t                Shm_Local_node;
450SHM_EXTERN Shm_Locked_queue_Control      *Shm_Local_receive_queue;
451SHM_EXTERN Shm_Node_status_control       *Shm_Local_node_status;
452SHM_EXTERN uint32_t                Shm_isrstat;
453                                                     /* reported by shmdr */
454
455SHM_EXTERN uint32_t   Shm_Pending_initialization;
456SHM_EXTERN uint32_t   Shm_Initialization_complete;
457SHM_EXTERN uint32_t   Shm_Active_node;
458
459SHM_EXTERN uint32_t   Shm_Maximum_nodes;
460SHM_EXTERN uint32_t   Shm_Maximum_envelopes;
461
462SHM_EXTERN uint32_t   Shm_Locked_queue_End_of_list;
463SHM_EXTERN uint32_t   Shm_Locked_queue_Not_on_list;
464
465/* functions */
466
467/* locked queue routines */
468void           Shm_Locked_queue_Add(
469                  Shm_Locked_queue_Control *, Shm_Envelope_control * );
470Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
471void           Shm_Locked_queue_Initialize(
472                  Shm_Locked_queue_Control *, uint32_t);
473            /* Shm_Initialize_lock is CPU dependent */
474            /* Shm_Lock is CPU dependent */
475            /* Shm_Unlock is CPU dependent */
476
477/* portable routines */
478void           Init_env_pool();
479void           Shm_Print_statistics( void );
480void           MPCI_Fatal( Internal_errors_Source, boolean, uint32_t);
481rtems_task     Shm_Cause_interrupt( uint32_t);
482void           Shm_Poll();
483void           Shm_setclockvec();
484void           Shm_Convert_packet( rtems_packet_prefix * );
485
486/* CPU specific routines are inlined in shmcpu.h */
487
488/* target specific routines */
489void          *Shm_Convert_address( void * );
490void           Shm_Get_configuration( uint32_t, shm_config_table ** );
491void           Shm_isr();
492void           Shm_setvec( void );
493
494void           Shm_Initialize_lock( Shm_Locked_queue_Control * );
495void           Shm_Lock( Shm_Locked_queue_Control * );
496void           Shm_Unlock( Shm_Locked_queue_Control * );
497
498/* MPCI entry points */
499rtems_mpci_entry Shm_Get_packet(
500  rtems_packet_prefix **
501);
502
503rtems_mpci_entry Shm_Initialization( void );
504
505rtems_mpci_entry Shm_Receive_packet(
506  rtems_packet_prefix **
507);
508
509rtems_mpci_entry Shm_Return_packet(
510  rtems_packet_prefix *
511);
512
513rtems_mpci_entry Shm_Send_packet(
514  uint32_t,
515  rtems_packet_prefix *
516);
517
518extern rtems_mpci_table MPCI_table;
519
520#ifdef _SHM_INIT
521
522/* multiprocessor communications interface (MPCI) table */
523
524rtems_mpci_table MPCI_table  = {
525  100000,                     /* default timeout value in ticks */
526  MAX_PACKET_SIZE,            /* maximum packet size */
527  Shm_Initialization,         /* initialization procedure   */
528  Shm_Get_packet,             /* get packet procedure       */
529  Shm_Return_packet,          /* return packet procedure    */
530  Shm_Send_packet,            /* packet send procedure      */
531  Shm_Receive_packet          /* packet receive procedure   */
532};
533
534#endif
535
536#ifdef __cplusplus
537}
538#endif
539
540#endif
541/* end of include file */
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