source: rtems/c/src/libchip/shmdr/shm_driver.h @ 12f86efd

4.104.114.84.95
Last change on this file since 12f86efd was 12f86efd, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 11, 1995 at 2:23:49 PM

minor clean up -- switched to memset for zero'ing SHM

  • Property mode set to 100644
File size: 19.5 KB
Line 
1/*  shm.h
2 *
3 *  This include file contains all the constants, structures,
4 *  and global variables for this RTEMS based shared memory
5 *  communications interface driver.
6 *
7 *  Processor board dependencies are in other files.
8 *
9 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
10 *  On-Line Applications Research Corporation (OAR).
11 *  All rights assigned to U.S. Government, 1994.
12 *
13 *  This material may be reproduced by or for the U.S. Government pursuant
14 *  to the copyright license under the clause at DFARS 252.227-7013.  This
15 *  notice must appear in all copies of this file and its derivatives.
16 *
17 *  shm.h,v 1.2 1995/05/09 20:23:03 joel Exp
18 */
19
20#ifndef __SHM_h
21#define __SHM_h
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/*  The information contained in the Node Status, Locked Queue, and
28 *  Envelope Control Blocks must be maintained in a NEUTRAL format.
29 *  Currently the neutral format may be selected as big or little
30 *  endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
31 *
32 *  It is CRITICAL to note that the neutral format can ONLY be
33 *  changed by modifying this file and recompiling the ENTIRE
34 *  SHM driver including ALL target specific support files.
35 *
36 *  The following table details the memory contents for the endian
37 *  field of the Node Status Control Block in the various
38 *  data format configurations (data is in hexadecimal):
39 *
40 *   NEUTRAL NATIVE BYTE 0  BYTE 1  BYTE 2  BYTE 3
41 *   ======= ====== ======  ======  ======  ======
42 *    BIG     BIG     00      00      00      01
43 *    BIG    LITTLE   10      00      00      00
44 *   LITTLE   BIG     01      00      00      00
45 *   LITTLE  LITTLE   00      00      00      10
46 *
47 *
48 *  NOTE: XXX
49 *                PORTABILITY OF LOCKING INSTRUCTIONS
50 *                ===================================
51 *            The locking mechanism described below is not
52 *            general enough.  Where the hardware supports
53 *            it we should use "atomic swap" instructions
54 *            so the values in the lock can be tailored to
55 *            support a CPU with only weak atomic memory
56 *            instructions.  There are combinations of
57 *            CPUs with inflexible atomic memory instructions
58 *            which appear to be incompatible.  For example,
59 *            the SPARClite instruction uses a byte which is
60 *            0xFF when locked.  The PA-RISC uses 1 to indicate
61 *            locked and 0 when unlocked.  These CPUs appear to
62 *            have incompatible lock instructions.  But
63 *            they could be used in a heterogenous system
64 *            with does not mix SPARCs and PA-RISCs.  For
65 *            example, the i386 and SPARC or i386 and SPARC
66 *            could work together.  The bottom line is that
67 *            not every CPU will work together using this
68 *            locking scheme.  There are supposed to be
69 *            algorithms to do this without hardware assist
70 *            and one of these should be incorporated into
71 *            the shared memory driver.
72 *
73 *            The most flexible scheme using the instructions
74 *            of the various CPUs for efficiency would be to use
75 *            "atomic swaps" wherever possible.  Make the lock
76 *            and unlock configurable much like BIG vs LITTLE
77 *            endian use of shared memory is now.  The values
78 *            of the lock could then reflect the "worst"
79 *            CPU in a system.  This still results in mixes
80 *            of CPUs which are incompatible.
81 *
82 *  The current locking mechanism is based upon the MC68020
83 *  "tas" instruction which is atomic.  All ports to other CPUs
84 *  comply with the restrictive placement of lock bit by this
85 *  instruction.  The lock bit is the most significant bit in a
86 *  big-endian rtems_unsigned32.  On other processors, the lock is
87 *  typically implemented via an atomic swap or atomic modify
88 *  bits type instruction.
89 */
90
91#define NEUTRAL_BIG
92
93#ifdef NEUTRAL_BIG
94#define SHM_BIG       0x00000001
95#define SHM_LITTLE    0x10000000
96#endif
97
98#ifdef NEUTRAL_LITTLE
99#define SHM_BIG       0x01000000
100#define SHM_LITTLE    0x00000010
101#endif
102
103/*
104 *  The following are the values used to fill in the lock field.  Some CPUs
105 *  are able to write only a single value into field.  By making the
106 *  lock and unlock values configurable, CPUs which support "atomic swap"
107 *  instructions can generally be made to work in any heterogeneous
108 *  configuration.  However, it is possible for two CPUs to be incompatible
109 *  in regards to the lock field values.  This occurs when two CPUs
110 *  which write only a single value to the field are used in a system
111 *  but the two CPUs write different incompatible values.
112 *
113 *  NOTE:  The following is a first attempt at defining values which
114 *         have a chance at working together.  The m68k should use
115 *         chk2 instead of tas to be less restrictive.  Target endian
116 *         problems (like the Force CPU386 which has (broken) big endian
117 *         view of the VMEbus address space) are not addressed yet.
118 */
119
120#if defined(i960)
121#define SHM_LOCK_VALUE    0x00000080
122#define SHM_UNLOCK_VALUE  0
123#elif defined(m68k)
124#define SHM_LOCK_VALUE    0x80000000
125#define SHM_UNLOCK_VALUE  0
126#define SHM_LOCK_VALUE    0x80000000
127#define SHM_UNLOCK_VALUE  0
128#elif defined(i386)
129#define SHM_LOCK_VALUE    0x80000000
130#define SHM_UNLOCK_VALUE  0
131#elif defined(hppa1_1)
132#define SHM_LOCK_VALUE    0
133#define SHM_UNLOCK_VALUE  1
134#elif defined(unix)
135#define SHM_LOCK_VALUE    0
136#define SHM_UNLOCK_VALUE  1
137#elif defined(no_cpu)               /* for this values are irrelevant */
138#define SHM_LOCK_VALUE    1
139#define SHM_UNLOCK_VALUE  0
140#endif
141
142#define Shm_Convert( value ) \
143  ((Shm_Configuration->convert) ? \
144    (*Shm_Configuration->convert)(value) : (value))
145
146/* constants */
147
148#define SHM_MASTER                  1     /* master initialization node */
149#define SHM_FIRST_NODE              1
150
151/* size constants */
152
153#define KILOBYTE          (1024)
154#define MEGABYTE          (1024*1024)
155
156/* inter-node interrupt values */
157
158#define NO_INTERRUPT            0     /* used for polled nodes */
159#define BYTE                    1
160#define WORD                    2
161#define LONG                    4
162
163/* operational mode constants -- used in SHM Configuration Table */
164#define POLLED_MODE             0
165#define INTR_MODE               1
166
167/* error codes */
168
169#define NO_ERROR                0
170#define SHM_NO_FREE_PKTS        0xf0000
171
172/* null pointers of different types */
173
174#define NULL_ENV_CB             ((Shm_Envelope_control *) 0)
175#define NULL_CONVERT            0
176
177/*
178 * size of stuff before preamble in envelope.
179 * It must be a constant since we will use it to generate MAX_PACKET_SIZE
180 */
181 
182#define SHM_ENVELOPE_PREFIX_OVERHEAD    (4 * sizeof(vol_u32))
183
184/*
185 *  The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long.
186 *  It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h.
187 */
188 
189#ifndef MAX_ENVELOPE_SIZE
190#define MAX_ENVELOPE_SIZE 0x180
191#endif
192
193#define MAX_PACKET_SIZE  (MAX_ENVELOPE_SIZE -               \
194                          SHM_ENVELOPE_PREFIX_OVERHEAD +    \
195                          sizeof(Shm_Envelope_preamble) +   \
196                          sizeof(Shm_Envelope_postamble))
197
198
199/* constants pertinent to Locked Queue routines */
200
201#define LQ_UNLOCKED              SHM_UNLOCK_VALUE
202#define LQ_LOCKED                SHM_LOCK_VALUE
203
204/* constants related to the Free Envelope Pool */
205
206#define FREE_ENV_POOL            0
207#define FREE_ENV_CB              (&Shm_Locked_queues[ FREE_ENV_POOL ])
208
209/*  The following are important when dealing with
210 *  the shared memory communications interface area.
211 *
212 *  NOTE: The starting address and length of the shared memory
213 *        is defined in a system dependent file.
214 */
215
216#define START_NS_CBS     ((void *)Shm_Configuration->base)
217#define START_LQ_CBS     ((START_NS_CBS) + \
218        ( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
219#define START_ENVELOPES  ( ((void *) START_LQ_CBS) + \
220        ( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
221#define END_SHMCI_AREA    ( (void *) START_ENVELOPES + \
222        ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
223#define END_SHARED_MEM   (START_NS_CBS+Shm_Configuration->length)
224
225/* macros */
226
227#define Shm_Is_master_node()  \
228  ( SHM_MASTER == Shm_Local_node )
229
230#define Shm_Free_envelope( ecb ) \
231  Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
232#define Shm_Allocate_envelope() \
233  Shm_Locked_queue_Get(FREE_ENV_CB)
234
235#define Shm_Initialize_receive_queue(node) \
236  Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
237
238#define Shm_Append_to_receive_queue(node, ecb) \
239  Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
240
241#define Shm_Envelope_control_to_packet_prefix_pointer(ecb)  \
242   ((void *)(ecb)->packet)
243
244#define Shm_Packet_prefix_to_envelope_control_pointer( pkt )   \
245   ((Shm_Envelope_control *)((rtems_unsigned8 *)(pkt) - \
246   (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD)))
247
248#define Shm_Build_preamble(ecb, node) \
249       (ecb)->Preamble.endian = Shm_Configuration->format
250
251#define Shm_Build_postamble( ecb )
252
253/* volatile types */
254
255typedef volatile rtems_unsigned8  vol_u8;
256typedef volatile rtems_unsigned32 vol_u32;
257
258/* shm control information */
259
260struct shm_info {
261  vol_u32 not_currently_used_0;
262  vol_u32 not_currently_used_1;
263  vol_u32 not_currently_used_2;
264  vol_u32 not_currently_used_3;
265};
266
267typedef struct {
268  /*byte start_of_text;*/
269  vol_u32 endian;
270  vol_u32 not_currently_used_0;
271  vol_u32 not_currently_used_1;
272  vol_u32 not_currently_used_2;
273} Shm_Envelope_preamble;
274
275typedef struct {
276} Shm_Envelope_postamble;
277
278/* WARNING! If you change this structure, don't forget to change
279 *          SHM_ENVELOPE_PREFIX_OVERHEAD and
280 *          Shm_Packet_prefix_to_envelope_control_pointer() above.
281 */
282
283/*  This comment block describes the contents of each field
284 *  of the Envelope Control Block:
285 *
286 *  next      - The index of the next envelope on this queue.
287 *  queue     - The index of the queue this envelope is on.
288 *  index     - The index of this envelope.
289 *  Preamble  - Generic packet preamble.  One day this structure
290 *              could be enhanced to contain routing information.
291 *  packet    - RTEMS MPCI packet.  Untouched by SHM Driver
292 *              other than copying and format conversion as
293 *              documented in the RTEMS User's Guide.
294 *  Postamble - Generic packet postamble.  One day this structure
295 *              could be enhanced to contain checksum information.
296 */
297
298typedef struct {
299  vol_u32           next;     /* next envelope on queue       */
300  vol_u32           queue;    /* queue on which this resides  */
301  vol_u32           index;    /* index into array of envelopes*/
302  vol_u32           pad0;     /* insure the next one is aligned */
303  Shm_Envelope_preamble    Preamble; /* header information           */
304  vol_u8            packet[MAX_PACKET_SIZE]; /* RTEMS INFO    */
305  Shm_Envelope_postamble   Postamble;/* trailer information          */
306} Shm_Envelope_control;
307
308/*  This comment block describes the contents of each field
309 *  of the Locked Queue Control Block:
310 *
311 *  lock      - Lock used to insure mutually exclusive access.
312 *  front     - Index of first envelope on queue.  This field
313 *              is used to remove head of queue (receive).
314 *  rear      - Index of last envelope on queue.  This field
315 *              is used to add evelope to queue (send).
316 *  owner     - The node number of the recipient (owning) node.
317 *              RTEMS does not use the node number zero (0).
318 *              The zero node is used by the SHM Driver for the
319 *              Free Envelope Queue shared by all nodes.
320 */
321
322typedef struct {
323  vol_u32 lock;  /* lock field for this queue    */
324  vol_u32 front; /* first envelope on queue      */
325  vol_u32 rear;  /* last envelope on queue       */
326  vol_u32 owner; /* receiving (i.e. owning) node */
327} Shm_Locked_queue_Control;
328
329/*  This comment block describes the contents of each field
330 *  of the Node Status Control Block:
331 *
332 *  status    - Node status.  Current values are Pending Initialization,
333 *              Initialization Complete, and Active Node.  Other values
334 *              could be added to enhance fault tolerance.
335 *  error     - Zero if the node has not failed.  Otherwise,
336 *              this field contains a status indicating the
337 *              failure reason.
338 *  int_address, int_value, and int_length
339 *            - These field are the Interrupt Information table
340 *              for this node in neutral format.  This is how
341 *              each node knows how to generate interrupts.
342 */
343
344typedef struct {
345  vol_u32  status;         /* node status information     */
346  vol_u32  error;          /* fatal error code            */
347  vol_u32  int_address;    /* write here for interrupt    */
348  vol_u32  int_value;      /* this value causes interrupt */
349  vol_u32  int_length;     /* for this length (0,1,2,4)   */
350  vol_u32  not_currently_used_0;
351  vol_u32  not_currently_used_1;
352  vol_u32  not_currently_used_2;
353} Shm_Node_status_control;
354
355/*  This comment block describes the contents of each field
356 *  of the Interrupt Information Table.  This table describes
357 *  how another node can generate an interrupt to this node.
358 *  This information is target board dependent.  If the
359 *  SHM Driver is in POLLED_MODE, then all fields should
360 *  be initialized to NO_INTERRUPT.
361 *
362 *  address   - The address to which another node should
363 *              write to cause an interrupt.
364 *  value     - The value which must be written
365 *  length    - The size of the value to write.  Valid
366 *              values are BYTE, WORD, and LONG.
367 *
368 *  NOTE:  The Node Status Control Block contains this
369 *         information in neutral format and not in a
370 *         structure to avoid potential alignment problems.
371 */
372
373typedef struct {
374  vol_u32 *address;        /* write here for interrupt    */
375  vol_u32  value;          /* this value causes interrupt */
376  vol_u32  length;         /* for this length (0,1,2,4)   */
377} Shm_Interrupt_information;
378
379/*  SHM Configuration Table
380 *
381 *  This comment block describes the contents of each field
382 *  of the SHM Configuration Table.
383 *
384 *  base       - The base address of the shared memory.  This
385 *               address may be specific to this node.
386 *  length     - The length of the shared memory in bytes.
387 *  format     - The natural format for rtems_unsigned32's in the
388 *               shared memory.  Valid values are currently
389 *               only SHM_LITTLE and SHM_BIG.
390 *  convert    - The address of the routine which converts
391 *               between neutral and local format.
392 *  poll_intr  - The operational mode of the driver.  Some
393 *               target boards may not provide hardware for
394 *               an interprocessor interrupt.  If POLLED_MODE
395 *               is selected, the SHM driver will install a
396 *               wrapper around the Clock_isr() to poll for
397 *               incoming packets.  Throughput is dependent
398 *               on the time between clock interrupts.
399 *               Valid values are POLLED_MODE and INTR_MODE.
400 *  cause_intr - This is the address of the routine used to
401 *               write to a particular address and cause an
402 *               interrupt on another node.  This routine
403 *               may need to be target dependent if something
404 *               other than a normal write from C does not work.
405 *  Intr       - This structure describes the operation required
406 *               to cause an interrupt to this node.  The actual
407 *               contents of this structure are described above.
408 */
409
410struct shm_config_info {
411  vol_u32           *base;     /* base address of SHM         */
412  vol_u32            length;   /* length (in bytes) of SHM    */
413  vol_u32            format;   /* SHM is big or little endian */
414  vol_u32          (*convert)();/* neutral conversion routine */
415  vol_u32            poll_intr;/* POLLED or INTR driven mode  */
416  void             (*cause_intr)( rtems_unsigned32 );
417  Shm_Interrupt_information   Intr;     /* cause intr information      */
418};
419
420typedef struct shm_config_info shm_config_table;
421
422/* global variables */
423
424#ifdef _SHM_INIT
425#define SHM_EXTERN
426#else
427#define SHM_EXTERN extern
428#endif
429
430SHM_EXTERN shm_config_table             *Shm_Configuration;
431SHM_EXTERN Shm_Interrupt_information     Shm_Interrupt_table[16];
432SHM_EXTERN Shm_Node_status_control      *Shm_Node_statuses;
433SHM_EXTERN Shm_Locked_queue_Control     *Shm_Locked_queues;
434SHM_EXTERN Shm_Envelope_control         *Shm_Envelopes;
435SHM_EXTERN rtems_configuration_table    *Shm_RTEMS_Configuration;
436SHM_EXTERN rtems_multiprocessing_table  *Shm_RTEMS_MP_Configuration;
437SHM_EXTERN rtems_unsigned32              Shm_Receive_message_count;
438SHM_EXTERN rtems_unsigned32              Shm_Null_message_count;
439SHM_EXTERN rtems_unsigned32              Shm_Interrupt_count;
440SHM_EXTERN rtems_unsigned32              Shm_Local_node;
441SHM_EXTERN Shm_Locked_queue_Control      *Shm_Local_receive_queue;
442SHM_EXTERN Shm_Node_status_control       *Shm_Local_node_status;
443SHM_EXTERN rtems_unsigned32              Shm_isrstat;
444                                                     /* reported by shmdr */
445
446SHM_EXTERN rtems_unsigned32 Shm_Pending_initialization;
447SHM_EXTERN rtems_unsigned32 Shm_Initialization_complete;
448SHM_EXTERN rtems_unsigned32 Shm_Active_node;
449
450SHM_EXTERN rtems_unsigned32 Shm_Maximum_nodes;
451SHM_EXTERN rtems_unsigned32 Shm_Maximum_envelopes;
452
453SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_End_of_list;
454SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_Not_on_list;
455
456/* functions */
457
458/* locked queue routines */
459void           Shm_Locked_queue_Add(
460                  Shm_Locked_queue_Control *, Shm_Envelope_control * );
461Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
462void           Shm_Locked_queue_Initialize(
463                  Shm_Locked_queue_Control *, rtems_unsigned32 );
464            /* Shm_Initialize_lock is CPU dependent */
465            /* Shm_Lock is CPU dependent */
466            /* Shm_Unlock is CPU dependent */
467
468/* portable routines */
469void           Init_env_pool();
470void           Shm_Print_statistics( void );
471void           MPCI_Fatal( rtems_unsigned32 );
472rtems_task     Shm_Cause_interrupt( rtems_unsigned32 );
473void           Shm_Poll();
474void           Shm_setclockvec();
475void           Shm_Convert_packet( rtems_packet_prefix * );
476
477/* CPU specific routines are inlined in shmcpu.h */
478
479/* target specific routines */
480void          *Shm_Convert_address( void * );
481void           Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );
482void           Shm_isr();
483void           Shm_setvec( void );
484
485void           Shm_Initialize_lock( Shm_Locked_queue_Control * );
486void           Shm_Lock( Shm_Locked_queue_Control * );
487void           Shm_Unlock( Shm_Locked_queue_Control * );
488
489/* MPCI entry points */
490rtems_mpci_entry Shm_Get_packet(
491  rtems_packet_prefix **
492);
493
494rtems_mpci_entry Shm_Initialization(
495  rtems_configuration_table   *configuration,
496  rtems_cpu_table             *cpu_configuration,
497  rtems_multiprocessing_table *mp_configuration
498);
499
500rtems_mpci_entry Shm_Receive_packet(
501  rtems_packet_prefix **
502);
503
504rtems_mpci_entry Shm_Return_packet(
505  rtems_packet_prefix *
506);
507
508rtems_mpci_entry Shm_Send_packet(
509  rtems_unsigned32,
510  rtems_packet_prefix *
511);
512
513extern rtems_mpci_table MPCI_table;
514
515#ifdef _SHM_INIT
516
517/* multiprocessor communications interface (MPCI) table */
518
519rtems_mpci_table MPCI_table  = {
520  100000,                     /* default timeout value in ticks */
521  Shm_Initialization,         /* initialization procedure   */
522  Shm_Get_packet,             /* get packet procedure       */
523  Shm_Return_packet,          /* return packet procedure    */
524  Shm_Send_packet,            /* packet send procedure      */
525  Shm_Receive_packet          /* packet receive procedure   */
526};
527
528#endif
529
530#ifdef __cplusplus
531}
532#endif
533
534#endif
535/* end of include file */
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