[48bfd992] | 1 | /* shm_driver.h |
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[ac7d5ef0] | 2 | * |
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| 3 | * This include file contains all the constants, structures, |
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| 4 | * and global variables for this RTEMS based shared memory |
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| 5 | * communications interface driver. |
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| 6 | * |
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| 7 | * Processor board dependencies are in other files. |
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| 8 | * |
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[a29bf16b] | 9 | * COPYRIGHT (c) 1989-2007. |
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[ac7d5ef0] | 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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[98e4ebf5] | 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[4e89a12] | 14 | * http://www.rtems.com/license/LICENSE. |
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[ac7d5ef0] | 15 | * |
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[3235ad9] | 16 | * $Id$ |
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[ac7d5ef0] | 17 | */ |
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| 18 | |
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| 19 | #ifndef __SHM_h |
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| 20 | #define __SHM_h |
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| 21 | |
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[4caeb10] | 22 | #include <rtems/clockdrv.h> |
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[b06e68ef] | 23 | |
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[ac7d5ef0] | 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |
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| 28 | /* The information contained in the Node Status, Locked Queue, and |
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| 29 | * Envelope Control Blocks must be maintained in a NEUTRAL format. |
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| 30 | * Currently the neutral format may be selected as big or little |
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| 31 | * endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE. |
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| 32 | * |
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| 33 | * It is CRITICAL to note that the neutral format can ONLY be |
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| 34 | * changed by modifying this file and recompiling the ENTIRE |
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| 35 | * SHM driver including ALL target specific support files. |
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| 36 | * |
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| 37 | * The following table details the memory contents for the endian |
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| 38 | * field of the Node Status Control Block in the various |
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| 39 | * data format configurations (data is in hexadecimal): |
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| 40 | * |
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| 41 | * NEUTRAL NATIVE BYTE 0 BYTE 1 BYTE 2 BYTE 3 |
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| 42 | * ======= ====== ====== ====== ====== ====== |
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| 43 | * BIG BIG 00 00 00 01 |
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| 44 | * BIG LITTLE 10 00 00 00 |
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| 45 | * LITTLE BIG 01 00 00 00 |
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| 46 | * LITTLE LITTLE 00 00 00 10 |
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| 47 | * |
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| 48 | * |
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| 49 | * NOTE: XXX |
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| 50 | * PORTABILITY OF LOCKING INSTRUCTIONS |
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| 51 | * =================================== |
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| 52 | * The locking mechanism described below is not |
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| 53 | * general enough. Where the hardware supports |
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| 54 | * it we should use "atomic swap" instructions |
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| 55 | * so the values in the lock can be tailored to |
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| 56 | * support a CPU with only weak atomic memory |
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| 57 | * instructions. There are combinations of |
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| 58 | * CPUs with inflexible atomic memory instructions |
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| 59 | * which appear to be incompatible. For example, |
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| 60 | * the SPARClite instruction uses a byte which is |
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| 61 | * 0xFF when locked. The PA-RISC uses 1 to indicate |
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| 62 | * locked and 0 when unlocked. These CPUs appear to |
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| 63 | * have incompatible lock instructions. But |
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| 64 | * they could be used in a heterogenous system |
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| 65 | * with does not mix SPARCs and PA-RISCs. For |
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| 66 | * example, the i386 and SPARC or i386 and SPARC |
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| 67 | * could work together. The bottom line is that |
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| 68 | * not every CPU will work together using this |
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| 69 | * locking scheme. There are supposed to be |
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| 70 | * algorithms to do this without hardware assist |
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| 71 | * and one of these should be incorporated into |
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| 72 | * the shared memory driver. |
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| 73 | * |
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| 74 | * The most flexible scheme using the instructions |
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| 75 | * of the various CPUs for efficiency would be to use |
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| 76 | * "atomic swaps" wherever possible. Make the lock |
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| 77 | * and unlock configurable much like BIG vs LITTLE |
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| 78 | * endian use of shared memory is now. The values |
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| 79 | * of the lock could then reflect the "worst" |
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| 80 | * CPU in a system. This still results in mixes |
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| 81 | * of CPUs which are incompatible. |
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| 82 | * |
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| 83 | * The current locking mechanism is based upon the MC68020 |
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| 84 | * "tas" instruction which is atomic. All ports to other CPUs |
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| 85 | * comply with the restrictive placement of lock bit by this |
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| 86 | * instruction. The lock bit is the most significant bit in a |
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[ee4f57d] | 87 | * big-endian uint32_t . On other processors, the lock is |
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[ac7d5ef0] | 88 | * typically implemented via an atomic swap or atomic modify |
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| 89 | * bits type instruction. |
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| 90 | */ |
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| 91 | |
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| 92 | #define NEUTRAL_BIG |
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| 93 | |
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| 94 | #ifdef NEUTRAL_BIG |
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| 95 | #define SHM_BIG 0x00000001 |
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| 96 | #define SHM_LITTLE 0x10000000 |
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| 97 | #endif |
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| 98 | |
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| 99 | #ifdef NEUTRAL_LITTLE |
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| 100 | #define SHM_BIG 0x01000000 |
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| 101 | #define SHM_LITTLE 0x00000010 |
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| 102 | #endif |
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| 103 | |
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| 104 | /* |
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| 105 | * The following are the values used to fill in the lock field. Some CPUs |
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| 106 | * are able to write only a single value into field. By making the |
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| 107 | * lock and unlock values configurable, CPUs which support "atomic swap" |
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| 108 | * instructions can generally be made to work in any heterogeneous |
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| 109 | * configuration. However, it is possible for two CPUs to be incompatible |
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| 110 | * in regards to the lock field values. This occurs when two CPUs |
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| 111 | * which write only a single value to the field are used in a system |
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| 112 | * but the two CPUs write different incompatible values. |
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| 113 | * |
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| 114 | * NOTE: The following is a first attempt at defining values which |
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| 115 | * have a chance at working together. The m68k should use |
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| 116 | * chk2 instead of tas to be less restrictive. Target endian |
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| 117 | * problems (like the Force CPU386 which has (broken) big endian |
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| 118 | * view of the VMEbus address space) are not addressed yet. |
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| 119 | */ |
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| 120 | |
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[7452b855] | 121 | #if defined(__mc68000__) |
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[ac7d5ef0] | 122 | #define SHM_LOCK_VALUE 0x80000000 |
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| 123 | #define SHM_UNLOCK_VALUE 0 |
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| 124 | #define SHM_LOCK_VALUE 0x80000000 |
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| 125 | #define SHM_UNLOCK_VALUE 0 |
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[3ec7bfc] | 126 | #elif defined(__i386__) |
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[ac7d5ef0] | 127 | #define SHM_LOCK_VALUE 0x80000000 |
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| 128 | #define SHM_UNLOCK_VALUE 0 |
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[3ec7bfc] | 129 | #elif defined(__mips__) |
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[3d07c8b] | 130 | #define SHM_LOCK_VALUE 0x80000000 |
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| 131 | #define SHM_UNLOCK_VALUE 0 |
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[3ec7bfc] | 132 | #elif defined(__hppa__) |
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[ac7d5ef0] | 133 | #define SHM_LOCK_VALUE 0 |
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| 134 | #define SHM_UNLOCK_VALUE 1 |
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[3ec7bfc] | 135 | #elif defined(__PPC__) |
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[4ef9e99] | 136 | #define SHM_LOCK_VALUE 1 |
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| 137 | #define SHM_UNLOCK_VALUE 0 |
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[3ec7bfc] | 138 | #elif defined(__unix__) |
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[ac7d5ef0] | 139 | #define SHM_LOCK_VALUE 0 |
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| 140 | #define SHM_UNLOCK_VALUE 1 |
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[cd872d9] | 141 | #elif defined(_AM29K) |
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| 142 | #define SHM_LOCK_VALUE 0 |
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| 143 | #define SHM_UNLOCK_VALUE 1 |
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[8faa4a5] | 144 | #elif defined(__sparc__) |
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| 145 | #define SHM_LOCK_VALUE 1 |
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| 146 | #define SHM_UNLOCK_VALUE 0 |
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[ac7d5ef0] | 147 | #elif defined(no_cpu) /* for this values are irrelevant */ |
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| 148 | #define SHM_LOCK_VALUE 1 |
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| 149 | #define SHM_UNLOCK_VALUE 0 |
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[3d07c8b] | 150 | #else |
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[48bfd992] | 151 | #error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture" |
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[ac7d5ef0] | 152 | #endif |
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| 153 | |
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| 154 | #define Shm_Convert( value ) \ |
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| 155 | ((Shm_Configuration->convert) ? \ |
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| 156 | (*Shm_Configuration->convert)(value) : (value)) |
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| 157 | |
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| 158 | /* constants */ |
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| 159 | |
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| 160 | #define SHM_MASTER 1 /* master initialization node */ |
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| 161 | #define SHM_FIRST_NODE 1 |
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| 162 | |
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| 163 | /* size constants */ |
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| 164 | |
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| 165 | #define KILOBYTE (1024) |
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| 166 | #define MEGABYTE (1024*1024) |
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| 167 | |
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| 168 | /* inter-node interrupt values */ |
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| 169 | |
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| 170 | #define NO_INTERRUPT 0 /* used for polled nodes */ |
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| 171 | #define BYTE 1 |
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| 172 | #define WORD 2 |
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| 173 | #define LONG 4 |
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| 174 | |
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| 175 | /* operational mode constants -- used in SHM Configuration Table */ |
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| 176 | #define POLLED_MODE 0 |
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| 177 | #define INTR_MODE 1 |
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| 178 | |
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| 179 | /* error codes */ |
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| 180 | |
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| 181 | #define NO_ERROR 0 |
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| 182 | #define SHM_NO_FREE_PKTS 0xf0000 |
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| 183 | |
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| 184 | /* null pointers of different types */ |
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| 185 | |
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| 186 | #define NULL_ENV_CB ((Shm_Envelope_control *) 0) |
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| 187 | #define NULL_CONVERT 0 |
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[12f86efd] | 188 | |
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| 189 | /* |
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| 190 | * size of stuff before preamble in envelope. |
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| 191 | * It must be a constant since we will use it to generate MAX_PACKET_SIZE |
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| 192 | */ |
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[a3d3d9a] | 193 | |
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[12f86efd] | 194 | #define SHM_ENVELOPE_PREFIX_OVERHEAD (4 * sizeof(vol_u32)) |
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| 195 | |
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| 196 | /* |
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| 197 | * The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long. |
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| 198 | * It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h. |
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| 199 | */ |
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[a3d3d9a] | 200 | |
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[12f86efd] | 201 | #ifndef MAX_ENVELOPE_SIZE |
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| 202 | #define MAX_ENVELOPE_SIZE 0x180 |
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[ac7d5ef0] | 203 | #endif |
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| 204 | |
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[12f86efd] | 205 | #define MAX_PACKET_SIZE (MAX_ENVELOPE_SIZE - \ |
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| 206 | SHM_ENVELOPE_PREFIX_OVERHEAD + \ |
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| 207 | sizeof(Shm_Envelope_preamble) + \ |
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| 208 | sizeof(Shm_Envelope_postamble)) |
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[ac7d5ef0] | 209 | |
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| 210 | |
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| 211 | /* constants pertinent to Locked Queue routines */ |
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| 212 | |
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| 213 | #define LQ_UNLOCKED SHM_UNLOCK_VALUE |
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| 214 | #define LQ_LOCKED SHM_LOCK_VALUE |
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| 215 | |
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| 216 | /* constants related to the Free Envelope Pool */ |
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| 217 | |
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| 218 | #define FREE_ENV_POOL 0 |
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| 219 | #define FREE_ENV_CB (&Shm_Locked_queues[ FREE_ENV_POOL ]) |
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| 220 | |
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| 221 | /* The following are important when dealing with |
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| 222 | * the shared memory communications interface area. |
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| 223 | * |
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| 224 | * NOTE: The starting address and length of the shared memory |
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| 225 | * is defined in a system dependent file. |
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| 226 | */ |
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| 227 | |
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| 228 | #define START_NS_CBS ((void *)Shm_Configuration->base) |
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| 229 | #define START_LQ_CBS ((START_NS_CBS) + \ |
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[534c893] | 230 | ( (sizeof (Shm_Node_status_control)) * (SHM_MAXIMUM_NODES + 1) ) ) |
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[ac7d5ef0] | 231 | #define START_ENVELOPES ( ((void *) START_LQ_CBS) + \ |
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[534c893] | 232 | ( (sizeof (Shm_Locked_queue_Control)) * (SHM_MAXIMUM_NODES + 1) ) ) |
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[ac7d5ef0] | 233 | #define END_SHMCI_AREA ( (void *) START_ENVELOPES + \ |
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| 234 | ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) ) |
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| 235 | #define END_SHARED_MEM (START_NS_CBS+Shm_Configuration->length) |
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| 236 | |
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| 237 | /* macros */ |
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| 238 | |
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[12f86efd] | 239 | #define Shm_Is_master_node() \ |
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[534c893] | 240 | ( SHM_MASTER ==_Configuration_MP_table-> node ) |
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[ac7d5ef0] | 241 | |
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| 242 | #define Shm_Free_envelope( ecb ) \ |
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| 243 | Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) ) |
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| 244 | #define Shm_Allocate_envelope() \ |
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| 245 | Shm_Locked_queue_Get(FREE_ENV_CB) |
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| 246 | |
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| 247 | #define Shm_Initialize_receive_queue(node) \ |
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| 248 | Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node ) |
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| 249 | |
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| 250 | #define Shm_Append_to_receive_queue(node, ecb) \ |
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| 251 | Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) ) |
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| 252 | |
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| 253 | #define Shm_Envelope_control_to_packet_prefix_pointer(ecb) \ |
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| 254 | ((void *)(ecb)->packet) |
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| 255 | |
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| 256 | #define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \ |
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[509fec9c] | 257 | ((Shm_Envelope_control *)((uint8_t*)(pkt) - \ |
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[12f86efd] | 258 | (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD))) |
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[ac7d5ef0] | 259 | |
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| 260 | #define Shm_Build_preamble(ecb, node) \ |
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| 261 | (ecb)->Preamble.endian = Shm_Configuration->format |
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| 262 | |
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| 263 | #define Shm_Build_postamble( ecb ) |
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| 264 | |
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[12f86efd] | 265 | /* volatile types */ |
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[ac7d5ef0] | 266 | |
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[ee4f57d] | 267 | typedef volatile uint8_t vol_u8; |
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| 268 | typedef volatile uint32_t vol_u32; |
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[ac7d5ef0] | 269 | |
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| 270 | /* shm control information */ |
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| 271 | |
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| 272 | struct shm_info { |
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| 273 | vol_u32 not_currently_used_0; |
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| 274 | vol_u32 not_currently_used_1; |
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| 275 | vol_u32 not_currently_used_2; |
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| 276 | vol_u32 not_currently_used_3; |
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| 277 | }; |
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| 278 | |
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| 279 | typedef struct { |
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| 280 | /*byte start_of_text;*/ |
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| 281 | vol_u32 endian; |
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| 282 | vol_u32 not_currently_used_0; |
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| 283 | vol_u32 not_currently_used_1; |
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| 284 | vol_u32 not_currently_used_2; |
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| 285 | } Shm_Envelope_preamble; |
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| 286 | |
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| 287 | typedef struct { |
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[12f86efd] | 288 | } Shm_Envelope_postamble; |
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[ac7d5ef0] | 289 | |
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| 290 | /* WARNING! If you change this structure, don't forget to change |
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[12f86efd] | 291 | * SHM_ENVELOPE_PREFIX_OVERHEAD and |
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[ac7d5ef0] | 292 | * Shm_Packet_prefix_to_envelope_control_pointer() above. |
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| 293 | */ |
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| 294 | |
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| 295 | /* This comment block describes the contents of each field |
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| 296 | * of the Envelope Control Block: |
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| 297 | * |
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| 298 | * next - The index of the next envelope on this queue. |
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| 299 | * queue - The index of the queue this envelope is on. |
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| 300 | * index - The index of this envelope. |
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| 301 | * Preamble - Generic packet preamble. One day this structure |
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| 302 | * could be enhanced to contain routing information. |
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| 303 | * packet - RTEMS MPCI packet. Untouched by SHM Driver |
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| 304 | * other than copying and format conversion as |
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| 305 | * documented in the RTEMS User's Guide. |
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| 306 | * Postamble - Generic packet postamble. One day this structure |
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| 307 | * could be enhanced to contain checksum information. |
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| 308 | */ |
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| 309 | |
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| 310 | typedef struct { |
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| 311 | vol_u32 next; /* next envelope on queue */ |
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| 312 | vol_u32 queue; /* queue on which this resides */ |
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| 313 | vol_u32 index; /* index into array of envelopes*/ |
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| 314 | vol_u32 pad0; /* insure the next one is aligned */ |
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| 315 | Shm_Envelope_preamble Preamble; /* header information */ |
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| 316 | vol_u8 packet[MAX_PACKET_SIZE]; /* RTEMS INFO */ |
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[12f86efd] | 317 | Shm_Envelope_postamble Postamble;/* trailer information */ |
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[ac7d5ef0] | 318 | } Shm_Envelope_control; |
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| 319 | |
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| 320 | /* This comment block describes the contents of each field |
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| 321 | * of the Locked Queue Control Block: |
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| 322 | * |
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| 323 | * lock - Lock used to insure mutually exclusive access. |
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| 324 | * front - Index of first envelope on queue. This field |
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| 325 | * is used to remove head of queue (receive). |
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| 326 | * rear - Index of last envelope on queue. This field |
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| 327 | * is used to add evelope to queue (send). |
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| 328 | * owner - The node number of the recipient (owning) node. |
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| 329 | * RTEMS does not use the node number zero (0). |
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| 330 | * The zero node is used by the SHM Driver for the |
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| 331 | * Free Envelope Queue shared by all nodes. |
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| 332 | */ |
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| 333 | |
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| 334 | typedef struct { |
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| 335 | vol_u32 lock; /* lock field for this queue */ |
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| 336 | vol_u32 front; /* first envelope on queue */ |
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| 337 | vol_u32 rear; /* last envelope on queue */ |
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| 338 | vol_u32 owner; /* receiving (i.e. owning) node */ |
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| 339 | } Shm_Locked_queue_Control; |
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| 340 | |
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| 341 | /* This comment block describes the contents of each field |
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| 342 | * of the Node Status Control Block: |
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| 343 | * |
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| 344 | * status - Node status. Current values are Pending Initialization, |
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| 345 | * Initialization Complete, and Active Node. Other values |
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| 346 | * could be added to enhance fault tolerance. |
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| 347 | * error - Zero if the node has not failed. Otherwise, |
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| 348 | * this field contains a status indicating the |
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| 349 | * failure reason. |
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| 350 | * int_address, int_value, and int_length |
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| 351 | * - These field are the Interrupt Information table |
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| 352 | * for this node in neutral format. This is how |
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| 353 | * each node knows how to generate interrupts. |
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| 354 | */ |
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| 355 | |
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| 356 | typedef struct { |
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| 357 | vol_u32 status; /* node status information */ |
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| 358 | vol_u32 error; /* fatal error code */ |
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| 359 | vol_u32 int_address; /* write here for interrupt */ |
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| 360 | vol_u32 int_value; /* this value causes interrupt */ |
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| 361 | vol_u32 int_length; /* for this length (0,1,2,4) */ |
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| 362 | vol_u32 not_currently_used_0; |
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| 363 | vol_u32 not_currently_used_1; |
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| 364 | vol_u32 not_currently_used_2; |
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| 365 | } Shm_Node_status_control; |
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| 366 | |
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| 367 | /* This comment block describes the contents of each field |
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| 368 | * of the Interrupt Information Table. This table describes |
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| 369 | * how another node can generate an interrupt to this node. |
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| 370 | * This information is target board dependent. If the |
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| 371 | * SHM Driver is in POLLED_MODE, then all fields should |
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| 372 | * be initialized to NO_INTERRUPT. |
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| 373 | * |
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| 374 | * address - The address to which another node should |
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| 375 | * write to cause an interrupt. |
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| 376 | * value - The value which must be written |
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| 377 | * length - The size of the value to write. Valid |
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| 378 | * values are BYTE, WORD, and LONG. |
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| 379 | * |
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| 380 | * NOTE: The Node Status Control Block contains this |
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| 381 | * information in neutral format and not in a |
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| 382 | * structure to avoid potential alignment problems. |
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| 383 | */ |
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| 384 | |
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| 385 | typedef struct { |
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| 386 | vol_u32 *address; /* write here for interrupt */ |
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| 387 | vol_u32 value; /* this value causes interrupt */ |
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| 388 | vol_u32 length; /* for this length (0,1,2,4) */ |
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| 389 | } Shm_Interrupt_information; |
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| 390 | |
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| 391 | /* SHM Configuration Table |
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| 392 | * |
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| 393 | * This comment block describes the contents of each field |
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| 394 | * of the SHM Configuration Table. |
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| 395 | * |
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| 396 | * base - The base address of the shared memory. This |
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| 397 | * address may be specific to this node. |
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| 398 | * length - The length of the shared memory in bytes. |
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[ee4f57d] | 399 | * format - The natural format for uint32_t 's in the |
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[ac7d5ef0] | 400 | * shared memory. Valid values are currently |
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| 401 | * only SHM_LITTLE and SHM_BIG. |
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| 402 | * convert - The address of the routine which converts |
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| 403 | * between neutral and local format. |
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| 404 | * poll_intr - The operational mode of the driver. Some |
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| 405 | * target boards may not provide hardware for |
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| 406 | * an interprocessor interrupt. If POLLED_MODE |
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[5c980d0] | 407 | * is selected, the SHM driver will use a |
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| 408 | * Classiv API Timer instance to poll for |
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[ac7d5ef0] | 409 | * incoming packets. Throughput is dependent |
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| 410 | * on the time between clock interrupts. |
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| 411 | * Valid values are POLLED_MODE and INTR_MODE. |
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| 412 | * cause_intr - This is the address of the routine used to |
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| 413 | * write to a particular address and cause an |
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| 414 | * interrupt on another node. This routine |
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| 415 | * may need to be target dependent if something |
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| 416 | * other than a normal write from C does not work. |
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| 417 | * Intr - This structure describes the operation required |
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| 418 | * to cause an interrupt to this node. The actual |
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| 419 | * contents of this structure are described above. |
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| 420 | */ |
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| 421 | |
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| 422 | struct shm_config_info { |
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| 423 | vol_u32 *base; /* base address of SHM */ |
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| 424 | vol_u32 length; /* length (in bytes) of SHM */ |
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| 425 | vol_u32 format; /* SHM is big or little endian */ |
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[aec17f1] | 426 | uint32_t (*convert)( uint32_t );/* neutral conversion routine */ |
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[ac7d5ef0] | 427 | vol_u32 poll_intr;/* POLLED or INTR driven mode */ |
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[509fec9c] | 428 | void (*cause_intr)( uint32_t); |
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[ac7d5ef0] | 429 | Shm_Interrupt_information Intr; /* cause intr information */ |
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| 430 | }; |
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| 431 | |
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| 432 | typedef struct shm_config_info shm_config_table; |
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| 433 | |
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[534c893] | 434 | #define SHM_MAXIMUM_NODES Multiprocessing_configuration.maximum_nodes |
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| 435 | |
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[ac7d5ef0] | 436 | /* global variables */ |
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| 437 | |
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| 438 | #ifdef _SHM_INIT |
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| 439 | #define SHM_EXTERN |
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| 440 | #else |
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| 441 | #define SHM_EXTERN extern |
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| 442 | #endif |
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| 443 | |
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| 444 | SHM_EXTERN shm_config_table *Shm_Configuration; |
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[f5674938] | 445 | SHM_EXTERN Shm_Interrupt_information *Shm_Interrupt_table; |
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[ac7d5ef0] | 446 | SHM_EXTERN Shm_Node_status_control *Shm_Node_statuses; |
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| 447 | SHM_EXTERN Shm_Locked_queue_Control *Shm_Locked_queues; |
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| 448 | SHM_EXTERN Shm_Envelope_control *Shm_Envelopes; |
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[534c893] | 449 | SHM_EXTERN uint32_t Shm_Receive_message_count; |
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| 450 | SHM_EXTERN uint32_t Shm_Null_message_count; |
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| 451 | SHM_EXTERN uint32_t Shm_Interrupt_count; |
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| 452 | SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue; |
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| 453 | SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status; |
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| 454 | SHM_EXTERN uint32_t Shm_isrstat; |
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[ac7d5ef0] | 455 | /* reported by shmdr */ |
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| 456 | |
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[ee4f57d] | 457 | SHM_EXTERN uint32_t Shm_Pending_initialization; |
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| 458 | SHM_EXTERN uint32_t Shm_Initialization_complete; |
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| 459 | SHM_EXTERN uint32_t Shm_Active_node; |
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[ac7d5ef0] | 460 | |
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[ee4f57d] | 461 | SHM_EXTERN uint32_t Shm_Maximum_envelopes; |
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[ac7d5ef0] | 462 | |
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[ee4f57d] | 463 | SHM_EXTERN uint32_t Shm_Locked_queue_End_of_list; |
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| 464 | SHM_EXTERN uint32_t Shm_Locked_queue_Not_on_list; |
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[ac7d5ef0] | 465 | |
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| 466 | /* functions */ |
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| 467 | |
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| 468 | /* locked queue routines */ |
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| 469 | void Shm_Locked_queue_Add( |
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| 470 | Shm_Locked_queue_Control *, Shm_Envelope_control * ); |
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| 471 | Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * ); |
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| 472 | void Shm_Locked_queue_Initialize( |
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[509fec9c] | 473 | Shm_Locked_queue_Control *, uint32_t); |
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[ac7d5ef0] | 474 | /* Shm_Initialize_lock is CPU dependent */ |
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| 475 | /* Shm_Lock is CPU dependent */ |
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| 476 | /* Shm_Unlock is CPU dependent */ |
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| 477 | |
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| 478 | /* portable routines */ |
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[aec17f1] | 479 | void Init_env_pool( void ); |
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[ac7d5ef0] | 480 | void Shm_Print_statistics( void ); |
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[e8d4c797] | 481 | void MPCI_Fatal( Internal_errors_Source, bool, uint32_t); |
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[aec17f1] | 482 | rtems_task Shm_Cause_interrupt( uint32_t ); |
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[5c980d0] | 483 | void Shm_install_timer( void ); |
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[ac7d5ef0] | 484 | void Shm_Convert_packet( rtems_packet_prefix * ); |
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| 485 | |
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| 486 | /* CPU specific routines are inlined in shmcpu.h */ |
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| 487 | |
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| 488 | /* target specific routines */ |
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| 489 | void *Shm_Convert_address( void * ); |
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[509fec9c] | 490 | void Shm_Get_configuration( uint32_t, shm_config_table ** ); |
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[aec17f1] | 491 | void Shm_isr( void ); |
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[ac7d5ef0] | 492 | void Shm_setvec( void ); |
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| 493 | |
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| 494 | void Shm_Initialize_lock( Shm_Locked_queue_Control * ); |
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| 495 | void Shm_Lock( Shm_Locked_queue_Control * ); |
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| 496 | void Shm_Unlock( Shm_Locked_queue_Control * ); |
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| 497 | |
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| 498 | /* MPCI entry points */ |
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| 499 | rtems_mpci_entry Shm_Get_packet( |
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| 500 | rtems_packet_prefix ** |
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| 501 | ); |
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| 502 | |
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[3a4ae6c] | 503 | rtems_mpci_entry Shm_Initialization( void ); |
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[ac7d5ef0] | 504 | |
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| 505 | rtems_mpci_entry Shm_Receive_packet( |
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| 506 | rtems_packet_prefix ** |
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| 507 | ); |
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| 508 | |
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| 509 | rtems_mpci_entry Shm_Return_packet( |
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| 510 | rtems_packet_prefix * |
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| 511 | ); |
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| 512 | |
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| 513 | rtems_mpci_entry Shm_Send_packet( |
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[509fec9c] | 514 | uint32_t, |
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[ac7d5ef0] | 515 | rtems_packet_prefix * |
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| 516 | ); |
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| 517 | |
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[12f86efd] | 518 | extern rtems_mpci_table MPCI_table; |
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| 519 | |
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[ac7d5ef0] | 520 | #ifdef _SHM_INIT |
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| 521 | |
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| 522 | /* multiprocessor communications interface (MPCI) table */ |
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| 523 | |
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| 524 | rtems_mpci_table MPCI_table = { |
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| 525 | 100000, /* default timeout value in ticks */ |
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[b06e68ef] | 526 | MAX_PACKET_SIZE, /* maximum packet size */ |
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[ac7d5ef0] | 527 | Shm_Initialization, /* initialization procedure */ |
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| 528 | Shm_Get_packet, /* get packet procedure */ |
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| 529 | Shm_Return_packet, /* return packet procedure */ |
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| 530 | Shm_Send_packet, /* packet send procedure */ |
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| 531 | Shm_Receive_packet /* packet receive procedure */ |
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| 532 | }; |
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| 533 | |
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| 534 | #endif |
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| 535 | |
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| 536 | #ifdef __cplusplus |
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| 537 | } |
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| 538 | #endif |
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| 539 | |
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| 540 | #endif |
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| 541 | /* end of include file */ |
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