source: rtems/c/src/libchip/serial/z85c30_p.h @ 9eef52b

4.104.114.84.95
Last change on this file since 9eef52b was e4acf68, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 22, 1998 at 9:59:22 AM

Added comments and corrected spacing.

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File size: 9.4 KB
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1/*
2 *  This include file contains all private driver definitions for the
3 *  Zilog z85c30.
4 *
5 *  COPYRIGHT (c) 1998 by Radstone Technology
6 *
7 *
8 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
9 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
10 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
11 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
12 *
13 * You are hereby granted permission to use, copy, modify, and distribute
14 * this file, provided that this notice, plus the above copyright notice
15 * and disclaimer, appears in all copies. Radstone Technology will provide
16 * no support for this code.
17 *
18 *  COPYRIGHT (c) 1989-1997.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may in
23 *  the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 */
28
29#ifndef __Z85C30_P_H
30#define __Z85C30_P_H
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36/* bit values for write register 0 */
37/* command register */
38
39#define SCC_WR0_SEL_WR0   0x00
40#define SCC_WR0_SEL_WR1   0x01
41#define SCC_WR0_SEL_WR2   0x02
42#define SCC_WR0_SEL_WR3   0x03
43#define SCC_WR0_SEL_WR4   0x04
44#define SCC_WR0_SEL_WR5   0x05
45#define SCC_WR0_SEL_WR6   0x06
46#define SCC_WR0_SEL_WR7   0x07
47#define SCC_WR0_SEL_WR8   0x08
48#define SCC_WR0_SEL_WR9   0x09
49#define SCC_WR0_SEL_WR10  0x0a
50#define SCC_WR0_SEL_WR11  0x0b
51#define SCC_WR0_SEL_WR12  0x0c
52#define SCC_WR0_SEL_WR13  0x0d
53#define SCC_WR0_SEL_WR14  0x0e
54#define SCC_WR0_SEL_WR15  0x0f
55#define SCC_WR0_SEL_RD0   0x00
56#define SCC_WR0_SEL_RD1   0x01
57#define SCC_WR0_SEL_RD2   0x02
58#define SCC_WR0_SEL_RD3   0x03
59#define SCC_WR0_SEL_RD4   0x04
60#define SCC_WR0_SEL_RD5   0x05
61#define SCC_WR0_SEL_RD6   0x06
62#define SCC_WR0_SEL_RD7   0x07
63#define SCC_WR0_SEL_RD8   0x08
64#define SCC_WR0_SEL_RD9   0x09
65#define SCC_WR0_SEL_RD10  0x0a
66#define SCC_WR0_SEL_RD11  0x0b
67#define SCC_WR0_SEL_RD12  0x0c
68#define SCC_WR0_SEL_RD13  0x0d
69#define SCC_WR0_SEL_RD14  0x0e
70#define SCC_WR0_SEL_RD15  0x0f
71#define SCC_WR0_NULL_CODE 0x00
72#define SCC_WR0_RST_INT   0x10
73#define SCC_WR0_SEND_ABORT  0x18
74#define SCC_WR0_EN_INT_RX 0x20
75#define SCC_WR0_RST_TX_INT  0x28
76#define SCC_WR0_ERR_RST   0x30
77#define SCC_WR0_RST_HI_IUS  0x38
78#define SCC_WR0_RST_RX_CRC  0x40
79#define SCC_WR0_RST_TX_CRC  0x80
80#define SCC_WR0_RST_TX_UND  0xc0
81
82/* write register 2 */
83/* interrupt vector */
84
85/* bit values for write register 1 */
86/* tx/rx interrupt and data transfer mode definition */
87
88#define SCC_WR1_EXT_INT_EN  0x01
89#define SCC_WR1_TX_INT_EN 0x02
90#define SCC_WR1_PARITY    0x04
91#define SCC_WR1_RX_INT_DIS  0x00
92#define SCC_WR1_RX_INT_FIR  0x08
93#define SCC_WR1_INT_ALL_RX  0x10
94#define SCC_WR1_RX_INT_SPE  0x18
95#define SCC_WR1_RDMA_RECTR  0x20
96#define SCC_WR1_RDMA_FUNC 0x40
97#define SCC_WR1_RDMA_EN   0x80
98
99/* bit values for write register 3 */
100/* receive parameters and control */
101
102#define SCC_WR3_RX_EN   0x01
103#define SCC_WR3_SYNC_CHAR 0x02
104#define SCC_WR3_ADR_SEARCH  0x04
105#define SCC_WR3_RX_CRC_EN 0x08
106#define SCC_WR3_ENTER_HUNT  0x10
107#define SCC_WR3_AUTO_EN   0x20
108#define SCC_WR3_RX_5_BITS 0x00
109#define SCC_WR3_RX_7_BITS 0x40
110#define SCC_WR3_RX_6_BITS 0x80
111#define SCC_WR3_RX_8_BITS 0xc0
112
113/* bit values for write register 4 */
114/* tx/rx misc parameters and modes */
115
116#define SCC_WR4_PAR_EN    0x01
117#define SCC_WR4_PAR_EVEN  0x02
118#define SCC_WR4_SYNC_EN   0x00
119#define SCC_WR4_1_STOP    0x04
120#define SCC_WR4_2_STOP    0x0c
121#define SCC_WR4_8_SYNC    0x00
122#define SCC_WR4_16_SYNC   0x10
123#define SCC_WR4_SDLC    0x20
124#define SCC_WR4_EXT_SYNC  0x30
125#define SCC_WR4_1_CLOCK   0x00
126#define SCC_WR4_16_CLOCK  0x40
127#define SCC_WR4_32_CLOCK  0x80
128#define SCC_WR4_64_CLOCK  0xc0
129
130/* bit values for write register 5 */
131/* transmit parameter and controls */
132
133#define SCC_WR5_TX_CRC_EN 0x01
134#define SCC_WR5_RTS   0x02
135#define SCC_WR5_SDLC    0x04
136#define SCC_WR5_TX_EN   0x08
137#define SCC_WR5_SEND_BRK  0x10
138
139#define SCC_WR5_TX_5_BITS 0x00
140#define SCC_WR5_TX_7_BITS 0x20
141#define SCC_WR5_TX_6_BITS 0x40
142#define SCC_WR5_TX_8_BITS 0x60
143#define SCC_WR5_DTR   0x80
144
145/* write register 6 */
146/* sync chars or sdlc address field */
147
148/* write register 7 */
149/* sync char or sdlc flag */
150
151/* write register 8 */
152/* transmit buffer */
153
154/* bit values for write register 9 */
155/* master interrupt control */
156
157#define SCC_WR9_VIS   0x01
158#define SCC_WR9_NV    0x02
159#define SCC_WR9_DLC   0x04
160#define SCC_WR9_MIE   0x08
161#define SCC_WR9_STATUS_HI 0x10
162#define SCC_WR9_NO_RST    0x00
163#define SCC_WR9_CH_B_RST  0x40
164#define SCC_WR9_CH_A_RST  0x80
165#define SCC_WR9_HDWR_RST  0xc0
166
167/* bit values for write register 10 */
168/* misc tx/rx control bits */
169
170#define SCC_WR10_6_BIT_SYNC 0x01
171#define SCC_WR10_LOOP_MODE  0x02
172#define SCC_WR10_ABORT_UND  0x04
173#define SCC_WR10_MARK_IDLE  0x08
174#define SCC_WR10_ACT_POLL 0x10
175#define SCC_WR10_NRZ    0x00
176#define SCC_WR10_NRZI   0x20
177#define SCC_WR10_FM1    0x40
178#define SCC_WR10_FM0    0x60
179#define SCC_WR10_CRC_PRESET 0x80
180
181/* bit values for write register 11 */
182/* clock mode control */
183
184#define SCC_WR11_OUT_XTAL 0x00
185#define SCC_WR11_OUT_TX_CLK 0x01
186#define SCC_WR11_OUT_BR_GEN 0x02
187#define SCC_WR11_OUT_DPLL 0x03
188#define SCC_WR11_TRXC_OI  0x04
189#define SCC_WR11_TX_RTXC  0x00
190#define SCC_WR11_TX_TRXC  0x08
191#define SCC_WR11_TX_BR_GEN  0x10
192#define SCC_WR11_TX_DPLL  0x18
193#define SCC_WR11_RX_RTXC  0x00
194#define SCC_WR11_RX_TRXC  0x20
195#define SCC_WR11_RX_BR_GEN  0x40
196#define SCC_WR11_RX_DPLL  0x60
197#define SCC_WR11_RTXC_XTAL  0x80
198
199/* write register 12 */
200/* lower byte of baud rate generator time constant */
201
202/* write register 13 */
203/* upper byte of baud rate generator time constant */
204
205/* bit values for write register 14 */
206/* misc control bits */
207
208#define SCC_WR14_BR_EN    0x01
209#define SCC_WR14_BR_SRC   0x02
210#define SCC_WR14_DTR_FUNC 0x04
211#define SCC_WR14_AUTO_ECHO  0x08
212#define SCC_WR14_LCL_LOOP 0x10
213#define SCC_WR14_NULL   0x00
214#define SCC_WR14_SEARCH   0x20
215#define SCC_WR14_RST_CLK  0x40
216#define SCC_WR14_DIS_DPLL 0x60
217#define SCC_WR14_SRC_BR   0x80
218#define SCC_WR14_SRC_RTXC 0xa0
219#define SCC_WR14_FM_MODE  0xc0
220#define SCC_WR14_NRZI   0xe0
221
222/* bit values for write register 15 */
223/* external/status interrupt control */
224
225#define SCC_WR15_ZERO_CNT 0x02
226#define SCC_WR15_CD_IE    0x08
227#define SCC_WR15_SYNC_IE  0x10
228#define SCC_WR15_CTS_IE   0x20
229#define SCC_WR15_TX_UND_IE  0x40
230#define SCC_WR15_BREAK_IE 0x80
231
232/* bit values for read register 0 */
233/* tx/rx buffer status and external status  */
234
235#define SCC_RR0_RX_AVAIL  0x01
236#define SCC_RR0_ZERO_CNT  0x02
237#define SCC_RR0_TX_EMPTY  0x04
238#define SCC_RR0_CD    0x08
239#define SCC_RR0_SYNC    0x10
240#define SCC_RR0_CTS   0x20
241#define SCC_RR0_TX_UND    0x40
242#define SCC_RR0_BREAK   0x80
243
244/* bit values for read register 1 */
245
246#define SCC_RR1_ALL_SENT  0x01
247#define SCC_RR1_RES_CD_2  0x02
248#define SCC_RR1_RES_CD_1  0x01
249#define SCC_RR1_RES_CD_0  0x08
250#define SCC_RR1_PAR_ERR   0x10
251#define SCC_RR1_RX_OV_ERR 0x20
252#define SCC_RR1_CRC_ERR   0x40
253#define SCC_RR1_END_FRAME 0x80
254
255/* read register 2 */
256/* interrupt vector */
257
258/* bit values for read register 3 */
259/* interrupt pending register */
260
261#define SCC_RR3_B_EXT_IP  0x01
262#define SCC_RR3_B_TX_IP   0x02
263#define SCC_RR3_B_RX_IP   0x04
264#define SCC_RR3_A_EXT_IP  0x08
265#define SCC_RR3_A_TX_IP   0x10
266#define SCC_RR3_A_RX_IP   0x20
267
268/* read register 8 */
269/* receive data register */
270
271/* bit values for read register 10 */
272/* misc status bits */
273
274#define SCC_RR10_ON_LOOP  0x02
275#define SCC_RR10_LOOP_SEND  0x10
276#define SCC_RR10_2_CLK_MIS  0x40
277#define SCC_RR10_1_CLK_MIS  0x80
278
279/* read register 12 */
280/* lower byte of time constant */
281
282/* read register 13 */
283/* upper byte of time constant */
284
285/* bit values for read register 15 */
286/* external/status ie bits */
287
288#define SCC_RR15_ZERO_CNT 0x02
289#define SCC_RR15_CD_IE    0x08
290#define SCC_RR15_SYNC_IE  0x10
291#define SCC_RR15_CTS_IE   0x20
292#define SCC_RR15_TX_UND_IE  0x40
293#define SCC_RR15_BREAK_IE 0x80
294
295typedef struct _z85c30_context
296{
297  unsigned8 ucModemCtrl;
298} z85c30_context;
299
300/*
301 * The following macro calculates the Baud constant. For the Z85C30 chip.
302 *
303 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
304 *       eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
305 */
306
307#define Z85C30_Baud( _clock, _baud_rate  )   \
308  ( ((_clock) /(  16 * 2 * _baud_rate))  - 2)
309
310#define Z85C30_Status_Is_RX_character_available(_status) \
311  ((_status) & SCC_RR0_RX_AVAIL)
312
313#define Z85C30_Status_Is_TX_buffer_empty(_status) \
314  ((_status) & SCC_RR0_TX_EMPTY)
315
316#define Z85C30_Status_Is_CTS_asserted(_status) \
317  ((_status) & SCC_RR0_CTS)
318
319#define Z85C30_Status_Is_break_abort(_status) \
320  ((_status) & SCC_RR0_BREAK)
321
322/*
323 * Private routines
324 */
325static boolean z85c30_probe(int minor);
326
327static void z85c30_init(int minor);
328
329static int z85c30_open(
330  int major,
331  int minor,
332  void  * arg
333);
334
335static int z85c30_close(
336  int major,
337  int minor,
338  void  * arg
339);
340
341static void z85c30_write_polled(
342  int   minor, 
343  char  cChar
344);
345
346static int z85c30_assert_RTS(
347  int minor
348);
349
350static int z85c30_negate_RTS(
351  int minor
352);
353
354static int z85c30_assert_DTR(
355  int minor
356);
357
358static int z85c30_negate_DTR(
359  int minor
360);
361
362static void z85c30_initialize_interrupts(int minor);
363
364static int z85c30_flush(int major, int minor, void *arg);
365
366static int z85c30_write_support_int(
367  int   minor,
368  const char *buf,
369  int   len
370);
371
372static int z85c30_write_support_polled(
373  int   minor,
374  const char *buf,
375  int   len
376);
377
378static int z85c30_inbyte_nonblocking_polled(
379  int minor
380);
381
382#ifdef __cplusplus
383}
384#endif
385
386#endif
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