1 | /* |
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2 | * This include file contains all private driver definitions for the |
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3 | * Zilog z85c30. |
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4 | * |
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5 | * COPYRIGHT (c) 1998 by Radstone Technology |
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6 | * |
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7 | * |
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8 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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9 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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10 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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11 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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12 | * |
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13 | * You are hereby granted permission to use, copy, modify, and distribute |
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14 | * this file, provided that this notice, plus the above copyright notice |
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15 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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16 | * no support for this code. |
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17 | * |
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18 | * COPYRIGHT (c) 1989-1997. |
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19 | * On-Line Applications Research Corporation (OAR). |
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20 | * Copyright assigned to U.S. Government, 1994. |
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21 | * |
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22 | * The license and distribution terms for this file may in |
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23 | * the file LICENSE in this distribution or at |
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24 | * http://www.OARcorp.com/rtems/license.html. |
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25 | * |
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26 | * $Id$ |
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27 | */ |
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28 | |
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29 | #ifndef __Z85C30_P_H |
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30 | #define __Z85C30_P_H |
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31 | |
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32 | #ifdef __cplusplus |
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33 | extern "C" { |
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34 | #endif |
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35 | |
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36 | /* |
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37 | * Define Z85C30_STATIC to nothing while debugging so the entry points |
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38 | * will show up in the symbol table. |
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39 | */ |
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40 | |
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41 | #define Z85C30_STATIC |
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42 | |
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43 | /* #define Z85C30_STATIC static */ |
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44 | |
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45 | /* bit values for write register 0 */ |
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46 | /* command register */ |
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47 | |
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48 | #define SCC_WR0_SEL_WR0 0x00 |
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49 | #define SCC_WR0_SEL_WR1 0x01 |
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50 | #define SCC_WR0_SEL_WR2 0x02 |
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51 | #define SCC_WR0_SEL_WR3 0x03 |
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52 | #define SCC_WR0_SEL_WR4 0x04 |
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53 | #define SCC_WR0_SEL_WR5 0x05 |
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54 | #define SCC_WR0_SEL_WR6 0x06 |
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55 | #define SCC_WR0_SEL_WR7 0x07 |
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56 | #define SCC_WR0_SEL_WR8 0x08 |
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57 | #define SCC_WR0_SEL_WR9 0x09 |
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58 | #define SCC_WR0_SEL_WR10 0x0a |
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59 | #define SCC_WR0_SEL_WR11 0x0b |
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60 | #define SCC_WR0_SEL_WR12 0x0c |
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61 | #define SCC_WR0_SEL_WR13 0x0d |
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62 | #define SCC_WR0_SEL_WR14 0x0e |
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63 | #define SCC_WR0_SEL_WR15 0x0f |
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64 | #define SCC_WR0_SEL_RD0 0x00 |
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65 | #define SCC_WR0_SEL_RD1 0x01 |
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66 | #define SCC_WR0_SEL_RD2 0x02 |
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67 | #define SCC_WR0_SEL_RD3 0x03 |
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68 | #define SCC_WR0_SEL_RD4 0x04 |
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69 | #define SCC_WR0_SEL_RD5 0x05 |
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70 | #define SCC_WR0_SEL_RD6 0x06 |
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71 | #define SCC_WR0_SEL_RD7 0x07 |
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72 | #define SCC_WR0_SEL_RD8 0x08 |
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73 | #define SCC_WR0_SEL_RD9 0x09 |
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74 | #define SCC_WR0_SEL_RD10 0x0a |
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75 | #define SCC_WR0_SEL_RD11 0x0b |
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76 | #define SCC_WR0_SEL_RD12 0x0c |
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77 | #define SCC_WR0_SEL_RD13 0x0d |
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78 | #define SCC_WR0_SEL_RD14 0x0e |
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79 | #define SCC_WR0_SEL_RD15 0x0f |
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80 | #define SCC_WR0_NULL_CODE 0x00 |
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81 | #define SCC_WR0_RST_INT 0x10 |
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82 | #define SCC_WR0_SEND_ABORT 0x18 |
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83 | #define SCC_WR0_EN_INT_RX 0x20 |
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84 | #define SCC_WR0_RST_TX_INT 0x28 |
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85 | #define SCC_WR0_ERR_RST 0x30 |
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86 | #define SCC_WR0_RST_HI_IUS 0x38 |
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87 | #define SCC_WR0_RST_RX_CRC 0x40 |
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88 | #define SCC_WR0_RST_TX_CRC 0x80 |
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89 | #define SCC_WR0_RST_TX_UND 0xc0 |
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90 | |
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91 | /* write register 2 */ |
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92 | /* interrupt vector */ |
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93 | |
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94 | /* bit values for write register 1 */ |
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95 | /* tx/rx interrupt and data transfer mode definition */ |
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96 | |
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97 | #define SCC_WR1_EXT_INT_EN 0x01 |
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98 | #define SCC_WR1_TX_INT_EN 0x02 |
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99 | #define SCC_WR1_PARITY 0x04 |
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100 | #define SCC_WR1_RX_INT_DIS 0x00 |
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101 | #define SCC_WR1_RX_INT_FIR 0x08 |
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102 | #define SCC_WR1_INT_ALL_RX 0x10 |
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103 | #define SCC_WR1_RX_INT_SPE 0x18 |
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104 | #define SCC_WR1_RDMA_RECTR 0x20 |
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105 | #define SCC_WR1_RDMA_FUNC 0x40 |
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106 | #define SCC_WR1_RDMA_EN 0x80 |
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107 | |
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108 | /* bit values for write register 3 */ |
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109 | /* receive parameters and control */ |
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110 | |
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111 | #define SCC_WR3_RX_EN 0x01 |
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112 | #define SCC_WR3_SYNC_CHAR 0x02 |
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113 | #define SCC_WR3_ADR_SEARCH 0x04 |
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114 | #define SCC_WR3_RX_CRC_EN 0x08 |
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115 | #define SCC_WR3_ENTER_HUNT 0x10 |
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116 | #define SCC_WR3_AUTO_EN 0x20 |
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117 | #define SCC_WR3_RX_5_BITS 0x00 |
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118 | #define SCC_WR3_RX_7_BITS 0x40 |
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119 | #define SCC_WR3_RX_6_BITS 0x80 |
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120 | #define SCC_WR3_RX_8_BITS 0xc0 |
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121 | |
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122 | /* bit values for write register 4 */ |
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123 | /* tx/rx misc parameters and modes */ |
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124 | |
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125 | #define SCC_WR4_PAR_EN 0x01 |
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126 | #define SCC_WR4_PAR_EVEN 0x02 |
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127 | #define SCC_WR4_SYNC_EN 0x00 |
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128 | #define SCC_WR4_1_STOP 0x04 |
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129 | #define SCC_WR4_2_STOP 0x0c |
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130 | #define SCC_WR4_8_SYNC 0x00 |
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131 | #define SCC_WR4_16_SYNC 0x10 |
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132 | #define SCC_WR4_SDLC 0x20 |
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133 | #define SCC_WR4_EXT_SYNC 0x30 |
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134 | #define SCC_WR4_1_CLOCK 0x00 |
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135 | #define SCC_WR4_16_CLOCK 0x40 |
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136 | #define SCC_WR4_32_CLOCK 0x80 |
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137 | #define SCC_WR4_64_CLOCK 0xc0 |
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138 | |
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139 | /* bit values for write register 5 */ |
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140 | /* transmit parameter and controls */ |
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141 | |
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142 | #define SCC_WR5_TX_CRC_EN 0x01 |
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143 | #define SCC_WR5_RTS 0x02 |
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144 | #define SCC_WR5_SDLC 0x04 |
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145 | #define SCC_WR5_TX_EN 0x08 |
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146 | #define SCC_WR5_SEND_BRK 0x10 |
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147 | |
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148 | #define SCC_WR5_TX_5_BITS 0x00 |
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149 | #define SCC_WR5_TX_7_BITS 0x20 |
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150 | #define SCC_WR5_TX_6_BITS 0x40 |
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151 | #define SCC_WR5_TX_8_BITS 0x60 |
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152 | #define SCC_WR5_DTR 0x80 |
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153 | |
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154 | /* write register 6 */ |
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155 | /* sync chars or sdlc address field */ |
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156 | |
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157 | /* write register 7 */ |
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158 | /* sync char or sdlc flag */ |
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159 | |
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160 | /* write register 8 */ |
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161 | /* transmit buffer */ |
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162 | |
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163 | /* bit values for write register 9 */ |
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164 | /* master interrupt control */ |
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165 | |
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166 | #define SCC_WR9_VIS 0x01 |
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167 | #define SCC_WR9_NV 0x02 |
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168 | #define SCC_WR9_DLC 0x04 |
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169 | #define SCC_WR9_MIE 0x08 |
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170 | #define SCC_WR9_STATUS_HI 0x10 |
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171 | #define SCC_WR9_NO_RST 0x00 |
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172 | #define SCC_WR9_CH_B_RST 0x40 |
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173 | #define SCC_WR9_CH_A_RST 0x80 |
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174 | #define SCC_WR9_HDWR_RST 0xc0 |
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175 | |
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176 | /* bit values for write register 10 */ |
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177 | /* misc tx/rx control bits */ |
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178 | |
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179 | #define SCC_WR10_6_BIT_SYNC 0x01 |
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180 | #define SCC_WR10_LOOP_MODE 0x02 |
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181 | #define SCC_WR10_ABORT_UND 0x04 |
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182 | #define SCC_WR10_MARK_IDLE 0x08 |
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183 | #define SCC_WR10_ACT_POLL 0x10 |
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184 | #define SCC_WR10_NRZ 0x00 |
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185 | #define SCC_WR10_NRZI 0x20 |
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186 | #define SCC_WR10_FM1 0x40 |
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187 | #define SCC_WR10_FM0 0x60 |
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188 | #define SCC_WR10_CRC_PRESET 0x80 |
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189 | |
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190 | /* bit values for write register 11 */ |
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191 | /* clock mode control */ |
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192 | |
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193 | #define SCC_WR11_OUT_XTAL 0x00 |
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194 | #define SCC_WR11_OUT_TX_CLK 0x01 |
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195 | #define SCC_WR11_OUT_BR_GEN 0x02 |
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196 | #define SCC_WR11_OUT_DPLL 0x03 |
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197 | #define SCC_WR11_TRXC_OI 0x04 |
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198 | #define SCC_WR11_TX_RTXC 0x00 |
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199 | #define SCC_WR11_TX_TRXC 0x08 |
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200 | #define SCC_WR11_TX_BR_GEN 0x10 |
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201 | #define SCC_WR11_TX_DPLL 0x18 |
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202 | #define SCC_WR11_RX_RTXC 0x00 |
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203 | #define SCC_WR11_RX_TRXC 0x20 |
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204 | #define SCC_WR11_RX_BR_GEN 0x40 |
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205 | #define SCC_WR11_RX_DPLL 0x60 |
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206 | #define SCC_WR11_RTXC_XTAL 0x80 |
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207 | |
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208 | /* write register 12 */ |
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209 | /* lower byte of baud rate generator time constant */ |
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210 | |
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211 | /* write register 13 */ |
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212 | /* upper byte of baud rate generator time constant */ |
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213 | |
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214 | /* bit values for write register 14 */ |
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215 | /* misc control bits */ |
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216 | |
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217 | #define SCC_WR14_BR_EN 0x01 |
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218 | #define SCC_WR14_BR_SRC 0x02 |
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219 | #define SCC_WR14_DTR_FUNC 0x04 |
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220 | #define SCC_WR14_AUTO_ECHO 0x08 |
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221 | #define SCC_WR14_LCL_LOOP 0x10 |
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222 | #define SCC_WR14_NULL 0x00 |
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223 | #define SCC_WR14_SEARCH 0x20 |
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224 | #define SCC_WR14_RST_CLK 0x40 |
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225 | #define SCC_WR14_DIS_DPLL 0x60 |
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226 | #define SCC_WR14_SRC_BR 0x80 |
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227 | #define SCC_WR14_SRC_RTXC 0xa0 |
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228 | #define SCC_WR14_FM_MODE 0xc0 |
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229 | #define SCC_WR14_NRZI 0xe0 |
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230 | |
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231 | /* bit values for write register 15 */ |
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232 | /* external/status interrupt control */ |
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233 | |
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234 | #define SCC_WR15_ZERO_CNT 0x02 |
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235 | #define SCC_WR15_CD_IE 0x08 |
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236 | #define SCC_WR15_SYNC_IE 0x10 |
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237 | #define SCC_WR15_CTS_IE 0x20 |
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238 | #define SCC_WR15_TX_UND_IE 0x40 |
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239 | #define SCC_WR15_BREAK_IE 0x80 |
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240 | |
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241 | /* bit values for read register 0 */ |
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242 | /* tx/rx buffer status and external status */ |
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243 | |
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244 | #define SCC_RR0_RX_AVAIL 0x01 |
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245 | #define SCC_RR0_ZERO_CNT 0x02 |
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246 | #define SCC_RR0_TX_EMPTY 0x04 |
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247 | #define SCC_RR0_CD 0x08 |
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248 | #define SCC_RR0_SYNC 0x10 |
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249 | #define SCC_RR0_CTS 0x20 |
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250 | #define SCC_RR0_TX_UND 0x40 |
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251 | #define SCC_RR0_BREAK 0x80 |
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252 | |
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253 | /* bit values for read register 1 */ |
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254 | |
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255 | #define SCC_RR1_ALL_SENT 0x01 |
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256 | #define SCC_RR1_RES_CD_2 0x02 |
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257 | #define SCC_RR1_RES_CD_1 0x01 |
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258 | #define SCC_RR1_RES_CD_0 0x08 |
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259 | #define SCC_RR1_PAR_ERR 0x10 |
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260 | #define SCC_RR1_RX_OV_ERR 0x20 |
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261 | #define SCC_RR1_CRC_ERR 0x40 |
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262 | #define SCC_RR1_END_FRAME 0x80 |
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263 | |
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264 | /* read register 2 */ |
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265 | /* interrupt vector */ |
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266 | |
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267 | /* bit values for read register 3 */ |
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268 | /* interrupt pending register */ |
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269 | |
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270 | #define SCC_RR3_B_EXT_IP 0x01 |
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271 | #define SCC_RR3_B_TX_IP 0x02 |
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272 | #define SCC_RR3_B_RX_IP 0x04 |
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273 | #define SCC_RR3_A_EXT_IP 0x08 |
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274 | #define SCC_RR3_A_TX_IP 0x10 |
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275 | #define SCC_RR3_A_RX_IP 0x20 |
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276 | |
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277 | /* read register 8 */ |
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278 | /* receive data register */ |
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279 | |
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280 | /* bit values for read register 10 */ |
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281 | /* misc status bits */ |
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282 | |
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283 | #define SCC_RR10_ON_LOOP 0x02 |
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284 | #define SCC_RR10_LOOP_SEND 0x10 |
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285 | #define SCC_RR10_2_CLK_MIS 0x40 |
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286 | #define SCC_RR10_1_CLK_MIS 0x80 |
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287 | |
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288 | /* read register 12 */ |
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289 | /* lower byte of time constant */ |
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290 | |
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291 | /* read register 13 */ |
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292 | /* upper byte of time constant */ |
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293 | |
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294 | /* bit values for read register 15 */ |
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295 | /* external/status ie bits */ |
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296 | |
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297 | #define SCC_RR15_ZERO_CNT 0x02 |
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298 | #define SCC_RR15_CD_IE 0x08 |
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299 | #define SCC_RR15_SYNC_IE 0x10 |
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300 | #define SCC_RR15_CTS_IE 0x20 |
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301 | #define SCC_RR15_TX_UND_IE 0x40 |
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302 | #define SCC_RR15_BREAK_IE 0x80 |
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303 | |
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304 | typedef struct _z85c30_context |
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305 | { |
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306 | unsigned8 ucModemCtrl; |
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307 | } z85c30_context; |
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308 | |
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309 | /* |
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310 | * The following macro calculates the Baud constant. For the Z85C30 chip. |
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311 | * |
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312 | * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 |
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313 | * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2 |
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314 | */ |
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315 | |
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316 | #define Z85C30_Baud( _clock, _baud_rate ) \ |
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317 | ( ((_clock) /( 16 * 2 * _baud_rate)) - 2) |
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318 | |
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319 | #define Z85C30_Status_Is_RX_character_available(_status) \ |
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320 | ((_status) & SCC_RR0_RX_AVAIL) |
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321 | |
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322 | #define Z85C30_Status_Is_TX_buffer_empty(_status) \ |
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323 | ((_status) & SCC_RR0_TX_EMPTY) |
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324 | |
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325 | #define Z85C30_Status_Is_CTS_asserted(_status) \ |
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326 | ((_status) & SCC_RR0_CTS) |
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327 | |
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328 | #define Z85C30_Status_Is_break_abort(_status) \ |
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329 | ((_status) & SCC_RR0_BREAK) |
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330 | |
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331 | /* |
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332 | * Private routines |
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333 | */ |
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334 | |
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335 | Z85C30_STATIC void z85c30_init(int minor); |
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336 | |
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337 | Z85C30_STATIC int z85c30_set_attributes( |
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338 | int minor, |
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339 | const struct termios *t |
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340 | ); |
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341 | |
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342 | Z85C30_STATIC int z85c30_open( |
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343 | int major, |
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344 | int minor, |
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345 | void * arg |
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346 | ); |
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347 | |
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348 | Z85C30_STATIC int z85c30_close( |
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349 | int major, |
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350 | int minor, |
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351 | void * arg |
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352 | ); |
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353 | |
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354 | Z85C30_STATIC void z85c30_write_polled( |
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355 | int minor, |
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356 | char cChar |
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357 | ); |
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358 | |
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359 | Z85C30_STATIC int z85c30_assert_RTS( |
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360 | int minor |
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361 | ); |
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362 | |
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363 | Z85C30_STATIC int z85c30_negate_RTS( |
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364 | int minor |
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365 | ); |
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366 | |
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367 | Z85C30_STATIC int z85c30_assert_DTR( |
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368 | int minor |
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369 | ); |
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370 | |
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371 | Z85C30_STATIC int z85c30_negate_DTR( |
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372 | int minor |
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373 | ); |
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374 | |
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375 | Z85C30_STATIC void z85c30_initialize_interrupts(int minor); |
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376 | |
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377 | Z85C30_STATIC int z85c30_flush(int major, int minor, void *arg); |
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378 | |
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379 | Z85C30_STATIC int z85c30_write_support_int( |
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380 | int minor, |
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381 | const char *buf, |
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382 | int len |
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383 | ); |
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384 | |
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385 | Z85C30_STATIC int z85c30_write_support_polled( |
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386 | int minor, |
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387 | const char *buf, |
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388 | int len |
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389 | ); |
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390 | |
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391 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
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392 | int minor |
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393 | ); |
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394 | |
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395 | #ifdef __cplusplus |
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396 | } |
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397 | #endif |
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398 | |
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399 | #endif |
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