source: rtems/c/src/libchip/serial/z85c30_p.h @ 849dc107

4.104.114.84.9
Last change on this file since 849dc107 was fb32356b, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 9, 1998 at 11:32:07 PM

Added set attributes routine but did not hook it in to the table.

Switched to shared default probe.

  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 *  This include file contains all private driver definitions for the
3 *  Zilog z85c30.
4 *
5 *  COPYRIGHT (c) 1998 by Radstone Technology
6 *
7 *
8 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
9 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
10 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
11 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
12 *
13 * You are hereby granted permission to use, copy, modify, and distribute
14 * this file, provided that this notice, plus the above copyright notice
15 * and disclaimer, appears in all copies. Radstone Technology will provide
16 * no support for this code.
17 *
18 *  COPYRIGHT (c) 1989-1997.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may in
23 *  the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 */
28
29#ifndef __Z85C30_P_H
30#define __Z85C30_P_H
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36/*
37 *  Define Z85C30_STATIC to nothing while debugging so the entry points
38 *  will show up in the symbol table.
39 */
40
41#define Z85C30_STATIC
42
43/* #define Z85C30_STATIC static */
44
45/* bit values for write register 0 */
46/* command register */
47
48#define SCC_WR0_SEL_WR0   0x00
49#define SCC_WR0_SEL_WR1   0x01
50#define SCC_WR0_SEL_WR2   0x02
51#define SCC_WR0_SEL_WR3   0x03
52#define SCC_WR0_SEL_WR4   0x04
53#define SCC_WR0_SEL_WR5   0x05
54#define SCC_WR0_SEL_WR6   0x06
55#define SCC_WR0_SEL_WR7   0x07
56#define SCC_WR0_SEL_WR8   0x08
57#define SCC_WR0_SEL_WR9   0x09
58#define SCC_WR0_SEL_WR10  0x0a
59#define SCC_WR0_SEL_WR11  0x0b
60#define SCC_WR0_SEL_WR12  0x0c
61#define SCC_WR0_SEL_WR13  0x0d
62#define SCC_WR0_SEL_WR14  0x0e
63#define SCC_WR0_SEL_WR15  0x0f
64#define SCC_WR0_SEL_RD0   0x00
65#define SCC_WR0_SEL_RD1   0x01
66#define SCC_WR0_SEL_RD2   0x02
67#define SCC_WR0_SEL_RD3   0x03
68#define SCC_WR0_SEL_RD4   0x04
69#define SCC_WR0_SEL_RD5   0x05
70#define SCC_WR0_SEL_RD6   0x06
71#define SCC_WR0_SEL_RD7   0x07
72#define SCC_WR0_SEL_RD8   0x08
73#define SCC_WR0_SEL_RD9   0x09
74#define SCC_WR0_SEL_RD10  0x0a
75#define SCC_WR0_SEL_RD11  0x0b
76#define SCC_WR0_SEL_RD12  0x0c
77#define SCC_WR0_SEL_RD13  0x0d
78#define SCC_WR0_SEL_RD14  0x0e
79#define SCC_WR0_SEL_RD15  0x0f
80#define SCC_WR0_NULL_CODE 0x00
81#define SCC_WR0_RST_INT   0x10
82#define SCC_WR0_SEND_ABORT  0x18
83#define SCC_WR0_EN_INT_RX 0x20
84#define SCC_WR0_RST_TX_INT  0x28
85#define SCC_WR0_ERR_RST   0x30
86#define SCC_WR0_RST_HI_IUS  0x38
87#define SCC_WR0_RST_RX_CRC  0x40
88#define SCC_WR0_RST_TX_CRC  0x80
89#define SCC_WR0_RST_TX_UND  0xc0
90
91/* write register 2 */
92/* interrupt vector */
93
94/* bit values for write register 1 */
95/* tx/rx interrupt and data transfer mode definition */
96
97#define SCC_WR1_EXT_INT_EN  0x01
98#define SCC_WR1_TX_INT_EN 0x02
99#define SCC_WR1_PARITY    0x04
100#define SCC_WR1_RX_INT_DIS  0x00
101#define SCC_WR1_RX_INT_FIR  0x08
102#define SCC_WR1_INT_ALL_RX  0x10
103#define SCC_WR1_RX_INT_SPE  0x18
104#define SCC_WR1_RDMA_RECTR  0x20
105#define SCC_WR1_RDMA_FUNC 0x40
106#define SCC_WR1_RDMA_EN   0x80
107
108/* bit values for write register 3 */
109/* receive parameters and control */
110
111#define SCC_WR3_RX_EN   0x01
112#define SCC_WR3_SYNC_CHAR 0x02
113#define SCC_WR3_ADR_SEARCH  0x04
114#define SCC_WR3_RX_CRC_EN 0x08
115#define SCC_WR3_ENTER_HUNT  0x10
116#define SCC_WR3_AUTO_EN   0x20
117#define SCC_WR3_RX_5_BITS 0x00
118#define SCC_WR3_RX_7_BITS 0x40
119#define SCC_WR3_RX_6_BITS 0x80
120#define SCC_WR3_RX_8_BITS 0xc0
121
122/* bit values for write register 4 */
123/* tx/rx misc parameters and modes */
124
125#define SCC_WR4_PAR_EN    0x01
126#define SCC_WR4_PAR_EVEN  0x02
127#define SCC_WR4_SYNC_EN   0x00
128#define SCC_WR4_1_STOP    0x04
129#define SCC_WR4_2_STOP    0x0c
130#define SCC_WR4_8_SYNC    0x00
131#define SCC_WR4_16_SYNC   0x10
132#define SCC_WR4_SDLC    0x20
133#define SCC_WR4_EXT_SYNC  0x30
134#define SCC_WR4_1_CLOCK   0x00
135#define SCC_WR4_16_CLOCK  0x40
136#define SCC_WR4_32_CLOCK  0x80
137#define SCC_WR4_64_CLOCK  0xc0
138
139/* bit values for write register 5 */
140/* transmit parameter and controls */
141
142#define SCC_WR5_TX_CRC_EN 0x01
143#define SCC_WR5_RTS   0x02
144#define SCC_WR5_SDLC    0x04
145#define SCC_WR5_TX_EN   0x08
146#define SCC_WR5_SEND_BRK  0x10
147
148#define SCC_WR5_TX_5_BITS 0x00
149#define SCC_WR5_TX_7_BITS 0x20
150#define SCC_WR5_TX_6_BITS 0x40
151#define SCC_WR5_TX_8_BITS 0x60
152#define SCC_WR5_DTR   0x80
153
154/* write register 6 */
155/* sync chars or sdlc address field */
156
157/* write register 7 */
158/* sync char or sdlc flag */
159
160/* write register 8 */
161/* transmit buffer */
162
163/* bit values for write register 9 */
164/* master interrupt control */
165
166#define SCC_WR9_VIS   0x01
167#define SCC_WR9_NV    0x02
168#define SCC_WR9_DLC   0x04
169#define SCC_WR9_MIE   0x08
170#define SCC_WR9_STATUS_HI 0x10
171#define SCC_WR9_NO_RST    0x00
172#define SCC_WR9_CH_B_RST  0x40
173#define SCC_WR9_CH_A_RST  0x80
174#define SCC_WR9_HDWR_RST  0xc0
175
176/* bit values for write register 10 */
177/* misc tx/rx control bits */
178
179#define SCC_WR10_6_BIT_SYNC 0x01
180#define SCC_WR10_LOOP_MODE  0x02
181#define SCC_WR10_ABORT_UND  0x04
182#define SCC_WR10_MARK_IDLE  0x08
183#define SCC_WR10_ACT_POLL 0x10
184#define SCC_WR10_NRZ    0x00
185#define SCC_WR10_NRZI   0x20
186#define SCC_WR10_FM1    0x40
187#define SCC_WR10_FM0    0x60
188#define SCC_WR10_CRC_PRESET 0x80
189
190/* bit values for write register 11 */
191/* clock mode control */
192
193#define SCC_WR11_OUT_XTAL 0x00
194#define SCC_WR11_OUT_TX_CLK 0x01
195#define SCC_WR11_OUT_BR_GEN 0x02
196#define SCC_WR11_OUT_DPLL 0x03
197#define SCC_WR11_TRXC_OI  0x04
198#define SCC_WR11_TX_RTXC  0x00
199#define SCC_WR11_TX_TRXC  0x08
200#define SCC_WR11_TX_BR_GEN  0x10
201#define SCC_WR11_TX_DPLL  0x18
202#define SCC_WR11_RX_RTXC  0x00
203#define SCC_WR11_RX_TRXC  0x20
204#define SCC_WR11_RX_BR_GEN  0x40
205#define SCC_WR11_RX_DPLL  0x60
206#define SCC_WR11_RTXC_XTAL  0x80
207
208/* write register 12 */
209/* lower byte of baud rate generator time constant */
210
211/* write register 13 */
212/* upper byte of baud rate generator time constant */
213
214/* bit values for write register 14 */
215/* misc control bits */
216
217#define SCC_WR14_BR_EN    0x01
218#define SCC_WR14_BR_SRC   0x02
219#define SCC_WR14_DTR_FUNC 0x04
220#define SCC_WR14_AUTO_ECHO  0x08
221#define SCC_WR14_LCL_LOOP 0x10
222#define SCC_WR14_NULL   0x00
223#define SCC_WR14_SEARCH   0x20
224#define SCC_WR14_RST_CLK  0x40
225#define SCC_WR14_DIS_DPLL 0x60
226#define SCC_WR14_SRC_BR   0x80
227#define SCC_WR14_SRC_RTXC 0xa0
228#define SCC_WR14_FM_MODE  0xc0
229#define SCC_WR14_NRZI   0xe0
230
231/* bit values for write register 15 */
232/* external/status interrupt control */
233
234#define SCC_WR15_ZERO_CNT 0x02
235#define SCC_WR15_CD_IE    0x08
236#define SCC_WR15_SYNC_IE  0x10
237#define SCC_WR15_CTS_IE   0x20
238#define SCC_WR15_TX_UND_IE  0x40
239#define SCC_WR15_BREAK_IE 0x80
240
241/* bit values for read register 0 */
242/* tx/rx buffer status and external status  */
243
244#define SCC_RR0_RX_AVAIL  0x01
245#define SCC_RR0_ZERO_CNT  0x02
246#define SCC_RR0_TX_EMPTY  0x04
247#define SCC_RR0_CD    0x08
248#define SCC_RR0_SYNC    0x10
249#define SCC_RR0_CTS   0x20
250#define SCC_RR0_TX_UND    0x40
251#define SCC_RR0_BREAK   0x80
252
253/* bit values for read register 1 */
254
255#define SCC_RR1_ALL_SENT  0x01
256#define SCC_RR1_RES_CD_2  0x02
257#define SCC_RR1_RES_CD_1  0x01
258#define SCC_RR1_RES_CD_0  0x08
259#define SCC_RR1_PAR_ERR   0x10
260#define SCC_RR1_RX_OV_ERR 0x20
261#define SCC_RR1_CRC_ERR   0x40
262#define SCC_RR1_END_FRAME 0x80
263
264/* read register 2 */
265/* interrupt vector */
266
267/* bit values for read register 3 */
268/* interrupt pending register */
269
270#define SCC_RR3_B_EXT_IP  0x01
271#define SCC_RR3_B_TX_IP   0x02
272#define SCC_RR3_B_RX_IP   0x04
273#define SCC_RR3_A_EXT_IP  0x08
274#define SCC_RR3_A_TX_IP   0x10
275#define SCC_RR3_A_RX_IP   0x20
276
277/* read register 8 */
278/* receive data register */
279
280/* bit values for read register 10 */
281/* misc status bits */
282
283#define SCC_RR10_ON_LOOP  0x02
284#define SCC_RR10_LOOP_SEND  0x10
285#define SCC_RR10_2_CLK_MIS  0x40
286#define SCC_RR10_1_CLK_MIS  0x80
287
288/* read register 12 */
289/* lower byte of time constant */
290
291/* read register 13 */
292/* upper byte of time constant */
293
294/* bit values for read register 15 */
295/* external/status ie bits */
296
297#define SCC_RR15_ZERO_CNT 0x02
298#define SCC_RR15_CD_IE    0x08
299#define SCC_RR15_SYNC_IE  0x10
300#define SCC_RR15_CTS_IE   0x20
301#define SCC_RR15_TX_UND_IE  0x40
302#define SCC_RR15_BREAK_IE 0x80
303
304typedef struct _z85c30_context
305{
306  unsigned8 ucModemCtrl;
307} z85c30_context;
308
309/*
310 * The following macro calculates the Baud constant. For the Z85C30 chip.
311 *
312 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
313 *       eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
314 */
315
316#define Z85C30_Baud( _clock, _baud_rate  )   \
317  ( ((_clock) /(  16 * 2 * _baud_rate))  - 2)
318
319#define Z85C30_Status_Is_RX_character_available(_status) \
320  ((_status) & SCC_RR0_RX_AVAIL)
321
322#define Z85C30_Status_Is_TX_buffer_empty(_status) \
323  ((_status) & SCC_RR0_TX_EMPTY)
324
325#define Z85C30_Status_Is_CTS_asserted(_status) \
326  ((_status) & SCC_RR0_CTS)
327
328#define Z85C30_Status_Is_break_abort(_status) \
329  ((_status) & SCC_RR0_BREAK)
330
331/*
332 * Private routines
333 */
334
335Z85C30_STATIC void z85c30_init(int minor);
336
337Z85C30_STATIC int z85c30_set_attributes(
338  int                   minor,
339  const struct termios *t
340);
341
342Z85C30_STATIC int z85c30_open(
343  int major,
344  int minor,
345  void  * arg
346);
347
348Z85C30_STATIC int z85c30_close(
349  int major,
350  int minor,
351  void  * arg
352);
353
354Z85C30_STATIC void z85c30_write_polled(
355  int   minor, 
356  char  cChar
357);
358
359Z85C30_STATIC int z85c30_assert_RTS(
360  int minor
361);
362
363Z85C30_STATIC int z85c30_negate_RTS(
364  int minor
365);
366
367Z85C30_STATIC int z85c30_assert_DTR(
368  int minor
369);
370
371Z85C30_STATIC int z85c30_negate_DTR(
372  int minor
373);
374
375Z85C30_STATIC void z85c30_initialize_interrupts(int minor);
376
377Z85C30_STATIC int z85c30_flush(int major, int minor, void *arg);
378
379Z85C30_STATIC int z85c30_write_support_int(
380  int   minor,
381  const char *buf,
382  int   len
383);
384
385Z85C30_STATIC int z85c30_write_support_polled(
386  int   minor,
387  const char *buf,
388  int   len
389);
390
391Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
392  int minor
393);
394
395#ifdef __cplusplus
396}
397#endif
398
399#endif
Note: See TracBrowser for help on using the repository browser.