source: rtems/c/src/libchip/serial/z85c30_p.h @ 3ed964f9

4.104.11
Last change on this file since 3ed964f9 was 3ed964f9, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 9, 2010 at 10:44:05 PM

adapt _write_ functions to new prototype

  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*
2 *  This include file contains all private driver definitions for the
3 *  Zilog z85c30.
4 *
5 *  COPYRIGHT (c) 1998 by Radstone Technology
6 *
7 *
8 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
9 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
10 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
11 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
12 *
13 * You are hereby granted permission to use, copy, modify, and distribute
14 * this file, provided that this notice, plus the above copyright notice
15 * and disclaimer, appears in all copies. Radstone Technology will provide
16 * no support for this code.
17 *
18 *  COPYRIGHT (c) 1989-1997.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may in
22 *  the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 *  $Id$
26 */
27
28#ifndef __Z85C30_P_H
29#define __Z85C30_P_H
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35/*
36 *  Define Z85C30_STATIC to nothing while debugging so the entry points
37 *  will show up in the symbol table.
38 */
39
40#define Z85C30_STATIC
41
42/* #define Z85C30_STATIC static */
43
44/* bit values for write register 0 */
45/* command register */
46
47#define SCC_WR0_SEL_WR0   0x00
48#define SCC_WR0_SEL_WR1   0x01
49#define SCC_WR0_SEL_WR2   0x02
50#define SCC_WR0_SEL_WR3   0x03
51#define SCC_WR0_SEL_WR4   0x04
52#define SCC_WR0_SEL_WR5   0x05
53#define SCC_WR0_SEL_WR6   0x06
54#define SCC_WR0_SEL_WR7   0x07
55#define SCC_WR0_SEL_WR8   0x08
56#define SCC_WR0_SEL_WR9   0x09
57#define SCC_WR0_SEL_WR10  0x0a
58#define SCC_WR0_SEL_WR11  0x0b
59#define SCC_WR0_SEL_WR12  0x0c
60#define SCC_WR0_SEL_WR13  0x0d
61#define SCC_WR0_SEL_WR14  0x0e
62#define SCC_WR0_SEL_WR15  0x0f
63#define SCC_WR0_SEL_RD0   0x00
64#define SCC_WR0_SEL_RD1   0x01
65#define SCC_WR0_SEL_RD2   0x02
66#define SCC_WR0_SEL_RD3   0x03
67#define SCC_WR0_SEL_RD4   0x04
68#define SCC_WR0_SEL_RD5   0x05
69#define SCC_WR0_SEL_RD6   0x06
70#define SCC_WR0_SEL_RD7   0x07
71#define SCC_WR0_SEL_RD8   0x08
72#define SCC_WR0_SEL_RD9   0x09
73#define SCC_WR0_SEL_RD10  0x0a
74#define SCC_WR0_SEL_RD11  0x0b
75#define SCC_WR0_SEL_RD12  0x0c
76#define SCC_WR0_SEL_RD13  0x0d
77#define SCC_WR0_SEL_RD14  0x0e
78#define SCC_WR0_SEL_RD15  0x0f
79#define SCC_WR0_NULL_CODE 0x00
80#define SCC_WR0_RST_INT   0x10
81#define SCC_WR0_SEND_ABORT  0x18
82#define SCC_WR0_EN_INT_RX 0x20
83#define SCC_WR0_RST_TX_INT  0x28
84#define SCC_WR0_ERR_RST   0x30
85#define SCC_WR0_RST_HI_IUS  0x38
86#define SCC_WR0_RST_RX_CRC  0x40
87#define SCC_WR0_RST_TX_CRC  0x80
88#define SCC_WR0_RST_TX_UND  0xc0
89
90/* write register 2 */
91/* interrupt vector */
92
93/* bit values for write register 1 */
94/* tx/rx interrupt and data transfer mode definition */
95
96#define SCC_WR1_EXT_INT_EN  0x01
97#define SCC_WR1_TX_INT_EN   0x02
98#define SCC_WR1_PARITY      0x04
99#define SCC_WR1_RX_INT_DIS  0x00
100#define SCC_WR1_RX_INT_FIR  0x08
101#define SCC_WR1_INT_ALL_RX  0x10
102#define SCC_WR1_RX_INT_SPE  0x18
103#define SCC_WR1_RDMA_RECTR  0x20
104#define SCC_WR1_RDMA_FUNC   0x40
105#define SCC_WR1_RDMA_EN     0x80
106
107#define SCC_ENABLE_ALL_INTR \
108    (SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX)
109
110#define SCC_DISABLE_ALL_INTR 0x00
111
112#define SCC_ENABLE_ALL_INTR_EXCEPT_TX \
113    (SCC_WR1_EXT_INT_EN | SCC_WR1_INT_ALL_RX)
114
115/* bit values for write register 3 */
116/* receive parameters and control */
117
118#define SCC_WR3_RX_EN   0x01
119#define SCC_WR3_SYNC_CHAR 0x02
120#define SCC_WR3_ADR_SEARCH  0x04
121#define SCC_WR3_RX_CRC_EN 0x08
122#define SCC_WR3_ENTER_HUNT  0x10
123#define SCC_WR3_AUTO_EN   0x20
124#define SCC_WR3_RX_5_BITS 0x00
125#define SCC_WR3_RX_7_BITS 0x40
126#define SCC_WR3_RX_6_BITS 0x80
127#define SCC_WR3_RX_8_BITS 0xc0
128
129/* bit values for write register 4 */
130/* tx/rx misc parameters and modes */
131
132#define SCC_WR4_PAR_EN    0x01
133#define SCC_WR4_PAR_EVEN  0x02
134#define SCC_WR4_SYNC_EN   0x00
135#define SCC_WR4_1_STOP    0x04
136#define SCC_WR4_2_STOP    0x0c
137#define SCC_WR4_8_SYNC    0x00
138#define SCC_WR4_16_SYNC   0x10
139#define SCC_WR4_SDLC    0x20
140#define SCC_WR4_EXT_SYNC  0x30
141#define SCC_WR4_1_CLOCK   0x00
142#define SCC_WR4_16_CLOCK  0x40
143#define SCC_WR4_32_CLOCK  0x80
144#define SCC_WR4_64_CLOCK  0xc0
145
146/* bit values for write register 5 */
147/* transmit parameter and controls */
148
149#define SCC_WR5_TX_CRC_EN 0x01
150#define SCC_WR5_RTS   0x02
151#define SCC_WR5_SDLC    0x04
152#define SCC_WR5_TX_EN   0x08
153#define SCC_WR5_SEND_BRK  0x10
154
155#define SCC_WR5_TX_5_BITS 0x00
156#define SCC_WR5_TX_7_BITS 0x20
157#define SCC_WR5_TX_6_BITS 0x40
158#define SCC_WR5_TX_8_BITS 0x60
159#define SCC_WR5_DTR   0x80
160
161/* write register 6 */
162/* sync chars or sdlc address field */
163
164/* write register 7 */
165/* sync char or sdlc flag */
166
167/* write register 8 */
168/* transmit buffer */
169
170/* bit values for write register 9 */
171/* master interrupt control */
172
173#define SCC_WR9_VIS   0x01
174#define SCC_WR9_NV    0x02
175#define SCC_WR9_DLC   0x04
176#define SCC_WR9_MIE   0x08
177#define SCC_WR9_STATUS_HI 0x10
178#define SCC_WR9_NO_RST    0x00
179#define SCC_WR9_CH_B_RST  0x40
180#define SCC_WR9_CH_A_RST  0x80
181#define SCC_WR9_HDWR_RST  0xc0
182
183/* bit values for write register 10 */
184/* misc tx/rx control bits */
185
186#define SCC_WR10_6_BIT_SYNC 0x01
187#define SCC_WR10_LOOP_MODE  0x02
188#define SCC_WR10_ABORT_UND  0x04
189#define SCC_WR10_MARK_IDLE  0x08
190#define SCC_WR10_ACT_POLL 0x10
191#define SCC_WR10_NRZ    0x00
192#define SCC_WR10_NRZI   0x20
193#define SCC_WR10_FM1    0x40
194#define SCC_WR10_FM0    0x60
195#define SCC_WR10_CRC_PRESET 0x80
196
197/* bit values for write register 11 */
198/* clock mode control */
199
200#define SCC_WR11_OUT_XTAL 0x00
201#define SCC_WR11_OUT_TX_CLK 0x01
202#define SCC_WR11_OUT_BR_GEN 0x02
203#define SCC_WR11_OUT_DPLL 0x03
204#define SCC_WR11_TRXC_OI  0x04
205#define SCC_WR11_TX_RTXC  0x00
206#define SCC_WR11_TX_TRXC  0x08
207#define SCC_WR11_TX_BR_GEN  0x10
208#define SCC_WR11_TX_DPLL  0x18
209#define SCC_WR11_RX_RTXC  0x00
210#define SCC_WR11_RX_TRXC  0x20
211#define SCC_WR11_RX_BR_GEN  0x40
212#define SCC_WR11_RX_DPLL  0x60
213#define SCC_WR11_RTXC_XTAL  0x80
214
215/* write register 12 */
216/* lower byte of baud rate generator time constant */
217
218/* write register 13 */
219/* upper byte of baud rate generator time constant */
220
221/* bit values for write register 14 */
222/* misc control bits */
223
224#define SCC_WR14_BR_EN    0x01
225#define SCC_WR14_BR_SRC   0x02
226#define SCC_WR14_DTR_FUNC 0x04
227#define SCC_WR14_AUTO_ECHO  0x08
228#define SCC_WR14_LCL_LOOP 0x10
229#define SCC_WR14_NULL   0x00
230#define SCC_WR14_SEARCH   0x20
231#define SCC_WR14_RST_CLK  0x40
232#define SCC_WR14_DIS_DPLL 0x60
233#define SCC_WR14_SRC_BR   0x80
234#define SCC_WR14_SRC_RTXC 0xa0
235#define SCC_WR14_FM_MODE  0xc0
236#define SCC_WR14_NRZI   0xe0
237
238/* bit values for write register 15 */
239/* external/status interrupt control */
240
241#define SCC_WR15_ZERO_CNT 0x02
242#define SCC_WR15_CD_IE    0x08
243#define SCC_WR15_SYNC_IE  0x10
244#define SCC_WR15_CTS_IE   0x20
245#define SCC_WR15_TX_UND_IE  0x40
246#define SCC_WR15_BREAK_IE 0x80
247
248/* bit values for read register 0 */
249/* tx/rx buffer status and external status  */
250
251#define SCC_RR0_RX_AVAIL  0x01
252#define SCC_RR0_ZERO_CNT  0x02
253#define SCC_RR0_TX_EMPTY  0x04
254#define SCC_RR0_CD    0x08
255#define SCC_RR0_SYNC    0x10
256#define SCC_RR0_CTS   0x20
257#define SCC_RR0_TX_UND    0x40
258#define SCC_RR0_BREAK   0x80
259
260/* bit values for read register 1 */
261
262#define SCC_RR1_ALL_SENT  0x01
263#define SCC_RR1_RES_CD_2  0x02
264#define SCC_RR1_RES_CD_1  0x01
265#define SCC_RR1_RES_CD_0  0x08
266#define SCC_RR1_PAR_ERR   0x10
267#define SCC_RR1_RX_OV_ERR 0x20
268#define SCC_RR1_CRC_ERR   0x40
269#define SCC_RR1_END_FRAME 0x80
270
271/* read register 2 */
272/* interrupt vector */
273
274/* bit values for read register 3 */
275/* interrupt pending register */
276
277#define SCC_RR3_B_EXT_IP  0x01
278#define SCC_RR3_B_TX_IP   0x02
279#define SCC_RR3_B_RX_IP   0x04
280#define SCC_RR3_A_EXT_IP  0x08
281#define SCC_RR3_A_TX_IP   0x10
282#define SCC_RR3_A_RX_IP   0x20
283
284/* read register 8 */
285/* receive data register */
286
287/* bit values for read register 10 */
288/* misc status bits */
289
290#define SCC_RR10_ON_LOOP  0x02
291#define SCC_RR10_LOOP_SEND  0x10
292#define SCC_RR10_2_CLK_MIS  0x40
293#define SCC_RR10_1_CLK_MIS  0x80
294
295/* read register 12 */
296/* lower byte of time constant */
297
298/* read register 13 */
299/* upper byte of time constant */
300
301/* bit values for read register 15 */
302/* external/status ie bits */
303
304#define SCC_RR15_ZERO_CNT 0x02
305#define SCC_RR15_CD_IE    0x08
306#define SCC_RR15_SYNC_IE  0x10
307#define SCC_RR15_CTS_IE   0x20
308#define SCC_RR15_TX_UND_IE  0x40
309#define SCC_RR15_BREAK_IE 0x80
310
311typedef struct _z85c30_context
312{
313  uint8_t   ucModemCtrl;
314} z85c30_context;
315
316/*
317 * The following macro calculates the Baud constant. For the Z85C30 chip.
318 *
319 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
320 *       eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
321 */
322
323#define Z85C30_Baud( _clock, _baud_rate  )   \
324  ( ((_clock) /(  16 * 2 * _baud_rate))  - 2)
325
326#define Z85C30_Status_Is_RX_character_available(_status) \
327  ((_status) & SCC_RR0_RX_AVAIL)
328
329#define Z85C30_Status_Is_TX_buffer_empty(_status) \
330  ((_status) & SCC_RR0_TX_EMPTY)
331
332#define Z85C30_Status_Is_CTS_asserted(_status) \
333  ((_status) & SCC_RR0_CTS)
334
335#define Z85C30_Status_Is_break_abort(_status) \
336  ((_status) & SCC_RR0_BREAK)
337
338/*
339 * Private routines
340 */
341
342Z85C30_STATIC void z85c30_init(int minor);
343
344Z85C30_STATIC int z85c30_set_attributes(
345  int                   minor,
346  const struct termios *t
347);
348
349Z85C30_STATIC int z85c30_open(
350  int major,
351  int minor,
352  void  * arg
353);
354
355Z85C30_STATIC int z85c30_close(
356  int major,
357  int minor,
358  void  * arg
359);
360
361Z85C30_STATIC void z85c30_write_polled(
362  int   minor,
363  char  cChar
364);
365
366Z85C30_STATIC int z85c30_assert_RTS(
367  int minor
368);
369
370Z85C30_STATIC int z85c30_negate_RTS(
371  int minor
372);
373
374Z85C30_STATIC int z85c30_assert_DTR(
375  int minor
376);
377
378Z85C30_STATIC int z85c30_negate_DTR(
379  int minor
380);
381
382Z85C30_STATIC void z85c30_initialize_interrupts(int minor);
383
384Z85C30_STATIC ssize_t z85c30_write_support_int(
385  int   minor,
386  const char *buf,
387  size_t len
388);
389
390Z85C30_STATIC ssize_t z85c30_write_support_polled(
391  int   minor,
392  const char *buf,
393  size_t len
394);
395
396Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
397  int minor
398);
399
400Z85C30_STATIC void z85c30_enable_interrupts(
401  int minor,
402  int interrupt_mask
403);
404
405#ifdef __cplusplus
406}
407#endif
408
409#endif
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