1 | /* |
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2 | * This file contains the console driver chip level routines for the |
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3 | * Zilog z85c30 chip. |
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4 | * |
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5 | * The Zilog Z8530 is also available as: |
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6 | * |
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7 | * + Intel 82530 |
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8 | * + AMD ??? |
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9 | * |
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10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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11 | * |
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12 | * |
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13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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17 | * |
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18 | * You are hereby granted permission to use, copy, modify, and distribute |
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19 | * this file, provided that this notice, plus the above copyright notice |
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20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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21 | * no support for this code. |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * |
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26 | * The license and distribution terms for this file may be |
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27 | * found in the file LICENSE in this distribution or at |
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28 | * http://www.rtems.org/license/LICENSE. |
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29 | */ |
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30 | |
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31 | #include <rtems.h> |
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32 | #include <rtems/libio.h> |
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33 | #include <rtems/score/sysstate.h> |
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34 | #include <stdlib.h> |
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35 | |
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36 | #include <libchip/serial.h> |
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37 | #include <libchip/sersupp.h> |
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38 | #include "z85c30_p.h" |
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39 | |
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40 | /* |
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41 | * Flow control is only supported when using interrupts |
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42 | */ |
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43 | |
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44 | const console_flow z85c30_flow_RTSCTS = { |
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45 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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46 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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47 | }; |
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48 | |
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49 | const console_flow z85c30_flow_DTRCTS = { |
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50 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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51 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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52 | }; |
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53 | |
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54 | /* |
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55 | * Exported driver function table |
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56 | */ |
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57 | |
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58 | const console_fns z85c30_fns = { |
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59 | libchip_serial_default_probe, /* deviceProbe */ |
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60 | z85c30_open, /* deviceFirstOpen */ |
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61 | NULL, /* deviceLastClose */ |
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62 | NULL, /* deviceRead */ |
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63 | z85c30_write_support_int, /* deviceWrite */ |
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64 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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65 | z85c30_write_polled, /* deviceWritePolled */ |
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66 | NULL, /* deviceSetAttributes */ |
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67 | true /* deviceOutputUsesInterrupts */ |
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68 | }; |
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69 | |
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70 | const console_fns z85c30_fns_polled = { |
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71 | libchip_serial_default_probe, /* deviceProbe */ |
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72 | z85c30_open, /* deviceFirstOpen */ |
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73 | z85c30_close, /* deviceLastClose */ |
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74 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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75 | z85c30_write_support_polled, /* deviceWrite */ |
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76 | z85c30_init, /* deviceInitialize */ |
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77 | z85c30_write_polled, /* deviceWritePolled */ |
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78 | NULL, /* deviceSetAttributes */ |
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79 | false /* deviceOutputUsesInterrupts */ |
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80 | }; |
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81 | |
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82 | #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) |
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83 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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84 | #endif |
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85 | |
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86 | /* |
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87 | * z85c30_initialize_port |
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88 | * |
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89 | * initialize a z85c30 Port |
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90 | */ |
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91 | |
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92 | Z85C30_STATIC void z85c30_initialize_port( |
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93 | int minor |
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94 | ) |
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95 | { |
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96 | uintptr_t ulCtrlPort; |
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97 | uintptr_t ulBaudDivisor; |
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98 | setRegister_f setReg; |
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99 | |
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100 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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101 | setReg = Console_Port_Tbl[minor]->setRegister; |
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102 | |
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103 | /* |
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104 | * Using register 4 |
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105 | * Set up the clock rate is 16 times the data |
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106 | * rate, 8 bit sync char, 1 stop bit, no parity |
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107 | */ |
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108 | |
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109 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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110 | |
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111 | /* |
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112 | * Set up for 8 bits/character on receive with |
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113 | * receiver disable via register 3 |
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114 | */ |
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115 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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116 | |
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117 | /* |
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118 | * Set up for 8 bits/character on transmit |
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119 | * with transmitter disable via register 5 |
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120 | */ |
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121 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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122 | |
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123 | /* |
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124 | * Clear misc control bits |
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125 | */ |
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126 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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127 | |
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128 | /* |
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129 | * Setup the source of the receive and xmit |
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130 | * clock as BRG output and the transmit clock |
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131 | * as the output source for TRxC pin via register 11 |
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132 | */ |
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133 | (*setReg)( |
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134 | ulCtrlPort, |
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135 | SCC_WR0_SEL_WR11, |
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136 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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137 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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138 | ); |
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139 | |
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140 | ulBaudDivisor = Z85C30_Baud( |
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141 | (uint32_t) Console_Port_Tbl[minor]->ulClock, |
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142 | (uint32_t) ((uintptr_t)Console_Port_Tbl[minor]->pDeviceParams) |
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143 | ); |
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144 | |
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145 | /* |
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146 | * Setup the lower 8 bits time constants=1E. |
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147 | * If the time constans=1E, then the desire |
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148 | * baud rate will be equilvalent to 9600, via register 12. |
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149 | */ |
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150 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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151 | |
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152 | /* |
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153 | * using register 13 |
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154 | * Setup the upper 8 bits time constant |
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155 | */ |
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156 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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157 | |
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158 | /* |
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159 | * Enable the baud rate generator enable with clock from the |
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160 | * SCC's PCLK input via register 14. |
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161 | */ |
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162 | (*setReg)( |
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163 | ulCtrlPort, |
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164 | SCC_WR0_SEL_WR14, |
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165 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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166 | ); |
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167 | |
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168 | /* |
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169 | * We are only interested in CTS state changes |
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170 | */ |
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171 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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172 | |
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173 | /* |
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174 | * Reset errors |
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175 | */ |
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176 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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177 | |
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178 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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179 | |
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180 | /* |
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181 | * Enable the receiver via register 3 |
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182 | */ |
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183 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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184 | |
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185 | /* |
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186 | * Enable the transmitter pins set via register 5. |
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187 | */ |
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188 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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189 | |
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190 | /* |
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191 | * Disable interrupts |
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192 | */ |
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193 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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194 | |
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195 | /* |
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196 | * Reset TX CRC |
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197 | */ |
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198 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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199 | |
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200 | /* |
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201 | * Reset interrupts |
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202 | */ |
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203 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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204 | } |
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205 | |
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206 | /* |
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207 | * z85c30_open |
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208 | */ |
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209 | |
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210 | Z85C30_STATIC int z85c30_open( |
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211 | int major, |
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212 | int minor, |
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213 | void *arg |
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214 | ) |
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215 | { |
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216 | |
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217 | z85c30_initialize_port(minor); |
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218 | |
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219 | /* |
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220 | * Assert DTR |
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221 | */ |
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222 | |
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223 | if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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224 | z85c30_assert_DTR(minor); |
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225 | } |
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226 | |
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227 | return(RTEMS_SUCCESSFUL); |
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228 | } |
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229 | |
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230 | /* |
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231 | * z85c30_close |
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232 | */ |
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233 | |
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234 | Z85C30_STATIC int z85c30_close( |
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235 | int major, |
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236 | int minor, |
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237 | void *arg |
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238 | ) |
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239 | { |
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240 | /* |
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241 | * Negate DTR |
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242 | */ |
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243 | |
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244 | if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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245 | z85c30_negate_DTR(minor); |
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246 | } |
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247 | |
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248 | return(RTEMS_SUCCESSFUL); |
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249 | } |
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250 | |
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251 | /* |
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252 | * z85c30_init |
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253 | */ |
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254 | |
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255 | Z85C30_STATIC void z85c30_init(int minor) |
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256 | { |
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257 | uintptr_t ulCtrlPort; |
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258 | z85c30_context *pz85c30Context; |
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259 | setRegister_f setReg; |
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260 | getRegister_f getReg; |
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261 | |
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262 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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263 | setReg = Console_Port_Tbl[minor]->setRegister; |
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264 | getReg = Console_Port_Tbl[minor]->getRegister; |
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265 | |
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266 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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267 | |
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268 | Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context; |
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269 | |
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270 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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271 | |
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272 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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273 | if ( ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort2 ) { |
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274 | /* |
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275 | * This is channel A |
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276 | */ |
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277 | /* |
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278 | * Ensure port state machine is reset |
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279 | */ |
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280 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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281 | |
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282 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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283 | |
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284 | } else { |
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285 | /* |
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286 | * This is channel B |
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287 | */ |
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288 | /* |
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289 | * Ensure port state machine is reset |
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290 | */ |
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291 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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292 | |
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293 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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294 | } |
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295 | } |
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296 | |
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297 | /* |
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298 | * These routines provide control of the RTS and DTR lines |
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299 | */ |
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300 | |
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301 | /* |
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302 | * z85c30_assert_RTS |
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303 | */ |
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304 | |
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305 | Z85C30_STATIC int z85c30_assert_RTS(int minor) |
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306 | { |
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307 | rtems_interrupt_level Irql; |
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308 | z85c30_context *pz85c30Context; |
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309 | setRegister_f setReg; |
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310 | |
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311 | setReg = Console_Port_Tbl[minor]->setRegister; |
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312 | |
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313 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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314 | |
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315 | /* |
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316 | * Assert RTS |
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317 | */ |
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318 | |
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319 | rtems_interrupt_disable(Irql); |
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320 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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321 | (*setReg)( |
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322 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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323 | SCC_WR0_SEL_WR5, |
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324 | pz85c30Context->ucModemCtrl |
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325 | ); |
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326 | rtems_interrupt_enable(Irql); |
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327 | return 0; |
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328 | } |
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329 | |
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330 | /* |
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331 | * z85c30_negate_RTS |
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332 | */ |
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333 | |
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334 | Z85C30_STATIC int z85c30_negate_RTS(int minor) |
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335 | { |
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336 | rtems_interrupt_level Irql; |
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337 | z85c30_context *pz85c30Context; |
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338 | setRegister_f setReg; |
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339 | |
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340 | setReg = Console_Port_Tbl[minor]->setRegister; |
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341 | |
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342 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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343 | |
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344 | /* |
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345 | * Negate RTS |
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346 | */ |
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347 | |
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348 | rtems_interrupt_disable(Irql); |
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349 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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350 | (*setReg)( |
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351 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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352 | SCC_WR0_SEL_WR5, |
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353 | pz85c30Context->ucModemCtrl |
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354 | ); |
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355 | rtems_interrupt_enable(Irql); |
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356 | return 0; |
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357 | } |
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358 | |
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359 | /* |
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360 | * These flow control routines utilise a connection from the local DTR |
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361 | * line to the remote CTS line |
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362 | */ |
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363 | |
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364 | /* |
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365 | * z85c30_assert_DTR |
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366 | */ |
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367 | |
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368 | Z85C30_STATIC int z85c30_assert_DTR(int minor) |
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369 | { |
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370 | rtems_interrupt_level Irql; |
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371 | z85c30_context *pz85c30Context; |
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372 | setRegister_f setReg; |
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373 | |
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374 | setReg = Console_Port_Tbl[minor]->setRegister; |
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375 | |
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376 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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377 | |
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378 | /* |
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379 | * Assert DTR |
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380 | */ |
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381 | |
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382 | rtems_interrupt_disable(Irql); |
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383 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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384 | (*setReg)( |
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385 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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386 | SCC_WR0_SEL_WR5, |
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387 | pz85c30Context->ucModemCtrl |
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388 | ); |
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389 | rtems_interrupt_enable(Irql); |
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390 | return 0; |
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391 | } |
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392 | |
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393 | /* |
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394 | * z85c30_negate_DTR |
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395 | */ |
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396 | |
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397 | Z85C30_STATIC int z85c30_negate_DTR(int minor) |
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398 | { |
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399 | rtems_interrupt_level Irql; |
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400 | z85c30_context *pz85c30Context; |
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401 | setRegister_f setReg; |
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402 | |
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403 | setReg = Console_Port_Tbl[minor]->setRegister; |
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404 | |
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405 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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406 | |
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407 | /* |
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408 | * Negate DTR |
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409 | */ |
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410 | |
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411 | rtems_interrupt_disable(Irql); |
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412 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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413 | (*setReg)( |
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414 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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415 | SCC_WR0_SEL_WR5, |
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416 | pz85c30Context->ucModemCtrl |
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417 | ); |
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418 | rtems_interrupt_enable(Irql); |
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419 | return 0; |
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420 | } |
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421 | |
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422 | /* |
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423 | * z85c30_set_attributes |
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424 | * |
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425 | * This function sets the SCC channel to reflect the requested termios |
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426 | * port settings. |
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427 | */ |
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428 | |
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429 | Z85C30_STATIC int z85c30_set_attributes( |
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430 | int minor, |
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431 | const struct termios *t |
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432 | ) |
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433 | { |
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434 | uintptr_t ulCtrlPort; |
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435 | uint32_t ulBaudDivisor; |
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436 | uint32_t wr3; |
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437 | uint32_t wr4; |
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438 | uint32_t wr5; |
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439 | int baud_requested; |
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440 | setRegister_f setReg; |
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441 | rtems_interrupt_level Irql; |
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442 | |
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443 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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444 | setReg = Console_Port_Tbl[minor]->setRegister; |
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445 | |
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446 | /* |
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447 | * Calculate the baud rate divisor |
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448 | */ |
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449 | |
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450 | baud_requested = t->c_cflag & CBAUD; |
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451 | if (!baud_requested) |
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452 | baud_requested = B9600; /* default to 9600 baud */ |
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453 | |
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454 | ulBaudDivisor = Z85C30_Baud( |
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455 | (uint32_t) Console_Port_Tbl[minor]->ulClock, |
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456 | (uint32_t) rtems_termios_baud_to_number( baud_requested ) |
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457 | ); |
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458 | |
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459 | wr3 = SCC_WR3_RX_EN; |
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460 | wr4 = SCC_WR4_16_CLOCK; |
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461 | wr5 = SCC_WR5_TX_EN; |
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462 | |
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463 | /* |
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464 | * Parity |
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465 | */ |
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466 | |
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467 | if (t->c_cflag & PARENB) { |
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468 | wr4 |= SCC_WR4_PAR_EN; |
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469 | if (!(t->c_cflag & PARODD)) |
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470 | wr4 |= SCC_WR4_PAR_EVEN; |
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471 | } |
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472 | |
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473 | /* |
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474 | * Character Size |
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475 | */ |
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476 | |
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477 | if (t->c_cflag & CSIZE) { |
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478 | switch (t->c_cflag & CSIZE) { |
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479 | case CS5: break; |
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480 | case CS6: wr3 |= SCC_WR3_RX_6_BITS; wr5 |= SCC_WR5_TX_6_BITS; break; |
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481 | case CS7: wr3 |= SCC_WR3_RX_7_BITS; wr5 |= SCC_WR5_TX_7_BITS; break; |
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482 | case CS8: wr3 |= SCC_WR3_RX_8_BITS; wr5 |= SCC_WR5_TX_8_BITS; break; |
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483 | } |
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484 | } else { |
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485 | wr3 |= SCC_WR3_RX_8_BITS; /* default to 9600,8,N,1 */ |
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486 | wr5 |= SCC_WR5_TX_8_BITS; /* default to 9600,8,N,1 */ |
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487 | } |
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488 | |
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489 | /* |
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490 | * Stop Bits |
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491 | */ |
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492 | |
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493 | if (t->c_cflag & CSTOPB) { |
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494 | wr4 |= SCC_WR4_2_STOP; /* 2 stop bits */ |
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495 | } else { |
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496 | wr4 |= SCC_WR4_1_STOP; /* 1 stop bits */ |
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497 | } |
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498 | |
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499 | /* |
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500 | * Now actually set the chip |
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501 | */ |
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502 | |
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503 | rtems_interrupt_disable(Irql); |
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504 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 ); |
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505 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 ); |
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506 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 ); |
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507 | |
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508 | /* |
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509 | * Setup the lower 8 bits time constants=1E. |
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510 | * If the time constans=1E, then the desire |
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511 | * baud rate will be equilvalent to 9600, via register 12. |
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512 | */ |
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513 | |
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514 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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515 | |
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516 | /* |
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517 | * using register 13 |
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518 | * Setup the upper 8 bits time constant |
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519 | */ |
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520 | |
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521 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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522 | |
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523 | rtems_interrupt_enable(Irql); |
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524 | |
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525 | return 0; |
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526 | } |
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527 | |
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528 | /* |
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529 | * z85c30_process |
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530 | * |
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531 | * This is the per port ISR handler. |
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532 | */ |
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533 | |
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534 | Z85C30_STATIC void z85c30_process( |
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535 | int minor, |
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536 | uint8_t ucIntPend |
---|
537 | ) |
---|
538 | { |
---|
539 | uint32_t ulCtrlPort; |
---|
540 | volatile uint8_t z85c30_status; |
---|
541 | char cChar; |
---|
542 | setRegister_f setReg; |
---|
543 | getRegister_f getReg; |
---|
544 | |
---|
545 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
546 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
547 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
548 | |
---|
549 | /* |
---|
550 | * Deal with any received characters |
---|
551 | */ |
---|
552 | |
---|
553 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
554 | { |
---|
555 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
556 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
557 | break; |
---|
558 | } |
---|
559 | |
---|
560 | /* |
---|
561 | * Return the character read. |
---|
562 | */ |
---|
563 | |
---|
564 | cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
565 | |
---|
566 | rtems_termios_enqueue_raw_characters( |
---|
567 | Console_Port_Data[minor].termios_data, |
---|
568 | &cChar, |
---|
569 | 1 |
---|
570 | ); |
---|
571 | } |
---|
572 | |
---|
573 | /* |
---|
574 | * There could be a race condition here if there is not yet a TX |
---|
575 | * interrupt pending but the buffer is empty. This condition has |
---|
576 | * been seen before on other z8530 drivers but has not been seen |
---|
577 | * with this one. The typical solution is to use "vector includes |
---|
578 | * status" or to only look at the interrupts actually pending |
---|
579 | * in RR3. |
---|
580 | */ |
---|
581 | |
---|
582 | while (true) { |
---|
583 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
584 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
585 | /* |
---|
586 | * We'll get another interrupt when |
---|
587 | * the transmitter holding reg. becomes |
---|
588 | * free again and we are clear to send |
---|
589 | */ |
---|
590 | break; |
---|
591 | } |
---|
592 | |
---|
593 | #if 0 |
---|
594 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
595 | /* |
---|
596 | * We can't transmit yet |
---|
597 | */ |
---|
598 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
599 | /* |
---|
600 | * The next state change of CTS will wake us up |
---|
601 | */ |
---|
602 | break; |
---|
603 | } |
---|
604 | #endif |
---|
605 | |
---|
606 | rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1); |
---|
607 | if (rtems_termios_dequeue_characters( |
---|
608 | Console_Port_Data[minor].termios_data, 1)) { |
---|
609 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
610 | z85c30_negate_RTS(minor); |
---|
611 | } |
---|
612 | Console_Port_Data[minor].bActive = FALSE; |
---|
613 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
614 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
615 | break; |
---|
616 | } |
---|
617 | |
---|
618 | } |
---|
619 | |
---|
620 | if (ucIntPend & SCC_RR3_B_EXT_IP) { |
---|
621 | /* |
---|
622 | * Clear the external status interrupt |
---|
623 | */ |
---|
624 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
625 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
626 | } |
---|
627 | |
---|
628 | /* |
---|
629 | * Reset interrupts |
---|
630 | */ |
---|
631 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
632 | } |
---|
633 | |
---|
634 | /* |
---|
635 | * z85c30_isr |
---|
636 | * |
---|
637 | * This is the ISR handler for each Z8530. |
---|
638 | */ |
---|
639 | |
---|
640 | Z85C30_STATIC rtems_isr z85c30_isr( |
---|
641 | rtems_vector_number vector |
---|
642 | ) |
---|
643 | { |
---|
644 | int minor; |
---|
645 | uint32_t ulCtrlPort; |
---|
646 | volatile uint8_t ucIntPend; |
---|
647 | volatile uint8_t ucIntPendPort; |
---|
648 | getRegister_f getReg; |
---|
649 | |
---|
650 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
651 | if(Console_Port_Tbl[minor]->ulIntVector == vector && |
---|
652 | Console_Port_Tbl[minor]->deviceType == SERIAL_Z85C30 ) { |
---|
653 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort2; |
---|
654 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
655 | do { |
---|
656 | ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
657 | |
---|
658 | /* |
---|
659 | * If this is channel A select channel A status |
---|
660 | */ |
---|
661 | |
---|
662 | if (ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort1) { |
---|
663 | ucIntPendPort = ucIntPend >> 3; |
---|
664 | ucIntPendPort &= 7; |
---|
665 | } else { |
---|
666 | ucIntPendPort = ucIntPend &= 7; |
---|
667 | } |
---|
668 | |
---|
669 | if (ucIntPendPort) { |
---|
670 | z85c30_process(minor, ucIntPendPort); |
---|
671 | } |
---|
672 | } while (ucIntPendPort); |
---|
673 | } |
---|
674 | } |
---|
675 | } |
---|
676 | |
---|
677 | /* |
---|
678 | * z85c30_enable_interrupts |
---|
679 | * |
---|
680 | * This routine enables the specified interrupts for this minor. |
---|
681 | */ |
---|
682 | |
---|
683 | Z85C30_STATIC void z85c30_enable_interrupts( |
---|
684 | int minor, |
---|
685 | int interrupt_mask |
---|
686 | ) |
---|
687 | { |
---|
688 | uint32_t ulCtrlPort; |
---|
689 | setRegister_f setReg; |
---|
690 | |
---|
691 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
692 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
693 | |
---|
694 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask); |
---|
695 | } |
---|
696 | |
---|
697 | /* |
---|
698 | * z85c30_initialize_interrupts |
---|
699 | * |
---|
700 | * This routine initializes the port to use interrupts. |
---|
701 | */ |
---|
702 | |
---|
703 | Z85C30_STATIC void z85c30_initialize_interrupts( |
---|
704 | int minor |
---|
705 | ) |
---|
706 | { |
---|
707 | uint32_t ulCtrlPort1; |
---|
708 | setRegister_f setReg; |
---|
709 | |
---|
710 | ulCtrlPort1 = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
711 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
712 | |
---|
713 | |
---|
714 | z85c30_init(minor); |
---|
715 | |
---|
716 | Console_Port_Data[minor].bActive=FALSE; |
---|
717 | |
---|
718 | z85c30_initialize_port( minor ); |
---|
719 | |
---|
720 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
721 | z85c30_negate_RTS(minor); |
---|
722 | } |
---|
723 | |
---|
724 | #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) |
---|
725 | set_vector(z85c30_isr, Console_Port_Tbl[minor]->ulIntVector, 1); |
---|
726 | #endif |
---|
727 | |
---|
728 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
729 | |
---|
730 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0); /* XXX vector */ |
---|
731 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
732 | |
---|
733 | /* |
---|
734 | * Reset interrupts |
---|
735 | */ |
---|
736 | |
---|
737 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
738 | } |
---|
739 | |
---|
740 | /* |
---|
741 | * z85c30_write_support_int |
---|
742 | * |
---|
743 | * Console Termios output entry point. |
---|
744 | * |
---|
745 | */ |
---|
746 | |
---|
747 | Z85C30_STATIC ssize_t z85c30_write_support_int( |
---|
748 | int minor, |
---|
749 | const char *buf, |
---|
750 | size_t len) |
---|
751 | { |
---|
752 | uint32_t Irql; |
---|
753 | uint32_t ulCtrlPort; |
---|
754 | setRegister_f setReg; |
---|
755 | |
---|
756 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
757 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
758 | |
---|
759 | /* |
---|
760 | * We are using interrupt driven output and termios only sends us |
---|
761 | * one character at a time. |
---|
762 | */ |
---|
763 | |
---|
764 | if ( !len ) |
---|
765 | return 0; |
---|
766 | |
---|
767 | /* |
---|
768 | * Put the character out and enable interrupts if necessary. |
---|
769 | */ |
---|
770 | |
---|
771 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
772 | z85c30_assert_RTS(minor); |
---|
773 | } |
---|
774 | rtems_interrupt_disable(Irql); |
---|
775 | if ( Console_Port_Data[minor].bActive == FALSE) { |
---|
776 | Console_Port_Data[minor].bActive = TRUE; |
---|
777 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR); |
---|
778 | } |
---|
779 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf); |
---|
780 | rtems_interrupt_enable(Irql); |
---|
781 | |
---|
782 | return 0; |
---|
783 | } |
---|
784 | |
---|
785 | /* |
---|
786 | * z85c30_inbyte_nonblocking_polled |
---|
787 | * |
---|
788 | * This routine polls for a character. |
---|
789 | */ |
---|
790 | |
---|
791 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
---|
792 | int minor |
---|
793 | ) |
---|
794 | { |
---|
795 | volatile uint8_t z85c30_status; |
---|
796 | uint32_t ulCtrlPort; |
---|
797 | getRegister_f getReg; |
---|
798 | |
---|
799 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
800 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
801 | |
---|
802 | /* |
---|
803 | * return -1 if a character is not available. |
---|
804 | */ |
---|
805 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
806 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
807 | return -1; |
---|
808 | } |
---|
809 | |
---|
810 | /* |
---|
811 | * Return the character read. |
---|
812 | */ |
---|
813 | |
---|
814 | return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
815 | } |
---|
816 | |
---|
817 | /* |
---|
818 | * z85c30_write_support_polled |
---|
819 | * |
---|
820 | * Console Termios output entry point. |
---|
821 | * |
---|
822 | */ |
---|
823 | |
---|
824 | Z85C30_STATIC ssize_t z85c30_write_support_polled( |
---|
825 | int minor, |
---|
826 | const char *buf, |
---|
827 | size_t len) |
---|
828 | { |
---|
829 | int nwrite=0; |
---|
830 | |
---|
831 | /* |
---|
832 | * poll each byte in the string out of the port. |
---|
833 | */ |
---|
834 | while (nwrite < len) { |
---|
835 | z85c30_write_polled(minor, *buf++); |
---|
836 | nwrite++; |
---|
837 | } |
---|
838 | |
---|
839 | /* |
---|
840 | * return the number of bytes written. |
---|
841 | */ |
---|
842 | return nwrite; |
---|
843 | } |
---|
844 | |
---|
845 | /* |
---|
846 | * z85c30_write_polled |
---|
847 | * |
---|
848 | * This routine transmits a character using polling. |
---|
849 | */ |
---|
850 | |
---|
851 | Z85C30_STATIC void z85c30_write_polled( |
---|
852 | int minor, |
---|
853 | char cChar |
---|
854 | ) |
---|
855 | { |
---|
856 | volatile uint8_t z85c30_status; |
---|
857 | uint32_t ulCtrlPort; |
---|
858 | getRegister_f getReg; |
---|
859 | setRegister_f setReg; |
---|
860 | |
---|
861 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
862 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
863 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
864 | |
---|
865 | /* |
---|
866 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
867 | */ |
---|
868 | |
---|
869 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
---|
870 | |
---|
871 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
872 | /* |
---|
873 | * Yield while we wait |
---|
874 | */ |
---|
875 | #if 0 |
---|
876 | if (_System_state_Is_up(_System_state_Get())) { |
---|
877 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
878 | } |
---|
879 | #endif |
---|
880 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
881 | } |
---|
882 | |
---|
883 | /* |
---|
884 | * Write the character. |
---|
885 | */ |
---|
886 | |
---|
887 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar ); |
---|
888 | } |
---|