source: rtems/c/src/libchip/serial/z85c30.c @ 64a1529

4.104.11
Last change on this file since 64a1529 was 64a1529, checked in by Ralf Corsepius <ralf.corsepius@…>, on Sep 30, 2009 at 4:02:40 AM

2009-09-30 Ralf Corsépius <ralf.corsepius@…>

  • libchip/serial/z85c30.c, libchip/serial/ns16550.c, libchip/serial/mc68681.c: Reflect termios_baud_to_number having been renamed to rtems_termios_baud_to_number.
  • Property mode set to 100644
File size: 20.0 KB
Line 
1/*
2 *  This file contains the console driver chip level routines for the
3 *  Zilog z85c30 chip.
4 *
5 *  The Zilog Z8530 is also available as:
6 *
7 *    + Intel 82530
8 *    + AMD ???
9 *
10 *  COPYRIGHT (c) 1998 by Radstone Technology
11 *
12 *
13 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
14 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
16 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
17 *
18 * You are hereby granted permission to use, copy, modify, and distribute
19 * this file, provided that this notice, plus the above copyright notice
20 * and disclaimer, appears in all copies. Radstone Technology will provide
21 * no support for this code.
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#include <rtems.h>
34#include <rtems/libio.h>
35#include <stdlib.h>
36
37#include <libchip/serial.h>
38#include <libchip/sersupp.h>
39#include "z85c30_p.h"
40
41/*
42 * Flow control is only supported when using interrupts
43 */
44
45console_flow z85c30_flow_RTSCTS = {
46  z85c30_negate_RTS,    /* deviceStopRemoteTx */
47  z85c30_assert_RTS     /* deviceStartRemoteTx */
48};
49
50console_flow z85c30_flow_DTRCTS = {
51  z85c30_negate_DTR,    /* deviceStopRemoteTx */
52  z85c30_assert_DTR     /* deviceStartRemoteTx */
53};
54
55/*
56 * Exported driver function table
57 */
58
59console_fns z85c30_fns = {
60  libchip_serial_default_probe,  /* deviceProbe */
61  z85c30_open,                   /* deviceFirstOpen */
62  NULL,                          /* deviceLastClose */
63  NULL,                          /* deviceRead */
64  z85c30_write_support_int,      /* deviceWrite */
65  z85c30_initialize_interrupts,  /* deviceInitialize */
66  z85c30_write_polled,           /* deviceWritePolled */
67  NULL,                          /* deviceSetAttributes */
68  true                           /* deviceOutputUsesInterrupts */
69};
70
71console_fns z85c30_fns_polled = {
72  libchip_serial_default_probe,      /* deviceProbe */
73  z85c30_open,                       /* deviceFirstOpen */
74  z85c30_close,                      /* deviceLastClose */
75  z85c30_inbyte_nonblocking_polled,  /* deviceRead */
76  z85c30_write_support_polled,       /* deviceWrite */
77  z85c30_init,                       /* deviceInitialize */
78  z85c30_write_polled,               /* deviceWritePolled */
79  NULL,                              /* deviceSetAttributes */
80  false                              /* deviceOutputUsesInterrupts */
81};
82
83extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
84
85/*
86 *  z85c30_initialize_port
87 *
88 *  initialize a z85c30 Port
89 */
90
91Z85C30_STATIC void z85c30_initialize_port(
92  int minor
93)
94{
95  uint32_t        ulCtrlPort;
96  uint32_t        ulBaudDivisor;
97  setRegister_f   setReg;
98
99  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
100  setReg   = Console_Port_Tbl[minor].setRegister;
101
102  /*
103   * Using register 4
104   * Set up the clock rate is 16 times the data
105   * rate, 8 bit sync char, 1 stop bit, no parity
106   */
107
108  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK );
109
110  /*
111   * Set up for 8 bits/character on receive with
112   * receiver disable via register 3
113   */
114  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS );
115
116  /*
117   * Set up for 8 bits/character on transmit
118   * with transmitter disable via register 5
119   */
120  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS );
121
122  /*
123   * Clear misc control bits
124   */
125  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 );
126
127  /*
128   * Setup the source of the receive and xmit
129   * clock as BRG output and the transmit clock
130   * as the output source for TRxC pin via register 11
131   */
132  (*setReg)(
133    ulCtrlPort,
134    SCC_WR0_SEL_WR11,
135    SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI |
136      SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN
137  );
138
139  ulBaudDivisor = Z85C30_Baud(
140    (uint32_t) Console_Port_Tbl[minor].ulClock,
141    (uint32_t) Console_Port_Tbl[minor].pDeviceParams
142  );
143
144  /*
145   * Setup the lower 8 bits time constants=1E.
146   * If the time constans=1E, then the desire
147   * baud rate will be equilvalent to 9600, via register 12.
148   */
149  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
150
151  /*
152   * using register 13
153   * Setup the upper 8 bits time constant
154   */
155  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
156
157  /*
158   * Enable the baud rate generator enable with clock from the
159   * SCC's PCLK input via register 14.
160   */
161  (*setReg)(
162    ulCtrlPort,
163    SCC_WR0_SEL_WR14,
164    SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL
165  );
166
167  /*
168   * We are only interested in CTS state changes
169   */
170  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE );
171
172  /*
173   * Reset errors
174   */
175  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
176
177  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST );
178
179  /*
180   * Enable the receiver via register 3
181   */
182  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN );
183
184  /*
185   * Enable the transmitter pins set via register 5.
186   */
187  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN );
188
189  /*
190   * Disable interrupts
191   */
192  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 );
193
194  /*
195   * Reset TX CRC
196   */
197  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC );
198
199  /*
200   * Reset interrupts
201   */
202  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
203}
204
205/*
206 *  z85c30_open
207 */
208
209Z85C30_STATIC int z85c30_open(
210  int   major,
211  int   minor,
212  void *arg
213)
214{
215
216  z85c30_initialize_port(minor);
217
218  /*
219   * Assert DTR
220   */
221
222  if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) {
223    z85c30_assert_DTR(minor);
224  }
225
226  return(RTEMS_SUCCESSFUL);
227}
228
229/*
230 *  z85c30_close
231 */
232
233Z85C30_STATIC int z85c30_close(
234  int   major,
235  int   minor,
236  void *arg
237)
238{
239  /*
240   * Negate DTR
241   */
242
243  if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) {
244    z85c30_negate_DTR(minor);
245  }
246
247  return(RTEMS_SUCCESSFUL);
248}
249
250/*
251 *  z85c30_init
252 */
253
254Z85C30_STATIC void z85c30_init(int minor)
255{
256  uint32_t         ulCtrlPort;
257  uint8_t          dummy;
258  z85c30_context  *pz85c30Context;
259  setRegister_f    setReg;
260  getRegister_f    getReg;
261
262  setReg = Console_Port_Tbl[minor].setRegister;
263  getReg   = Console_Port_Tbl[minor].getRegister;
264
265  pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context));
266
267  Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context;
268
269  pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN;
270
271  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
272  if ( ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2 ) {
273    /*
274     * This is channel A
275     */
276    /*
277     * Ensure port state machine is reset
278     */
279    dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
280
281    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST);
282
283  } else {
284    /*
285     * This is channel B
286     */
287    /*
288     * Ensure port state machine is reset
289     */
290    dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
291
292    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST);
293  }
294}
295
296/*
297 * These routines provide control of the RTS and DTR lines
298 */
299
300/*
301 *  z85c30_assert_RTS
302 */
303
304Z85C30_STATIC int z85c30_assert_RTS(int minor)
305{
306  rtems_interrupt_level  Irql;
307  z85c30_context        *pz85c30Context;
308  setRegister_f          setReg;
309
310  setReg = Console_Port_Tbl[minor].setRegister;
311
312  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
313
314  /*
315   * Assert RTS
316   */
317
318  rtems_interrupt_disable(Irql);
319    pz85c30Context->ucModemCtrl|=SCC_WR5_RTS;
320    (*setReg)(
321      Console_Port_Tbl[minor].ulCtrlPort1,
322      SCC_WR0_SEL_WR5,
323      pz85c30Context->ucModemCtrl
324    );
325  rtems_interrupt_enable(Irql);
326  return 0;
327}
328
329/*
330 *  z85c30_negate_RTS
331 */
332
333Z85C30_STATIC int z85c30_negate_RTS(int minor)
334{
335  rtems_interrupt_level  Irql;
336  z85c30_context        *pz85c30Context;
337  setRegister_f          setReg;
338
339  setReg = Console_Port_Tbl[minor].setRegister;
340
341  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
342
343  /*
344   * Negate RTS
345   */
346
347  rtems_interrupt_disable(Irql);
348    pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS;
349    (*setReg)(
350      Console_Port_Tbl[minor].ulCtrlPort1,
351      SCC_WR0_SEL_WR5,
352      pz85c30Context->ucModemCtrl
353    );
354  rtems_interrupt_enable(Irql);
355  return 0;
356}
357
358/*
359 * These flow control routines utilise a connection from the local DTR
360 * line to the remote CTS line
361 */
362
363/*
364 *  z85c30_assert_DTR
365 */
366
367Z85C30_STATIC int z85c30_assert_DTR(int minor)
368{
369  rtems_interrupt_level  Irql;
370  z85c30_context        *pz85c30Context;
371  setRegister_f          setReg;
372
373  setReg = Console_Port_Tbl[minor].setRegister;
374
375  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
376
377  /*
378   * Assert DTR
379   */
380
381  rtems_interrupt_disable(Irql);
382    pz85c30Context->ucModemCtrl|=SCC_WR5_DTR;
383    (*setReg)(
384      Console_Port_Tbl[minor].ulCtrlPort1,
385      SCC_WR0_SEL_WR5,
386      pz85c30Context->ucModemCtrl
387  );
388  rtems_interrupt_enable(Irql);
389  return 0;
390}
391
392/*
393 *  z85c30_negate_DTR
394 */
395
396Z85C30_STATIC int z85c30_negate_DTR(int minor)
397{
398  rtems_interrupt_level  Irql;
399  z85c30_context        *pz85c30Context;
400  setRegister_f          setReg;
401
402  setReg = Console_Port_Tbl[minor].setRegister;
403
404  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
405
406  /*
407   * Negate DTR
408   */
409
410  rtems_interrupt_disable(Irql);
411    pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR;
412    (*setReg)(
413      Console_Port_Tbl[minor].ulCtrlPort1,
414      SCC_WR0_SEL_WR5,
415      pz85c30Context->ucModemCtrl
416  );
417  rtems_interrupt_enable(Irql);
418  return 0;
419}
420
421/*
422 *  z85c30_set_attributes
423 *
424 *  This function sets the SCC channel to reflect the requested termios
425 *  port settings.
426 */
427
428Z85C30_STATIC int z85c30_set_attributes(
429  int                   minor,
430  const struct termios *t
431)
432{
433  uint32_t               ulCtrlPort;
434  uint32_t               ulBaudDivisor;
435  uint32_t               wr3;
436  uint32_t               wr4;
437  uint32_t               wr5;
438  int                    baud_requested;
439  setRegister_f          setReg;
440  rtems_interrupt_level  Irql;
441
442  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
443  setReg     = Console_Port_Tbl[minor].setRegister;
444
445  /*
446   *  Calculate the baud rate divisor
447   */
448
449  baud_requested = t->c_cflag & CBAUD;
450  if (!baud_requested)
451    baud_requested = B9600;              /* default to 9600 baud */
452
453  ulBaudDivisor = Z85C30_Baud(
454    (uint32_t) Console_Port_Tbl[minor].ulClock,
455    (uint32_t) rtems_termios_baud_to_number( baud_requested )
456  );
457
458  wr3 = SCC_WR3_RX_EN;
459  wr4 = SCC_WR4_16_CLOCK;
460  wr5 = SCC_WR5_TX_EN;
461
462  /*
463   *  Parity
464   */
465
466  if (t->c_cflag & PARENB) {
467    wr4 |= SCC_WR4_PAR_EN;
468    if (!(t->c_cflag & PARODD))
469      wr4 |= SCC_WR4_PAR_EVEN;
470  }
471
472  /*
473   *  Character Size
474   */
475
476  if (t->c_cflag & CSIZE) {
477    switch (t->c_cflag & CSIZE) {
478      case CS5:   break;
479      case CS6:  wr3 |= SCC_WR3_RX_6_BITS;  wr5 |= SCC_WR5_TX_6_BITS;  break;
480      case CS7:  wr3 |= SCC_WR3_RX_7_BITS;  wr5 |= SCC_WR5_TX_7_BITS;  break;
481      case CS8:  wr3 |= SCC_WR3_RX_8_BITS;  wr5 |= SCC_WR5_TX_8_BITS;  break;
482    }
483  } else {
484    wr3 |= SCC_WR3_RX_8_BITS;       /* default to 9600,8,N,1 */
485    wr5 |= SCC_WR5_TX_8_BITS;       /* default to 9600,8,N,1 */
486  }
487
488  /*
489   *  Stop Bits
490   */
491
492  if (t->c_cflag & CSTOPB) {
493    wr4 |= SCC_WR4_2_STOP;                      /* 2 stop bits */
494  } else {
495    wr4 |= SCC_WR4_1_STOP;                      /* 1 stop bits */
496  }
497
498  /*
499   *  Now actually set the chip
500   */
501
502  rtems_interrupt_disable(Irql);
503    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 );
504    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 );
505    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 );
506
507    /*
508     * Setup the lower 8 bits time constants=1E.
509     * If the time constans=1E, then the desire
510     * baud rate will be equilvalent to 9600, via register 12.
511     */
512
513    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
514
515    /*
516     * using register 13
517     * Setup the upper 8 bits time constant
518     */
519
520    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
521
522  rtems_interrupt_enable(Irql);
523
524  return 0;
525}
526
527/*
528 *  z85c30_process
529 *
530 *  This is the per port ISR handler.
531 */
532
533Z85C30_STATIC void z85c30_process(
534  int        minor,
535  uint8_t    ucIntPend
536)
537{
538  uint32_t            ulCtrlPort;
539  volatile uint8_t    z85c30_status;
540  char                cChar;
541  setRegister_f       setReg;
542  getRegister_f       getReg;
543
544  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
545  setReg     = Console_Port_Tbl[minor].setRegister;
546  getReg     = Console_Port_Tbl[minor].getRegister;
547
548  /*
549   * Deal with any received characters
550   */
551
552  while (ucIntPend&SCC_RR3_B_RX_IP)
553  {
554    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
555    if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
556      break;
557    }
558
559    /*
560     * Return the character read.
561     */
562
563    cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
564
565    rtems_termios_enqueue_raw_characters(
566      Console_Port_Data[minor].termios_data,
567      &cChar,
568      1
569    );
570  }
571
572  /*
573   *  There could be a race condition here if there is not yet a TX
574   *  interrupt pending but the buffer is empty.  This condition has
575   *  been seen before on other z8530 drivers but has not been seen
576   *  with this one.  The typical solution is to use "vector includes
577   *  status" or to only look at the interrupts actually pending
578   *  in RR3.
579   */
580
581  while (true) {
582    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
583    if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
584      /*
585       * We'll get another interrupt when
586       * the transmitter holding reg. becomes
587       * free again and we are clear to send
588       */
589      break;
590    }
591
592#if 0
593    if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) {
594      /*
595       * We can't transmit yet
596       */
597      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
598      /*
599       * The next state change of CTS will wake us up
600       */
601      break;
602    }
603#endif
604
605    rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1);
606    if (rtems_termios_dequeue_characters(
607         Console_Port_Data[minor].termios_data, 1)) {
608      if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
609        z85c30_negate_RTS(minor);
610      }
611      Console_Port_Data[minor].bActive = FALSE;
612      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
613      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
614      break;
615    }
616
617  }
618
619  if (ucIntPend & SCC_RR3_B_EXT_IP) {
620    /*
621     * Clear the external status interrupt
622     */
623    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
624    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
625  }
626
627  /*
628   * Reset interrupts
629   */
630  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS);
631}
632
633/*
634 *  z85c30_isr
635 *
636 *  This is the ISR handler for each Z8530.
637 */
638
639Z85C30_STATIC rtems_isr z85c30_isr(
640  rtems_vector_number vector
641)
642{
643  int                 minor;
644  uint32_t            ulCtrlPort;
645  volatile uint8_t    ucIntPend;
646  volatile uint8_t    ucIntPendPort;
647  getRegister_f       getReg;
648
649  for (minor=0;minor<Console_Port_Count;minor++) {
650    if(Console_Port_Tbl[minor].ulIntVector == vector &&
651       Console_Port_Tbl[minor].deviceType == SERIAL_Z85C30 ) {
652      ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2;
653      getReg     = Console_Port_Tbl[minor].getRegister;
654      do {
655        ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3);
656
657          /*
658           * If this is channel A select channel A status
659           */
660
661          if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) {
662            ucIntPendPort = ucIntPend >> 3;
663            ucIntPendPort &= 7;
664          } else {
665            ucIntPendPort = ucIntPend &= 7;
666          }
667
668          if (ucIntPendPort) {
669            z85c30_process(minor, ucIntPendPort);
670          }
671      } while (ucIntPendPort);
672    }
673  }
674}
675
676/*
677 *  z85c30_enable_interrupts
678 *
679 *  This routine enables the specified interrupts for this minor.
680 */
681
682Z85C30_STATIC void z85c30_enable_interrupts(
683  int minor,
684  int interrupt_mask
685)
686{
687  uint32_t       ulCtrlPort;
688  setRegister_f  setReg;
689
690  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
691  setReg     = Console_Port_Tbl[minor].setRegister;
692
693  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask);
694}
695
696/*
697 *  z85c30_initialize_interrupts
698 *
699 *  This routine initializes the port to use interrupts.
700 */
701
702Z85C30_STATIC void z85c30_initialize_interrupts(
703  int minor
704)
705{
706  uint32_t       ulCtrlPort1;
707  uint32_t       ulCtrlPort2;
708  setRegister_f  setReg;
709
710  ulCtrlPort1 = Console_Port_Tbl[minor].ulCtrlPort1;
711  ulCtrlPort2 = Console_Port_Tbl[minor].ulCtrlPort2;
712  setReg      = Console_Port_Tbl[minor].setRegister;
713
714
715  z85c30_init(minor);
716
717  Console_Port_Data[minor].bActive=FALSE;
718
719  z85c30_initialize_port( minor );
720
721  if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
722    z85c30_negate_RTS(minor);
723  }
724
725  set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1);
726
727  z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
728
729  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0);              /* XXX vector */
730  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE);
731
732  /*
733   * Reset interrupts
734   */
735
736  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
737}
738
739/*
740 *  z85c30_write_support_int
741 *
742 *  Console Termios output entry point.
743 *
744 */
745
746Z85C30_STATIC int z85c30_write_support_int(
747  int   minor,
748  const char *buf,
749  int   len)
750{
751  uint32_t       Irql;
752  uint32_t       ulCtrlPort;
753  setRegister_f  setReg;
754
755  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
756  setReg     = Console_Port_Tbl[minor].setRegister;
757
758  /*
759   *  We are using interrupt driven output and termios only sends us
760   *  one character at a time.
761   */
762
763  if ( !len )
764    return 0;
765
766  /*
767   *  Put the character out and enable interrupts if necessary.
768   */
769
770  if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
771    z85c30_assert_RTS(minor);
772  }
773  rtems_interrupt_disable(Irql);
774    if ( Console_Port_Data[minor].bActive == FALSE) {
775      Console_Port_Data[minor].bActive = TRUE;
776      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR);
777    }
778    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf);
779  rtems_interrupt_enable(Irql);
780
781  return 1;
782}
783
784/*
785 *  z85c30_inbyte_nonblocking_polled
786 *
787 *  This routine polls for a character.
788 */
789
790Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
791  int  minor
792)
793{
794  volatile uint8_t    z85c30_status;
795  uint32_t            ulCtrlPort;
796  getRegister_f       getReg;
797
798  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
799  getReg     = Console_Port_Tbl[minor].getRegister;
800
801  /*
802   * return -1 if a character is not available.
803   */
804  z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
805  if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
806    return -1;
807  }
808
809  /*
810   * Return the character read.
811   */
812
813  return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
814}
815
816/*
817 *  z85c30_write_support_polled
818 *
819 *  Console Termios output entry point.
820 *
821 */
822
823Z85C30_STATIC int z85c30_write_support_polled(
824  int   minor,
825  const char *buf,
826  int   len)
827{
828  int nwrite=0;
829
830  /*
831   * poll each byte in the string out of the port.
832   */
833  while (nwrite < len) {
834    z85c30_write_polled(minor, *buf++);
835    nwrite++;
836  }
837
838  /*
839   * return the number of bytes written.
840   */
841  return nwrite;
842}
843
844/*
845 *  z85c30_write_polled
846 *
847 *  This routine transmits a character using polling.
848 */
849
850Z85C30_STATIC void z85c30_write_polled(
851  int   minor,
852  char  cChar
853)
854{
855  volatile uint8_t   z85c30_status;
856  uint32_t           ulCtrlPort;
857  getRegister_f      getReg;
858  setRegister_f      setReg;
859
860  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
861  getReg     = Console_Port_Tbl[minor].getRegister;
862  setReg     = Console_Port_Tbl[minor].setRegister;
863
864  /*
865   * Wait for the Transmit buffer to indicate that it is empty.
866   */
867
868  z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 );
869
870  while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
871    /*
872     * Yield while we wait
873     */
874#if 0
875    if (_System_state_Is_up(_System_state_Get())) {
876      rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
877    }
878#endif
879    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
880  }
881
882  /*
883   * Write the character.
884   */
885
886  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar );
887}
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