1 | /* |
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2 | * This file contains the console driver chip level routines for the |
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3 | * Zilog z85c30 chip. |
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4 | * |
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5 | * The Zilog Z8530 is also available as: |
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6 | * |
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7 | * + Intel 82530 |
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8 | * + AMD ??? |
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9 | * |
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10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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11 | * |
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12 | * |
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13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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17 | * |
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18 | * You are hereby granted permission to use, copy, modify, and distribute |
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19 | * this file, provided that this notice, plus the above copyright notice |
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20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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21 | * no support for this code. |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * Copyright assigned to U.S. Government, 1994. |
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26 | * |
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27 | * The license and distribution terms for this file may be |
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28 | * found in the file LICENSE in this distribution or at |
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29 | * http://www.OARcorp.com/rtems/license.html. |
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30 | * |
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31 | * $Id$ |
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32 | */ |
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33 | |
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34 | #include <rtems.h> |
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35 | #include <rtems/libio.h> |
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36 | #include <stdlib.h> |
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37 | |
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38 | #include <libchip/serial.h> |
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39 | #include "z85c30_p.h" |
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40 | |
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41 | /* |
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42 | * Flow control is only supported when using interrupts |
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43 | */ |
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44 | |
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45 | console_flow z85c30_flow_RTSCTS = |
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46 | { |
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47 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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48 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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49 | }; |
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50 | |
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51 | console_flow z85c30_flow_DTRCTS = |
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52 | { |
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53 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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54 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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55 | }; |
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56 | |
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57 | /* |
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58 | * Exported driver function table |
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59 | */ |
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60 | |
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61 | console_fns z85c30_fns = |
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62 | { |
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63 | z85c30_probe, /* deviceProbe */ |
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64 | z85c30_open, /* deviceFirstOpen */ |
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65 | z85c30_flush, /* deviceLastClose */ |
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66 | NULL, /* deviceRead */ |
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67 | z85c30_write_support_int, /* deviceWrite */ |
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68 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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69 | z85c30_write_polled, /* deviceWritePolled */ |
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70 | FALSE, /* deviceOutputUsesInterrupts */ |
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71 | }; |
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72 | |
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73 | console_fns z85c30_fns_polled = |
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74 | { |
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75 | z85c30_probe, /* deviceProbe */ |
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76 | z85c30_open, /* deviceFirstOpen */ |
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77 | z85c30_close, /* deviceLastClose */ |
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78 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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79 | z85c30_write_support_polled, /* deviceWrite */ |
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80 | z85c30_init, /* deviceInitialize */ |
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81 | z85c30_write_polled, /* deviceWritePolled */ |
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82 | FALSE, /* deviceOutputUsesInterrupts */ |
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83 | }; |
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84 | |
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85 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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86 | |
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87 | |
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88 | |
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89 | /* |
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90 | * z85c30_initialize_port |
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91 | * |
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92 | * initialize a z85c30 Port |
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93 | */ |
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94 | |
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95 | static void z85c30_initialize_port( |
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96 | int minor |
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97 | ) |
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98 | { |
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99 | unsigned32 ulCtrlPort; |
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100 | unsigned32 ulBaudDivisor; |
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101 | setRegister_f setReg; |
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102 | |
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103 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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104 | setReg = Console_Port_Tbl[minor].setRegister; |
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105 | |
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106 | /* |
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107 | * Using register 4 |
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108 | * Set up the clock rate is 16 times the data |
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109 | * rate, 8 bit sync char, 1 stop bit, no parity |
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110 | */ |
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111 | |
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112 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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113 | |
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114 | /* |
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115 | * Set up for 8 bits/character on receive with |
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116 | * receiver disable via register 3 |
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117 | */ |
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118 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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119 | |
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120 | /* |
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121 | * Set up for 8 bits/character on transmit |
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122 | * with transmitter disable via register 5 |
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123 | */ |
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124 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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125 | |
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126 | /* |
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127 | * Clear misc control bits |
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128 | */ |
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129 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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130 | |
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131 | /* |
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132 | * Setup the source of the receive and xmit |
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133 | * clock as BRG output and the transmit clock |
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134 | * as the output source for TRxC pin via register 11 |
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135 | */ |
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136 | (*setReg)( |
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137 | ulCtrlPort, |
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138 | SCC_WR0_SEL_WR11, |
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139 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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140 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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141 | ); |
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142 | |
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143 | ulBaudDivisor = Z85C30_Baud( |
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144 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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145 | (unsigned32) Console_Port_Tbl[minor].pDeviceParams |
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146 | ); |
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147 | |
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148 | /* |
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149 | * Setup the lower 8 bits time constants=1E. |
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150 | * If the time constans=1E, then the desire |
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151 | * baud rate will be equilvalent to 9600, via register 12. |
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152 | */ |
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153 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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154 | |
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155 | /* |
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156 | * using register 13 |
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157 | * Setup the upper 8 bits time constant |
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158 | */ |
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159 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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160 | |
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161 | /* |
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162 | * Enable the baud rate generator enable with clock from the |
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163 | * SCC's PCLK input via register 14. |
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164 | */ |
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165 | (*setReg)( |
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166 | ulCtrlPort, |
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167 | SCC_WR0_SEL_WR14, |
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168 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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169 | ); |
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170 | |
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171 | /* |
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172 | * We are only interested in CTS state changes |
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173 | */ |
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174 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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175 | |
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176 | /* |
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177 | * Reset errors |
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178 | */ |
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179 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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180 | |
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181 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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182 | |
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183 | /* |
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184 | * Enable the receiver via register 3 |
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185 | */ |
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186 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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187 | |
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188 | /* |
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189 | * Enable the transmitter pins set via register 5. |
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190 | */ |
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191 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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192 | |
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193 | /* |
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194 | * Disable interrupts |
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195 | */ |
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196 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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197 | |
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198 | /* |
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199 | * Reset TX CRC |
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200 | */ |
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201 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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202 | |
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203 | /* |
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204 | * Reset interrupts |
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205 | */ |
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206 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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207 | } |
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208 | |
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209 | static int z85c30_open( |
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210 | int major, |
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211 | int minor, |
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212 | void *arg |
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213 | ) |
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214 | { |
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215 | /* |
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216 | * Assert DTR |
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217 | */ |
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218 | |
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219 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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220 | z85c30_assert_DTR(minor); |
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221 | } |
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222 | |
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223 | return(RTEMS_SUCCESSFUL); |
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224 | } |
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225 | |
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226 | static int z85c30_close( |
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227 | int major, |
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228 | int minor, |
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229 | void *arg |
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230 | ) |
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231 | { |
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232 | /* |
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233 | * Negate DTR |
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234 | */ |
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235 | |
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236 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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237 | z85c30_negate_DTR(minor); |
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238 | } |
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239 | |
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240 | return(RTEMS_SUCCESSFUL); |
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241 | } |
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242 | |
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243 | /* |
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244 | * z85c30_write_polled |
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245 | * |
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246 | * This routine transmits a character using polling. |
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247 | */ |
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248 | |
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249 | static void z85c30_write_polled( |
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250 | int minor, |
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251 | char cChar |
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252 | ) |
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253 | { |
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254 | volatile unsigned8 z85c30_status; |
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255 | unsigned32 ulCtrlPort; |
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256 | getRegister_f getReg; |
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257 | setData_f setData; |
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258 | |
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259 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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260 | getReg = Console_Port_Tbl[minor].getRegister; |
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261 | setData = Console_Port_Tbl[minor].setData; |
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262 | |
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263 | /* |
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264 | * Wait for the Transmit buffer to indicate that it is empty. |
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265 | */ |
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266 | |
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267 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
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268 | |
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269 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
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270 | /* |
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271 | * Yield while we wait |
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272 | */ |
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273 | if (_System_state_Is_up(_System_state_Get())) { |
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274 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
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275 | } |
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276 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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277 | } |
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278 | |
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279 | /* |
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280 | * Write the character. |
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281 | */ |
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282 | |
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283 | (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); |
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284 | } |
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285 | |
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286 | /* |
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287 | * Console Device Driver Entry Points |
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288 | */ |
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289 | |
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290 | static boolean z85c30_probe(int minor) |
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291 | { |
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292 | /* |
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293 | * If the configuration dependent probe has located the device then |
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294 | * assume it is there |
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295 | */ |
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296 | |
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297 | return(TRUE); |
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298 | } |
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299 | |
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300 | static void z85c30_init(int minor) |
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301 | { |
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302 | unsigned32 ulCtrlPort; |
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303 | unsigned8 dummy; |
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304 | z85c30_context *pz85c30Context; |
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305 | setRegister_f setReg; |
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306 | getRegister_f getReg; |
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307 | |
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308 | setReg = Console_Port_Tbl[minor].setRegister; |
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309 | getReg = Console_Port_Tbl[minor].getRegister; |
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310 | |
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311 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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312 | |
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313 | Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; |
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314 | |
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315 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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316 | |
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317 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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318 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { |
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319 | /* |
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320 | * This is channel A |
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321 | */ |
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322 | /* |
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323 | * Ensure port state machine is reset |
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324 | */ |
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325 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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326 | |
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327 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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328 | |
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329 | } else { |
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330 | /* |
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331 | * This is channel B |
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332 | */ |
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333 | /* |
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334 | * Ensure port state machine is reset |
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335 | */ |
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336 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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337 | |
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338 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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339 | } |
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340 | |
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341 | z85c30_initialize_port(minor); |
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342 | } |
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343 | |
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344 | /* |
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345 | * These routines provide control of the RTS and DTR lines |
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346 | */ |
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347 | |
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348 | /* |
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349 | * z85c30_assert_RTS |
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350 | */ |
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351 | |
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352 | static int z85c30_assert_RTS(int minor) |
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353 | { |
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354 | rtems_interrupt_level Irql; |
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355 | z85c30_context *pz85c30Context; |
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356 | setRegister_f setReg; |
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357 | |
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358 | setReg = Console_Port_Tbl[minor].setRegister; |
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359 | |
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360 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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361 | |
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362 | /* |
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363 | * Assert RTS |
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364 | */ |
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365 | |
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366 | rtems_interrupt_disable(Irql); |
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367 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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368 | (*setReg)( |
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369 | Console_Port_Tbl[minor].ulCtrlPort1, |
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370 | SCC_WR0_SEL_WR5, |
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371 | pz85c30Context->ucModemCtrl |
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372 | ); |
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373 | rtems_interrupt_enable(Irql); |
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374 | return 0; |
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375 | } |
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376 | |
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377 | /* |
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378 | * z85c30_negate_RTS |
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379 | */ |
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380 | |
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381 | static int z85c30_negate_RTS(int minor) |
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382 | { |
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383 | rtems_interrupt_level Irql; |
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384 | z85c30_context *pz85c30Context; |
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385 | setRegister_f setReg; |
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386 | |
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387 | setReg = Console_Port_Tbl[minor].setRegister; |
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388 | |
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389 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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390 | |
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391 | /* |
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392 | * Negate RTS |
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393 | */ |
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394 | |
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395 | rtems_interrupt_disable(Irql); |
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396 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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397 | (*setReg)( |
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398 | Console_Port_Tbl[minor].ulCtrlPort1, |
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399 | SCC_WR0_SEL_WR5, |
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400 | pz85c30Context->ucModemCtrl |
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401 | ); |
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402 | rtems_interrupt_enable(Irql); |
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403 | return 0; |
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404 | } |
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405 | |
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406 | /* |
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407 | * These flow control routines utilise a connection from the local DTR |
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408 | * line to the remote CTS line |
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409 | */ |
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410 | |
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411 | /* |
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412 | * z85c30_assert_DTR |
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413 | */ |
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414 | |
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415 | static int z85c30_assert_DTR(int minor) |
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416 | { |
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417 | rtems_interrupt_level Irql; |
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418 | z85c30_context *pz85c30Context; |
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419 | setRegister_f setReg; |
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420 | |
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421 | setReg = Console_Port_Tbl[minor].setRegister; |
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422 | |
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423 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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424 | |
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425 | /* |
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426 | * Assert DTR |
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427 | */ |
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428 | |
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429 | rtems_interrupt_disable(Irql); |
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430 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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431 | (*setReg)( |
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432 | Console_Port_Tbl[minor].ulCtrlPort1, |
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433 | SCC_WR0_SEL_WR5, |
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434 | pz85c30Context->ucModemCtrl |
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435 | ); |
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436 | rtems_interrupt_enable(Irql); |
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437 | return 0; |
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438 | } |
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439 | |
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440 | /* |
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441 | * z85c30_negate_DTR |
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442 | */ |
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443 | |
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444 | static int z85c30_negate_DTR(int minor) |
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445 | { |
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446 | rtems_interrupt_level Irql; |
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447 | z85c30_context *pz85c30Context; |
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448 | setRegister_f setReg; |
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449 | |
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450 | setReg = Console_Port_Tbl[minor].setRegister; |
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451 | |
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452 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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453 | |
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454 | /* |
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455 | * Negate DTR |
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456 | */ |
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457 | |
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458 | rtems_interrupt_disable(Irql); |
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459 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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460 | (*setReg)( |
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461 | Console_Port_Tbl[minor].ulCtrlPort1, |
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462 | SCC_WR0_SEL_WR5, |
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463 | pz85c30Context->ucModemCtrl |
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464 | ); |
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465 | rtems_interrupt_enable(Irql); |
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466 | return 0; |
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467 | } |
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468 | |
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469 | /* |
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470 | * z85c30_isr |
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471 | * |
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472 | * This routine is the console interrupt handler for COM3 and COM4 |
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473 | * |
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474 | * Input parameters: |
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475 | * vector - vector number |
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476 | * |
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477 | * Output parameters: NONE |
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478 | * |
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479 | * Return values: NONE |
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480 | */ |
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481 | |
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482 | static void z85c30_process( |
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483 | int minor, |
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484 | unsigned8 ucIntPend |
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485 | ) |
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486 | { |
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487 | unsigned32 ulCtrlPort; |
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488 | unsigned32 ulDataPort; |
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489 | volatile unsigned8 z85c30_status; |
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490 | char cChar; |
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491 | setRegister_f setReg; |
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492 | getRegister_f getReg; |
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493 | getData_f getData; |
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494 | setData_f setData; |
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495 | |
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496 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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497 | ulDataPort = Console_Port_Tbl[minor].ulDataPort; |
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498 | setReg = Console_Port_Tbl[minor].setRegister; |
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499 | getReg = Console_Port_Tbl[minor].getRegister; |
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500 | getData = Console_Port_Tbl[minor].getData; |
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501 | setData = Console_Port_Tbl[minor].setData; |
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502 | |
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503 | /* |
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504 | * Deal with any received characters |
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505 | */ |
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506 | while (ucIntPend&SCC_RR3_B_RX_IP) |
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507 | { |
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508 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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509 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
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510 | break; |
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511 | } |
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512 | |
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513 | /* |
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514 | * Return the character read. |
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515 | */ |
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516 | |
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517 | cChar = (*getData)(ulDataPort); |
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518 | |
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519 | rtems_termios_enqueue_raw_characters( |
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520 | Console_Port_Data[minor].termios_data, |
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521 | &cChar, |
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522 | 1 |
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523 | ); |
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524 | } |
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525 | |
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526 | while (TRUE) |
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527 | { |
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528 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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529 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
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530 | /* |
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531 | * We'll get another interrupt when |
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532 | * the transmitter holding reg. becomes |
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533 | * free again and we are clear to send |
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534 | */ |
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535 | break; |
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536 | } |
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537 | |
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538 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
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539 | /* |
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540 | * We can't transmit yet |
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541 | */ |
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542 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
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543 | /* |
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544 | * The next state change of CTS will wake us up |
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545 | */ |
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546 | break; |
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547 | } |
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548 | |
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549 | if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
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550 | Console_Port_Data[minor].bActive=FALSE; |
---|
551 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
552 | z85c30_negate_RTS(minor); |
---|
553 | } |
---|
554 | /* |
---|
555 | * There is no data to transmit |
---|
556 | */ |
---|
557 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
558 | break; |
---|
559 | } |
---|
560 | |
---|
561 | Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); |
---|
562 | |
---|
563 | /* |
---|
564 | * transmit character |
---|
565 | */ |
---|
566 | (*setData)(ulDataPort, cChar); |
---|
567 | |
---|
568 | /* |
---|
569 | * Interrupt once FIFO has room |
---|
570 | */ |
---|
571 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
572 | break; |
---|
573 | } |
---|
574 | |
---|
575 | if (ucIntPend&SCC_RR3_B_EXT_IP) { |
---|
576 | /* |
---|
577 | * Clear the external status interrupt |
---|
578 | */ |
---|
579 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
580 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
581 | } |
---|
582 | |
---|
583 | /* |
---|
584 | * Reset interrupts |
---|
585 | */ |
---|
586 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
587 | } |
---|
588 | |
---|
589 | static rtems_isr z85c30_isr( |
---|
590 | rtems_vector_number vector |
---|
591 | ) |
---|
592 | { |
---|
593 | int minor; |
---|
594 | unsigned32 ulCtrlPort; |
---|
595 | volatile unsigned8 ucIntPend; |
---|
596 | volatile unsigned8 ucIntPendPort; |
---|
597 | getRegister_f getReg; |
---|
598 | |
---|
599 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
600 | if (vector==Console_Port_Tbl[minor].ulIntVector) { |
---|
601 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
602 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
603 | do { |
---|
604 | ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
605 | |
---|
606 | /* |
---|
607 | * If this is channel A select channel A status |
---|
608 | */ |
---|
609 | |
---|
610 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
611 | ucIntPendPort = ucIntPend>>3; |
---|
612 | ucIntPendPort = ucIntPendPort&=7; |
---|
613 | } else { |
---|
614 | ucIntPendPort = ucIntPend &= 7; |
---|
615 | } |
---|
616 | |
---|
617 | if (ucIntPendPort) { |
---|
618 | z85c30_process(minor, ucIntPendPort); |
---|
619 | } |
---|
620 | } while (ucIntPendPort); |
---|
621 | } |
---|
622 | } |
---|
623 | } |
---|
624 | |
---|
625 | /* |
---|
626 | * z85c30_flush |
---|
627 | */ |
---|
628 | |
---|
629 | static int z85c30_flush( |
---|
630 | int major, |
---|
631 | int minor, |
---|
632 | void *arg |
---|
633 | ) |
---|
634 | { |
---|
635 | while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
636 | /* |
---|
637 | * Yield while we wait |
---|
638 | */ |
---|
639 | if (_System_state_Is_up(_System_state_Get())) { |
---|
640 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
641 | } |
---|
642 | } |
---|
643 | |
---|
644 | z85c30_close(major, minor, arg); |
---|
645 | |
---|
646 | return(RTEMS_SUCCESSFUL); |
---|
647 | } |
---|
648 | |
---|
649 | /* |
---|
650 | * z85c30_initialize_interrupts |
---|
651 | * |
---|
652 | * This routine initializes the console's receive and transmit |
---|
653 | * ring buffers and loads the appropriate vectors to handle the interrupts. |
---|
654 | * |
---|
655 | * Input parameters: NONE |
---|
656 | * |
---|
657 | * Output parameters: NONE |
---|
658 | * |
---|
659 | * Return values: NONE |
---|
660 | */ |
---|
661 | |
---|
662 | static void z85c30_enable_interrupts( |
---|
663 | int minor |
---|
664 | ) |
---|
665 | { |
---|
666 | unsigned32 ulCtrlPort; |
---|
667 | setRegister_f setReg; |
---|
668 | |
---|
669 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
670 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
671 | |
---|
672 | /* |
---|
673 | * Enable interrupts |
---|
674 | */ |
---|
675 | (*setReg)( |
---|
676 | ulCtrlPort, |
---|
677 | SCC_WR0_SEL_WR1, |
---|
678 | SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX |
---|
679 | ); |
---|
680 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); |
---|
681 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
682 | |
---|
683 | /* |
---|
684 | * Reset interrupts |
---|
685 | */ |
---|
686 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
687 | } |
---|
688 | |
---|
689 | static void z85c30_initialize_interrupts( |
---|
690 | int minor |
---|
691 | ) |
---|
692 | { |
---|
693 | z85c30_init(minor); |
---|
694 | |
---|
695 | Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); |
---|
696 | |
---|
697 | Console_Port_Data[minor].bActive=FALSE; |
---|
698 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
699 | z85c30_negate_RTS(minor); |
---|
700 | } |
---|
701 | |
---|
702 | if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { |
---|
703 | /* |
---|
704 | * Only do this for Channel A |
---|
705 | */ |
---|
706 | |
---|
707 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
708 | } |
---|
709 | |
---|
710 | z85c30_enable_interrupts(minor); |
---|
711 | } |
---|
712 | |
---|
713 | /* |
---|
714 | * z85c30_write_support_int |
---|
715 | * |
---|
716 | * Console Termios output entry point. |
---|
717 | * |
---|
718 | */ |
---|
719 | |
---|
720 | static int z85c30_write_support_int( |
---|
721 | int minor, |
---|
722 | const char *buf, |
---|
723 | int len) |
---|
724 | { |
---|
725 | int i; |
---|
726 | unsigned32 Irql; |
---|
727 | |
---|
728 | for (i=0; i<len;) { |
---|
729 | if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { |
---|
730 | if (!Console_Port_Data[minor].bActive) { |
---|
731 | /* |
---|
732 | * Wake up the device |
---|
733 | */ |
---|
734 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
735 | z85c30_assert_RTS(minor); |
---|
736 | } |
---|
737 | rtems_interrupt_disable(Irql); |
---|
738 | Console_Port_Data[minor].bActive=TRUE; |
---|
739 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
740 | rtems_interrupt_enable(Irql); |
---|
741 | } else { |
---|
742 | /* |
---|
743 | * Yield while we await an interrupt |
---|
744 | */ |
---|
745 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
746 | } |
---|
747 | |
---|
748 | /* |
---|
749 | * Wait for ring buffer to empty |
---|
750 | */ |
---|
751 | continue; |
---|
752 | } else { |
---|
753 | Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); |
---|
754 | i++; |
---|
755 | } |
---|
756 | } |
---|
757 | |
---|
758 | /* |
---|
759 | * Ensure that characters are on the way |
---|
760 | */ |
---|
761 | if (!Console_Port_Data[minor].bActive) { |
---|
762 | /* |
---|
763 | * Wake up the device |
---|
764 | */ |
---|
765 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
766 | z85c30_assert_RTS(minor); |
---|
767 | } |
---|
768 | rtems_interrupt_disable(Irql); |
---|
769 | Console_Port_Data[minor].bActive=TRUE; |
---|
770 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
771 | rtems_interrupt_enable(Irql); |
---|
772 | } |
---|
773 | |
---|
774 | return (len); |
---|
775 | } |
---|
776 | |
---|
777 | /* |
---|
778 | * z85c30_inbyte_nonblocking_polled |
---|
779 | * |
---|
780 | * This routine polls for a character. |
---|
781 | */ |
---|
782 | |
---|
783 | static int z85c30_inbyte_nonblocking_polled( |
---|
784 | int minor |
---|
785 | ) |
---|
786 | { |
---|
787 | volatile unsigned8 z85c30_status; |
---|
788 | unsigned32 ulCtrlPort; |
---|
789 | getRegister_f getReg; |
---|
790 | getData_f getData; |
---|
791 | |
---|
792 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
793 | getData = Console_Port_Tbl[minor].getData; |
---|
794 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
795 | |
---|
796 | /* |
---|
797 | * return -1 if a character is not available. |
---|
798 | */ |
---|
799 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
800 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
801 | return -1; |
---|
802 | } |
---|
803 | |
---|
804 | /* |
---|
805 | * Return the character read. |
---|
806 | */ |
---|
807 | return (*getData)(Console_Port_Tbl[minor].ulDataPort); |
---|
808 | } |
---|
809 | |
---|
810 | /* |
---|
811 | * z85c30_write_support_polled |
---|
812 | * |
---|
813 | * Console Termios output entry point. |
---|
814 | * |
---|
815 | */ |
---|
816 | |
---|
817 | static int z85c30_write_support_polled( |
---|
818 | int minor, |
---|
819 | const char *buf, |
---|
820 | int len) |
---|
821 | { |
---|
822 | int nwrite=0; |
---|
823 | |
---|
824 | /* |
---|
825 | * poll each byte in the string out of the port. |
---|
826 | */ |
---|
827 | while (nwrite < len) { |
---|
828 | z85c30_write_polled(minor, *buf++); |
---|
829 | nwrite++; |
---|
830 | } |
---|
831 | |
---|
832 | /* |
---|
833 | * return the number of bytes written. |
---|
834 | */ |
---|
835 | return nwrite; |
---|
836 | } |
---|