source: rtems/c/src/libchip/serial/z85c30.c @ 02958c5e

4.115
Last change on this file since 02958c5e was 02958c5e, checked in by Josh Oguin <josh.oguin@…>, on Nov 19, 2014 at 8:28:08 PM

libchip/serial/ns16550* and z8530*: Assert on baud number to avoid divide by 0

This was flagged by CodeSonar?. It should be impossible to get an
incorrect baud number back but ensure this in debug mode. The _Assert()
keeps their scanner from evaluating for divide by 0 past this point.

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File size: 20.3 KB
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1/*
2 *  This file contains the console driver chip level routines for the
3 *  Zilog z85c30 chip.
4 *
5 *  The Zilog Z8530 is also available as:
6 *
7 *    + Intel 82530
8 *    + AMD ???
9 *
10 *  COPYRIGHT (c) 1998 by Radstone Technology
11 *
12 *
13 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
14 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
16 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
17 *
18 * You are hereby granted permission to use, copy, modify, and distribute
19 * this file, provided that this notice, plus the above copyright notice
20 * and disclaimer, appears in all copies. Radstone Technology will provide
21 * no support for this code.
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.org/license/LICENSE.
29 */
30
31#include <rtems.h>
32#include <rtems/libio.h>
33#include <rtems/score/sysstate.h>
34#include <stdlib.h>
35
36#include <libchip/serial.h>
37#include <libchip/sersupp.h>
38#include "z85c30_p.h"
39
40/*
41 * Flow control is only supported when using interrupts
42 */
43
44const console_flow z85c30_flow_RTSCTS = {
45  z85c30_negate_RTS,    /* deviceStopRemoteTx */
46  z85c30_assert_RTS     /* deviceStartRemoteTx */
47};
48
49const console_flow z85c30_flow_DTRCTS = {
50  z85c30_negate_DTR,    /* deviceStopRemoteTx */
51  z85c30_assert_DTR     /* deviceStartRemoteTx */
52};
53
54/*
55 * Exported driver function table
56 */
57
58const console_fns z85c30_fns = {
59  libchip_serial_default_probe,  /* deviceProbe */
60  z85c30_open,                   /* deviceFirstOpen */
61  NULL,                          /* deviceLastClose */
62  NULL,                          /* deviceRead */
63  z85c30_write_support_int,      /* deviceWrite */
64  z85c30_initialize_interrupts,  /* deviceInitialize */
65  z85c30_write_polled,           /* deviceWritePolled */
66  NULL,                          /* deviceSetAttributes */
67  true                           /* deviceOutputUsesInterrupts */
68};
69
70const console_fns z85c30_fns_polled = {
71  libchip_serial_default_probe,      /* deviceProbe */
72  z85c30_open,                       /* deviceFirstOpen */
73  z85c30_close,                      /* deviceLastClose */
74  z85c30_inbyte_nonblocking_polled,  /* deviceRead */
75  z85c30_write_support_polled,       /* deviceWrite */
76  z85c30_init,                       /* deviceInitialize */
77  z85c30_write_polled,               /* deviceWritePolled */
78  NULL,                              /* deviceSetAttributes */
79  false                              /* deviceOutputUsesInterrupts */
80};
81
82#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
83  extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
84#endif
85
86/*
87 *  z85c30_initialize_port
88 *
89 *  initialize a z85c30 Port
90 */
91
92Z85C30_STATIC void z85c30_initialize_port(
93  int minor
94)
95{
96  uintptr_t       ulCtrlPort;
97  uintptr_t       ulBaudDivisor;
98  setRegister_f   setReg;
99
100  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
101  setReg   = Console_Port_Tbl[minor]->setRegister;
102
103  /*
104   * Using register 4
105   * Set up the clock rate is 16 times the data
106   * rate, 8 bit sync char, 1 stop bit, no parity
107   */
108
109  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK );
110
111  /*
112   * Set up for 8 bits/character on receive with
113   * receiver disable via register 3
114   */
115  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS );
116
117  /*
118   * Set up for 8 bits/character on transmit
119   * with transmitter disable via register 5
120   */
121  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS );
122
123  /*
124   * Clear misc control bits
125   */
126  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 );
127
128  /*
129   * Setup the source of the receive and xmit
130   * clock as BRG output and the transmit clock
131   * as the output source for TRxC pin via register 11
132   */
133  (*setReg)(
134    ulCtrlPort,
135    SCC_WR0_SEL_WR11,
136    SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI |
137      SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN
138  );
139
140  ulBaudDivisor = Z85C30_Baud(
141    (uint32_t) Console_Port_Tbl[minor]->ulClock,
142    (uint32_t) ((uintptr_t)Console_Port_Tbl[minor]->pDeviceParams)
143  );
144
145  /*
146   * Setup the lower 8 bits time constants=1E.
147   * If the time constans=1E, then the desire
148   * baud rate will be equilvalent to 9600, via register 12.
149   */
150  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
151
152  /*
153   * using register 13
154   * Setup the upper 8 bits time constant
155   */
156  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
157
158  /*
159   * Enable the baud rate generator enable with clock from the
160   * SCC's PCLK input via register 14.
161   */
162  (*setReg)(
163    ulCtrlPort,
164    SCC_WR0_SEL_WR14,
165    SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL
166  );
167
168  /*
169   * We are only interested in CTS state changes
170   */
171  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE );
172
173  /*
174   * Reset errors
175   */
176  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
177
178  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST );
179
180  /*
181   * Enable the receiver via register 3
182   */
183  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN );
184
185  /*
186   * Enable the transmitter pins set via register 5.
187   */
188  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN );
189
190  /*
191   * Disable interrupts
192   */
193  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 );
194
195  /*
196   * Reset TX CRC
197   */
198  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC );
199
200  /*
201   * Reset interrupts
202   */
203  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
204}
205
206/*
207 *  z85c30_open
208 */
209
210Z85C30_STATIC int z85c30_open(
211  int   major,
212  int   minor,
213  void *arg
214)
215{
216
217  z85c30_initialize_port(minor);
218
219  /*
220   * Assert DTR
221   */
222
223  if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) {
224    z85c30_assert_DTR(minor);
225  }
226
227  return(RTEMS_SUCCESSFUL);
228}
229
230/*
231 *  z85c30_close
232 */
233
234Z85C30_STATIC int z85c30_close(
235  int   major,
236  int   minor,
237  void *arg
238)
239{
240  /*
241   * Negate DTR
242   */
243
244  if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) {
245    z85c30_negate_DTR(minor);
246  }
247
248  return(RTEMS_SUCCESSFUL);
249}
250
251/*
252 *  z85c30_init
253 */
254
255Z85C30_STATIC void z85c30_init(int minor)
256{
257  uintptr_t        ulCtrlPort;
258  z85c30_context  *pz85c30Context;
259  setRegister_f    setReg;
260  getRegister_f    getReg;
261
262  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
263  setReg     = Console_Port_Tbl[minor]->setRegister;
264  getReg     = Console_Port_Tbl[minor]->getRegister;
265
266  pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context));
267
268  Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context;
269
270  pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN;
271
272  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
273  if ( ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort2 ) {
274    /*
275     * This is channel A
276     */
277    /*
278     * Ensure port state machine is reset
279     */
280    (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
281
282    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST);
283
284  } else {
285    /*
286     * This is channel B
287     */
288    /*
289     * Ensure port state machine is reset
290     */
291    (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
292
293    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST);
294  }
295}
296
297/*
298 * These routines provide control of the RTS and DTR lines
299 */
300
301/*
302 *  z85c30_assert_RTS
303 */
304
305Z85C30_STATIC int z85c30_assert_RTS(int minor)
306{
307  rtems_interrupt_level  Irql;
308  z85c30_context        *pz85c30Context;
309  setRegister_f          setReg;
310
311  setReg = Console_Port_Tbl[minor]->setRegister;
312
313  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
314
315  /*
316   * Assert RTS
317   */
318
319  rtems_interrupt_disable(Irql);
320    pz85c30Context->ucModemCtrl|=SCC_WR5_RTS;
321    (*setReg)(
322      Console_Port_Tbl[minor]->ulCtrlPort1,
323      SCC_WR0_SEL_WR5,
324      pz85c30Context->ucModemCtrl
325    );
326  rtems_interrupt_enable(Irql);
327  return 0;
328}
329
330/*
331 *  z85c30_negate_RTS
332 */
333
334Z85C30_STATIC int z85c30_negate_RTS(int minor)
335{
336  rtems_interrupt_level  Irql;
337  z85c30_context        *pz85c30Context;
338  setRegister_f          setReg;
339
340  setReg = Console_Port_Tbl[minor]->setRegister;
341
342  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
343
344  /*
345   * Negate RTS
346   */
347
348  rtems_interrupt_disable(Irql);
349    pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS;
350    (*setReg)(
351      Console_Port_Tbl[minor]->ulCtrlPort1,
352      SCC_WR0_SEL_WR5,
353      pz85c30Context->ucModemCtrl
354    );
355  rtems_interrupt_enable(Irql);
356  return 0;
357}
358
359/*
360 * These flow control routines utilise a connection from the local DTR
361 * line to the remote CTS line
362 */
363
364/*
365 *  z85c30_assert_DTR
366 */
367
368Z85C30_STATIC int z85c30_assert_DTR(int minor)
369{
370  rtems_interrupt_level  Irql;
371  z85c30_context        *pz85c30Context;
372  setRegister_f          setReg;
373
374  setReg = Console_Port_Tbl[minor]->setRegister;
375
376  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
377
378  /*
379   * Assert DTR
380   */
381
382  rtems_interrupt_disable(Irql);
383    pz85c30Context->ucModemCtrl|=SCC_WR5_DTR;
384    (*setReg)(
385      Console_Port_Tbl[minor]->ulCtrlPort1,
386      SCC_WR0_SEL_WR5,
387      pz85c30Context->ucModemCtrl
388  );
389  rtems_interrupt_enable(Irql);
390  return 0;
391}
392
393/*
394 *  z85c30_negate_DTR
395 */
396
397Z85C30_STATIC int z85c30_negate_DTR(int minor)
398{
399  rtems_interrupt_level  Irql;
400  z85c30_context        *pz85c30Context;
401  setRegister_f          setReg;
402
403  setReg = Console_Port_Tbl[minor]->setRegister;
404
405  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
406
407  /*
408   * Negate DTR
409   */
410
411  rtems_interrupt_disable(Irql);
412    pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR;
413    (*setReg)(
414      Console_Port_Tbl[minor]->ulCtrlPort1,
415      SCC_WR0_SEL_WR5,
416      pz85c30Context->ucModemCtrl
417  );
418  rtems_interrupt_enable(Irql);
419  return 0;
420}
421
422/*
423 *  z85c30_set_attributes
424 *
425 *  This function sets the SCC channel to reflect the requested termios
426 *  port settings.
427 */
428
429Z85C30_STATIC int z85c30_set_attributes(
430  int                   minor,
431  const struct termios *t
432)
433{
434  uintptr_t              ulCtrlPort;
435  uint32_t               ulBaudDivisor;
436  uint32_t               wr3;
437  uint32_t               wr4;
438  uint32_t               wr5;
439  int                    baud_requested;
440  uint32_t               baud_number;
441  setRegister_f          setReg;
442  rtems_interrupt_level  Irql;
443
444  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
445  setReg     = Console_Port_Tbl[minor]->setRegister;
446
447  /*
448   *  Calculate the baud rate divisor
449   *
450   *  Assert ensures there is no division by 0.
451   */
452
453  baud_requested = t->c_cflag & CBAUD;
454  if (!baud_requested)
455    baud_requested = B9600;              /* default to 9600 baud */
456
457  baud_number = (uint32_t) rtems_termios_baud_to_number( baud_requested );
458  _Assert( baud_number != 0 );
459
460  ulBaudDivisor = Z85C30_Baud(
461    (uint32_t) Console_Port_Tbl[minor]->ulClock,
462    baud_number
463  );
464
465  wr3 = SCC_WR3_RX_EN;
466  wr4 = SCC_WR4_16_CLOCK;
467  wr5 = SCC_WR5_TX_EN;
468
469  /*
470   *  Parity
471   */
472
473  if (t->c_cflag & PARENB) {
474    wr4 |= SCC_WR4_PAR_EN;
475    if (!(t->c_cflag & PARODD))
476      wr4 |= SCC_WR4_PAR_EVEN;
477  }
478
479  /*
480   *  Character Size
481   */
482
483  if (t->c_cflag & CSIZE) {
484    switch (t->c_cflag & CSIZE) {
485      case CS5:   break;
486      case CS6:  wr3 |= SCC_WR3_RX_6_BITS;  wr5 |= SCC_WR5_TX_6_BITS;  break;
487      case CS7:  wr3 |= SCC_WR3_RX_7_BITS;  wr5 |= SCC_WR5_TX_7_BITS;  break;
488      case CS8:  wr3 |= SCC_WR3_RX_8_BITS;  wr5 |= SCC_WR5_TX_8_BITS;  break;
489    }
490  } else {
491    wr3 |= SCC_WR3_RX_8_BITS;       /* default to 9600,8,N,1 */
492    wr5 |= SCC_WR5_TX_8_BITS;       /* default to 9600,8,N,1 */
493  }
494
495  /*
496   *  Stop Bits
497   */
498
499  if (t->c_cflag & CSTOPB) {
500    wr4 |= SCC_WR4_2_STOP;                      /* 2 stop bits */
501  } else {
502    wr4 |= SCC_WR4_1_STOP;                      /* 1 stop bits */
503  }
504
505  /*
506   *  Now actually set the chip
507   */
508
509  rtems_interrupt_disable(Irql);
510    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 );
511    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 );
512    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 );
513
514    /*
515     * Setup the lower 8 bits time constants=1E.
516     * If the time constans=1E, then the desire
517     * baud rate will be equilvalent to 9600, via register 12.
518     */
519
520    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
521
522    /*
523     * using register 13
524     * Setup the upper 8 bits time constant
525     */
526
527    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
528
529  rtems_interrupt_enable(Irql);
530
531  return 0;
532}
533
534/*
535 *  z85c30_process
536 *
537 *  This is the per port ISR handler.
538 */
539
540Z85C30_STATIC void z85c30_process(
541  int        minor,
542  uint8_t    ucIntPend
543)
544{
545  uint32_t            ulCtrlPort;
546  volatile uint8_t    z85c30_status;
547  char                cChar;
548  setRegister_f       setReg;
549  getRegister_f       getReg;
550
551  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
552  setReg     = Console_Port_Tbl[minor]->setRegister;
553  getReg     = Console_Port_Tbl[minor]->getRegister;
554
555  /*
556   * Deal with any received characters
557   */
558
559  while (ucIntPend&SCC_RR3_B_RX_IP)
560  {
561    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
562    if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
563      break;
564    }
565
566    /*
567     * Return the character read.
568     */
569
570    cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
571
572    rtems_termios_enqueue_raw_characters(
573      Console_Port_Data[minor].termios_data,
574      &cChar,
575      1
576    );
577  }
578
579  /*
580   *  There could be a race condition here if there is not yet a TX
581   *  interrupt pending but the buffer is empty.  This condition has
582   *  been seen before on other z8530 drivers but has not been seen
583   *  with this one.  The typical solution is to use "vector includes
584   *  status" or to only look at the interrupts actually pending
585   *  in RR3.
586   */
587
588  while (true) {
589    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
590    if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
591      /*
592       * We'll get another interrupt when
593       * the transmitter holding reg. becomes
594       * free again and we are clear to send
595       */
596      break;
597    }
598
599#if 0
600    if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) {
601      /*
602       * We can't transmit yet
603       */
604      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
605      /*
606       * The next state change of CTS will wake us up
607       */
608      break;
609    }
610#endif
611
612    rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1);
613    if (rtems_termios_dequeue_characters(
614         Console_Port_Data[minor].termios_data, 1)) {
615      if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
616        z85c30_negate_RTS(minor);
617      }
618      Console_Port_Data[minor].bActive = FALSE;
619      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
620      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
621      break;
622    }
623
624  }
625
626  if (ucIntPend & SCC_RR3_B_EXT_IP) {
627    /*
628     * Clear the external status interrupt
629     */
630    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
631    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
632  }
633
634  /*
635   * Reset interrupts
636   */
637  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS);
638}
639
640/*
641 *  z85c30_isr
642 *
643 *  This is the ISR handler for each Z8530.
644 */
645
646Z85C30_STATIC rtems_isr z85c30_isr(
647  rtems_vector_number vector
648)
649{
650  int                 minor;
651  uint32_t            ulCtrlPort;
652  volatile uint8_t    ucIntPend;
653  volatile uint8_t    ucIntPendPort;
654  getRegister_f       getReg;
655
656  for (minor=0;minor<Console_Port_Count;minor++) {
657    if(Console_Port_Tbl[minor]->ulIntVector == vector &&
658       Console_Port_Tbl[minor]->deviceType == SERIAL_Z85C30 ) {
659      ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort2;
660      getReg     = Console_Port_Tbl[minor]->getRegister;
661      do {
662        ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3);
663
664          /*
665           * If this is channel A select channel A status
666           */
667
668          if (ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort1) {
669            ucIntPendPort = ucIntPend >> 3;
670            ucIntPendPort &= 7;
671          } else {
672            ucIntPendPort = ucIntPend &= 7;
673          }
674
675          if (ucIntPendPort) {
676            z85c30_process(minor, ucIntPendPort);
677          }
678      } while (ucIntPendPort);
679    }
680  }
681}
682
683/*
684 *  z85c30_enable_interrupts
685 *
686 *  This routine enables the specified interrupts for this minor.
687 */
688
689Z85C30_STATIC void z85c30_enable_interrupts(
690  int minor,
691  int interrupt_mask
692)
693{
694  uint32_t       ulCtrlPort;
695  setRegister_f  setReg;
696
697  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
698  setReg     = Console_Port_Tbl[minor]->setRegister;
699
700  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask);
701}
702
703/*
704 *  z85c30_initialize_interrupts
705 *
706 *  This routine initializes the port to use interrupts.
707 */
708
709Z85C30_STATIC void z85c30_initialize_interrupts(
710  int minor
711)
712{
713  uint32_t       ulCtrlPort1;
714  setRegister_f  setReg;
715
716  ulCtrlPort1 = Console_Port_Tbl[minor]->ulCtrlPort1;
717  setReg      = Console_Port_Tbl[minor]->setRegister;
718
719
720  z85c30_init(minor);
721
722  Console_Port_Data[minor].bActive=FALSE;
723
724  z85c30_initialize_port( minor );
725
726  if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
727    z85c30_negate_RTS(minor);
728  }
729
730#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
731  set_vector(z85c30_isr, Console_Port_Tbl[minor]->ulIntVector, 1);
732#endif
733
734  z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
735
736  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0);              /* XXX vector */
737  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE);
738
739  /*
740   * Reset interrupts
741   */
742
743  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
744}
745
746/*
747 *  z85c30_write_support_int
748 *
749 *  Console Termios output entry point.
750 *
751 */
752
753Z85C30_STATIC ssize_t z85c30_write_support_int(
754  int   minor,
755  const char *buf,
756  size_t len)
757{
758  uint32_t       Irql;
759  uint32_t       ulCtrlPort;
760  setRegister_f  setReg;
761
762  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
763  setReg     = Console_Port_Tbl[minor]->setRegister;
764
765  /*
766   *  We are using interrupt driven output and termios only sends us
767   *  one character at a time.
768   */
769
770  if ( !len )
771    return 0;
772
773  /*
774   *  Put the character out and enable interrupts if necessary.
775   */
776
777  if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
778    z85c30_assert_RTS(minor);
779  }
780  rtems_interrupt_disable(Irql);
781    if ( Console_Port_Data[minor].bActive == FALSE) {
782      Console_Port_Data[minor].bActive = TRUE;
783      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR);
784    }
785    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf);
786  rtems_interrupt_enable(Irql);
787
788  return 0;
789}
790
791/*
792 *  z85c30_inbyte_nonblocking_polled
793 *
794 *  This routine polls for a character.
795 */
796
797Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
798  int  minor
799)
800{
801  volatile uint8_t    z85c30_status;
802  uint32_t            ulCtrlPort;
803  getRegister_f       getReg;
804
805  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
806  getReg     = Console_Port_Tbl[minor]->getRegister;
807
808  /*
809   * return -1 if a character is not available.
810   */
811  z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
812  if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
813    return -1;
814  }
815
816  /*
817   * Return the character read.
818   */
819
820  return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
821}
822
823/*
824 *  z85c30_write_support_polled
825 *
826 *  Console Termios output entry point.
827 *
828 */
829
830Z85C30_STATIC ssize_t z85c30_write_support_polled(
831  int   minor,
832  const char *buf,
833  size_t len)
834{
835  int nwrite=0;
836
837  /*
838   * poll each byte in the string out of the port.
839   */
840  while (nwrite < len) {
841    z85c30_write_polled(minor, *buf++);
842    nwrite++;
843  }
844
845  /*
846   * return the number of bytes written.
847   */
848  return nwrite;
849}
850
851/*
852 *  z85c30_write_polled
853 *
854 *  This routine transmits a character using polling.
855 */
856
857Z85C30_STATIC void z85c30_write_polled(
858  int   minor,
859  char  cChar
860)
861{
862  volatile uint8_t   z85c30_status;
863  uint32_t           ulCtrlPort;
864  getRegister_f      getReg;
865  setRegister_f      setReg;
866
867  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
868  getReg     = Console_Port_Tbl[minor]->getRegister;
869  setReg     = Console_Port_Tbl[minor]->setRegister;
870
871  /*
872   * Wait for the Transmit buffer to indicate that it is empty.
873   */
874
875  z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 );
876
877  while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
878    /*
879     * Yield while we wait
880     */
881#if 0
882    if (_System_state_Is_up(_System_state_Get())) {
883      rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
884    }
885#endif
886    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
887  }
888
889  /*
890   * Write the character.
891   */
892
893  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar );
894}
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