[0737710] | 1 | /* |
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| 2 | * This file contains the console driver chip level routines for the |
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[e4acf68] | 3 | * Zilog z85c30 chip. |
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| 4 | * |
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| 5 | * The Zilog Z8530 is also available as: |
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| 6 | * |
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| 7 | * + Intel 82530 |
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| 8 | * + AMD ??? |
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[0737710] | 9 | * |
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| 10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 11 | * |
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| 12 | * |
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| 13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 17 | * |
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| 18 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 19 | * this file, provided that this notice, plus the above copyright notice |
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| 20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 21 | * no support for this code. |
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| 22 | * |
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| 23 | * COPYRIGHT (c) 1989-1997. |
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| 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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| 28 | * http://www.OARcorp.com/rtems/license.html. |
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| 29 | * |
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| 30 | * $Id$ |
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| 31 | */ |
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| 32 | |
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| 33 | #include <rtems.h> |
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| 34 | #include <rtems/libio.h> |
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| 35 | #include <stdlib.h> |
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| 36 | |
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[ee3b242b] | 37 | #include <libchip/serial.h> |
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[7e05b53] | 38 | #include <libchip/sersupp.h> |
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[0737710] | 39 | #include "z85c30_p.h" |
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| 40 | |
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| 41 | /* |
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| 42 | * Flow control is only supported when using interrupts |
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| 43 | */ |
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[e4acf68] | 44 | |
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[749c54e] | 45 | console_flow z85c30_flow_RTSCTS = { |
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[0737710] | 46 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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| 47 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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| 48 | }; |
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| 49 | |
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[749c54e] | 50 | console_flow z85c30_flow_DTRCTS = { |
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[0737710] | 51 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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| 52 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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| 53 | }; |
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| 54 | |
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| 55 | /* |
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| 56 | * Exported driver function table |
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| 57 | */ |
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[e4acf68] | 58 | |
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[749c54e] | 59 | console_fns z85c30_fns = { |
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[fb32356b] | 60 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 61 | z85c30_open, /* deviceFirstOpen */ |
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[04c5ac7] | 62 | NULL, /* deviceLastClose */ |
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[0737710] | 63 | NULL, /* deviceRead */ |
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| 64 | z85c30_write_support_int, /* deviceWrite */ |
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| 65 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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| 66 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 67 | NULL, /* deviceSetAttributes */ |
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[e283140c] | 68 | TRUE /* deviceOutputUsesInterrupts */ |
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[0737710] | 69 | }; |
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| 70 | |
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[749c54e] | 71 | console_fns z85c30_fns_polled = { |
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[fb32356b] | 72 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 73 | z85c30_open, /* deviceFirstOpen */ |
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| 74 | z85c30_close, /* deviceLastClose */ |
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| 75 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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| 76 | z85c30_write_support_polled, /* deviceWrite */ |
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| 77 | z85c30_init, /* deviceInitialize */ |
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| 78 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 79 | NULL, /* deviceSetAttributes */ |
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[b636d56] | 80 | FALSE /* deviceOutputUsesInterrupts */ |
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[0737710] | 81 | }; |
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| 82 | |
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| 83 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 84 | |
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| 85 | /* |
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[749c54e] | 86 | * z85c30_initialize_port |
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[0737710] | 87 | * |
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[749c54e] | 88 | * initialize a z85c30 Port |
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[0737710] | 89 | */ |
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| 90 | |
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[677a503] | 91 | Z85C30_STATIC void z85c30_initialize_port( |
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[0737710] | 92 | int minor |
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| 93 | ) |
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| 94 | { |
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| 95 | unsigned32 ulCtrlPort; |
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| 96 | unsigned32 ulBaudDivisor; |
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| 97 | setRegister_f setReg; |
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| 98 | |
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| 99 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 100 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 101 | |
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| 102 | /* |
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| 103 | * Using register 4 |
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| 104 | * Set up the clock rate is 16 times the data |
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| 105 | * rate, 8 bit sync char, 1 stop bit, no parity |
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| 106 | */ |
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| 107 | |
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| 108 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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| 109 | |
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| 110 | /* |
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| 111 | * Set up for 8 bits/character on receive with |
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| 112 | * receiver disable via register 3 |
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| 113 | */ |
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| 114 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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| 115 | |
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| 116 | /* |
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| 117 | * Set up for 8 bits/character on transmit |
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| 118 | * with transmitter disable via register 5 |
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| 119 | */ |
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| 120 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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| 121 | |
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| 122 | /* |
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| 123 | * Clear misc control bits |
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| 124 | */ |
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| 125 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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| 126 | |
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| 127 | /* |
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| 128 | * Setup the source of the receive and xmit |
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| 129 | * clock as BRG output and the transmit clock |
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| 130 | * as the output source for TRxC pin via register 11 |
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| 131 | */ |
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| 132 | (*setReg)( |
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| 133 | ulCtrlPort, |
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| 134 | SCC_WR0_SEL_WR11, |
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| 135 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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| 136 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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| 137 | ); |
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| 138 | |
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| 139 | ulBaudDivisor = Z85C30_Baud( |
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| 140 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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| 141 | (unsigned32) Console_Port_Tbl[minor].pDeviceParams |
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| 142 | ); |
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| 143 | |
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| 144 | /* |
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| 145 | * Setup the lower 8 bits time constants=1E. |
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| 146 | * If the time constans=1E, then the desire |
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| 147 | * baud rate will be equilvalent to 9600, via register 12. |
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| 148 | */ |
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| 149 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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| 150 | |
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| 151 | /* |
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| 152 | * using register 13 |
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| 153 | * Setup the upper 8 bits time constant |
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| 154 | */ |
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| 155 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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| 156 | |
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| 157 | /* |
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| 158 | * Enable the baud rate generator enable with clock from the |
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| 159 | * SCC's PCLK input via register 14. |
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| 160 | */ |
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| 161 | (*setReg)( |
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| 162 | ulCtrlPort, |
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| 163 | SCC_WR0_SEL_WR14, |
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| 164 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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| 165 | ); |
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| 166 | |
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| 167 | /* |
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| 168 | * We are only interested in CTS state changes |
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| 169 | */ |
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| 170 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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| 171 | |
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| 172 | /* |
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| 173 | * Reset errors |
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| 174 | */ |
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| 175 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 176 | |
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| 177 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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| 178 | |
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| 179 | /* |
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| 180 | * Enable the receiver via register 3 |
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| 181 | */ |
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| 182 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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| 183 | |
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| 184 | /* |
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| 185 | * Enable the transmitter pins set via register 5. |
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| 186 | */ |
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| 187 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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| 188 | |
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| 189 | /* |
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| 190 | * Disable interrupts |
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| 191 | */ |
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| 192 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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| 193 | |
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| 194 | /* |
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| 195 | * Reset TX CRC |
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| 196 | */ |
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| 197 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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| 198 | |
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| 199 | /* |
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| 200 | * Reset interrupts |
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| 201 | */ |
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| 202 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 203 | } |
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| 204 | |
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[749c54e] | 205 | /* |
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| 206 | * z85c30_open |
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| 207 | */ |
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| 208 | |
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[677a503] | 209 | Z85C30_STATIC int z85c30_open( |
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[0737710] | 210 | int major, |
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| 211 | int minor, |
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| 212 | void *arg |
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| 213 | ) |
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| 214 | { |
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[04c5ac7] | 215 | |
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| 216 | z85c30_initialize_port(minor); |
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| 217 | |
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[0737710] | 218 | /* |
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| 219 | * Assert DTR |
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| 220 | */ |
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| 221 | |
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| 222 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 223 | z85c30_assert_DTR(minor); |
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| 224 | } |
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| 225 | |
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| 226 | return(RTEMS_SUCCESSFUL); |
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| 227 | } |
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| 228 | |
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[749c54e] | 229 | /* |
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| 230 | * z85c30_close |
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| 231 | */ |
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| 232 | |
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[677a503] | 233 | Z85C30_STATIC int z85c30_close( |
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[0737710] | 234 | int major, |
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| 235 | int minor, |
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| 236 | void *arg |
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| 237 | ) |
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| 238 | { |
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| 239 | /* |
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| 240 | * Negate DTR |
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| 241 | */ |
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| 242 | |
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| 243 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 244 | z85c30_negate_DTR(minor); |
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| 245 | } |
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| 246 | |
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| 247 | return(RTEMS_SUCCESSFUL); |
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| 248 | } |
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| 249 | |
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| 250 | /* |
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[749c54e] | 251 | * z85c30_init |
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[0737710] | 252 | */ |
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| 253 | |
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[677a503] | 254 | Z85C30_STATIC void z85c30_init(int minor) |
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[0737710] | 255 | { |
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| 256 | unsigned32 ulCtrlPort; |
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| 257 | unsigned8 dummy; |
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| 258 | z85c30_context *pz85c30Context; |
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| 259 | setRegister_f setReg; |
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| 260 | getRegister_f getReg; |
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| 261 | |
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| 262 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 263 | getReg = Console_Port_Tbl[minor].getRegister; |
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| 264 | |
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| 265 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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| 266 | |
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[c14a619] | 267 | Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context; |
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[0737710] | 268 | |
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| 269 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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| 270 | |
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| 271 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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[c14a619] | 272 | if ( ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2 ) { |
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[0737710] | 273 | /* |
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| 274 | * This is channel A |
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| 275 | */ |
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| 276 | /* |
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| 277 | * Ensure port state machine is reset |
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| 278 | */ |
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| 279 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 280 | |
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| 281 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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| 282 | |
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| 283 | } else { |
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| 284 | /* |
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| 285 | * This is channel B |
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| 286 | */ |
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| 287 | /* |
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| 288 | * Ensure port state machine is reset |
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| 289 | */ |
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| 290 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 291 | |
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| 292 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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| 293 | } |
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| 294 | } |
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| 295 | |
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| 296 | /* |
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| 297 | * These routines provide control of the RTS and DTR lines |
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| 298 | */ |
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[e4acf68] | 299 | |
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[0737710] | 300 | /* |
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| 301 | * z85c30_assert_RTS |
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| 302 | */ |
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[e4acf68] | 303 | |
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[677a503] | 304 | Z85C30_STATIC int z85c30_assert_RTS(int minor) |
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[0737710] | 305 | { |
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| 306 | rtems_interrupt_level Irql; |
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| 307 | z85c30_context *pz85c30Context; |
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| 308 | setRegister_f setReg; |
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| 309 | |
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| 310 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 311 | |
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| 312 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 313 | |
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| 314 | /* |
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| 315 | * Assert RTS |
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| 316 | */ |
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| 317 | |
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| 318 | rtems_interrupt_disable(Irql); |
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| 319 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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| 320 | (*setReg)( |
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| 321 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 322 | SCC_WR0_SEL_WR5, |
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| 323 | pz85c30Context->ucModemCtrl |
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| 324 | ); |
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| 325 | rtems_interrupt_enable(Irql); |
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| 326 | return 0; |
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| 327 | } |
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| 328 | |
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| 329 | /* |
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| 330 | * z85c30_negate_RTS |
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| 331 | */ |
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[e4acf68] | 332 | |
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[677a503] | 333 | Z85C30_STATIC int z85c30_negate_RTS(int minor) |
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[0737710] | 334 | { |
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| 335 | rtems_interrupt_level Irql; |
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| 336 | z85c30_context *pz85c30Context; |
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| 337 | setRegister_f setReg; |
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| 338 | |
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| 339 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 340 | |
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| 341 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 342 | |
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| 343 | /* |
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| 344 | * Negate RTS |
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| 345 | */ |
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| 346 | |
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| 347 | rtems_interrupt_disable(Irql); |
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| 348 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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| 349 | (*setReg)( |
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| 350 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 351 | SCC_WR0_SEL_WR5, |
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| 352 | pz85c30Context->ucModemCtrl |
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| 353 | ); |
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| 354 | rtems_interrupt_enable(Irql); |
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| 355 | return 0; |
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| 356 | } |
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| 357 | |
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| 358 | /* |
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| 359 | * These flow control routines utilise a connection from the local DTR |
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| 360 | * line to the remote CTS line |
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| 361 | */ |
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[e4acf68] | 362 | |
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[0737710] | 363 | /* |
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| 364 | * z85c30_assert_DTR |
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| 365 | */ |
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[e4acf68] | 366 | |
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[677a503] | 367 | Z85C30_STATIC int z85c30_assert_DTR(int minor) |
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[0737710] | 368 | { |
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| 369 | rtems_interrupt_level Irql; |
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| 370 | z85c30_context *pz85c30Context; |
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| 371 | setRegister_f setReg; |
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| 372 | |
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| 373 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 374 | |
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| 375 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 376 | |
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| 377 | /* |
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| 378 | * Assert DTR |
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| 379 | */ |
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| 380 | |
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| 381 | rtems_interrupt_disable(Irql); |
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| 382 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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| 383 | (*setReg)( |
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| 384 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 385 | SCC_WR0_SEL_WR5, |
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| 386 | pz85c30Context->ucModemCtrl |
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| 387 | ); |
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| 388 | rtems_interrupt_enable(Irql); |
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| 389 | return 0; |
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| 390 | } |
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| 391 | |
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| 392 | /* |
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| 393 | * z85c30_negate_DTR |
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| 394 | */ |
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[e4acf68] | 395 | |
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[677a503] | 396 | Z85C30_STATIC int z85c30_negate_DTR(int minor) |
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[0737710] | 397 | { |
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| 398 | rtems_interrupt_level Irql; |
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| 399 | z85c30_context *pz85c30Context; |
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| 400 | setRegister_f setReg; |
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| 401 | |
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| 402 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 403 | |
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| 404 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 405 | |
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| 406 | /* |
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| 407 | * Negate DTR |
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| 408 | */ |
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| 409 | |
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| 410 | rtems_interrupt_disable(Irql); |
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| 411 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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| 412 | (*setReg)( |
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| 413 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 414 | SCC_WR0_SEL_WR5, |
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| 415 | pz85c30Context->ucModemCtrl |
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| 416 | ); |
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| 417 | rtems_interrupt_enable(Irql); |
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| 418 | return 0; |
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| 419 | } |
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| 420 | |
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[fb32356b] | 421 | /* |
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| 422 | * z85c30_set_attributes |
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| 423 | * |
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| 424 | * This function sets the SCC channel to reflect the requested termios |
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| 425 | * port settings. |
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| 426 | */ |
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| 427 | |
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| 428 | Z85C30_STATIC int z85c30_set_attributes( |
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| 429 | int minor, |
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| 430 | const struct termios *t |
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| 431 | ) |
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| 432 | { |
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| 433 | unsigned32 ulCtrlPort; |
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| 434 | unsigned32 ulBaudDivisor; |
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| 435 | unsigned32 wr3; |
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| 436 | unsigned32 wr4; |
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| 437 | unsigned32 wr5; |
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| 438 | int baud_requested; |
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| 439 | setRegister_f setReg; |
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| 440 | rtems_interrupt_level Irql; |
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| 441 | |
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| 442 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 443 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 444 | |
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| 445 | /* |
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| 446 | * Calculate the baud rate divisor |
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| 447 | */ |
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| 448 | |
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| 449 | baud_requested = t->c_cflag & CBAUD; |
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| 450 | if (!baud_requested) |
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| 451 | baud_requested = B9600; /* default to 9600 baud */ |
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| 452 | |
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| 453 | ulBaudDivisor = Z85C30_Baud( |
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| 454 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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| 455 | (unsigned32) termios_baud_to_number( baud_requested ) |
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| 456 | ); |
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| 457 | |
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| 458 | wr3 = SCC_WR3_RX_EN; |
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| 459 | wr4 = SCC_WR4_16_CLOCK; |
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| 460 | wr5 = SCC_WR5_TX_EN; |
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| 461 | |
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| 462 | /* |
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| 463 | * Parity |
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| 464 | */ |
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| 465 | |
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| 466 | if (t->c_cflag & PARENB) { |
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| 467 | wr4 |= SCC_WR4_PAR_EN; |
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| 468 | if (!(t->c_cflag & PARODD)) |
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| 469 | wr4 |= SCC_WR4_PAR_EVEN; |
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| 470 | } |
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| 471 | |
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| 472 | /* |
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| 473 | * Character Size |
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| 474 | */ |
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| 475 | |
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| 476 | if (t->c_cflag & CSIZE) { |
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| 477 | switch (t->c_cflag & CSIZE) { |
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| 478 | case CS5: break; |
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| 479 | case CS6: wr3 |= SCC_WR3_RX_6_BITS; wr5 |= SCC_WR5_TX_6_BITS; break; |
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| 480 | case CS7: wr3 |= SCC_WR3_RX_7_BITS; wr5 |= SCC_WR5_TX_7_BITS; break; |
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| 481 | case CS8: wr3 |= SCC_WR3_RX_8_BITS; wr5 |= SCC_WR5_TX_8_BITS; break; |
---|
| 482 | } |
---|
| 483 | } else { |
---|
| 484 | wr3 |= SCC_WR3_RX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 485 | wr5 |= SCC_WR5_TX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 486 | } |
---|
| 487 | |
---|
| 488 | /* |
---|
| 489 | * Stop Bits |
---|
| 490 | */ |
---|
| 491 | |
---|
| 492 | if (t->c_cflag & CSTOPB) { |
---|
| 493 | wr4 |= SCC_WR4_2_STOP; /* 2 stop bits */ |
---|
| 494 | } else { |
---|
| 495 | wr4 |= SCC_WR4_1_STOP; /* 1 stop bits */ |
---|
| 496 | } |
---|
| 497 | |
---|
[b636d56] | 498 | /* |
---|
| 499 | * Now actually set the chip |
---|
| 500 | */ |
---|
| 501 | |
---|
[fb32356b] | 502 | rtems_interrupt_disable(Irql); |
---|
| 503 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 ); |
---|
| 504 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 ); |
---|
| 505 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 ); |
---|
| 506 | |
---|
| 507 | /* |
---|
| 508 | * Setup the lower 8 bits time constants=1E. |
---|
| 509 | * If the time constans=1E, then the desire |
---|
| 510 | * baud rate will be equilvalent to 9600, via register 12. |
---|
| 511 | */ |
---|
| 512 | |
---|
| 513 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
---|
| 514 | |
---|
| 515 | /* |
---|
| 516 | * using register 13 |
---|
| 517 | * Setup the upper 8 bits time constant |
---|
| 518 | */ |
---|
| 519 | |
---|
| 520 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
---|
| 521 | |
---|
| 522 | rtems_interrupt_enable(Irql); |
---|
| 523 | |
---|
| 524 | return 0; |
---|
| 525 | } |
---|
| 526 | |
---|
[0737710] | 527 | /* |
---|
[749c54e] | 528 | * z85c30_process |
---|
[0737710] | 529 | * |
---|
[749c54e] | 530 | * This is the per port ISR handler. |
---|
[0737710] | 531 | */ |
---|
| 532 | |
---|
[677a503] | 533 | Z85C30_STATIC void z85c30_process( |
---|
[0737710] | 534 | int minor, |
---|
| 535 | unsigned8 ucIntPend |
---|
| 536 | ) |
---|
| 537 | { |
---|
| 538 | unsigned32 ulCtrlPort; |
---|
| 539 | volatile unsigned8 z85c30_status; |
---|
[cb27f05] | 540 | unsigned char cChar; |
---|
[0737710] | 541 | setRegister_f setReg; |
---|
| 542 | getRegister_f getReg; |
---|
| 543 | |
---|
| 544 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 545 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 546 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 547 | |
---|
| 548 | /* |
---|
| 549 | * Deal with any received characters |
---|
| 550 | */ |
---|
[04c5ac7] | 551 | |
---|
[0737710] | 552 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
| 553 | { |
---|
[c14a619] | 554 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 555 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 556 | break; |
---|
| 557 | } |
---|
| 558 | |
---|
| 559 | /* |
---|
| 560 | * Return the character read. |
---|
| 561 | */ |
---|
| 562 | |
---|
[c14a619] | 563 | cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 564 | |
---|
| 565 | rtems_termios_enqueue_raw_characters( |
---|
| 566 | Console_Port_Data[minor].termios_data, |
---|
| 567 | &cChar, |
---|
| 568 | 1 |
---|
| 569 | ); |
---|
| 570 | } |
---|
| 571 | |
---|
[04c5ac7] | 572 | /* |
---|
| 573 | * There could be a race condition here if there is not yet a TX |
---|
| 574 | * interrupt pending but the buffer is empty. This condition has |
---|
| 575 | * been seen before on other z8530 drivers but has not been seen |
---|
| 576 | * with this one. The typical solution is to use "vector includes |
---|
| 577 | * status" or to only look at the interrupts actually pending |
---|
| 578 | * in RR3. |
---|
| 579 | */ |
---|
| 580 | |
---|
| 581 | while (TRUE) { |
---|
[0737710] | 582 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 583 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 584 | /* |
---|
| 585 | * We'll get another interrupt when |
---|
| 586 | * the transmitter holding reg. becomes |
---|
| 587 | * free again and we are clear to send |
---|
| 588 | */ |
---|
| 589 | break; |
---|
| 590 | } |
---|
| 591 | |
---|
[04c5ac7] | 592 | #if 0 |
---|
[0737710] | 593 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
| 594 | /* |
---|
| 595 | * We can't transmit yet |
---|
| 596 | */ |
---|
| 597 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 598 | /* |
---|
| 599 | * The next state change of CTS will wake us up |
---|
| 600 | */ |
---|
| 601 | break; |
---|
| 602 | } |
---|
[04c5ac7] | 603 | #endif |
---|
[0737710] | 604 | |
---|
[bfcf4cb3] | 605 | rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1); |
---|
[692b9f7] | 606 | if (rtems_termios_dequeue_characters( |
---|
| 607 | Console_Port_Data[minor].termios_data, 1)) { |
---|
[04c5ac7] | 608 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 609 | z85c30_negate_RTS(minor); |
---|
| 610 | } |
---|
[04c5ac7] | 611 | Console_Port_Data[minor].bActive = FALSE; |
---|
| 612 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
[0737710] | 613 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 614 | break; |
---|
| 615 | } |
---|
| 616 | |
---|
| 617 | } |
---|
| 618 | |
---|
[04c5ac7] | 619 | if (ucIntPend & SCC_RR3_B_EXT_IP) { |
---|
[0737710] | 620 | /* |
---|
| 621 | * Clear the external status interrupt |
---|
| 622 | */ |
---|
| 623 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[c14a619] | 624 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 625 | } |
---|
| 626 | |
---|
| 627 | /* |
---|
| 628 | * Reset interrupts |
---|
| 629 | */ |
---|
| 630 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
| 631 | } |
---|
| 632 | |
---|
[749c54e] | 633 | /* |
---|
| 634 | * z85c30_isr |
---|
| 635 | * |
---|
| 636 | * This is the ISR handler for each Z8530. |
---|
| 637 | */ |
---|
| 638 | |
---|
[677a503] | 639 | Z85C30_STATIC rtems_isr z85c30_isr( |
---|
[0737710] | 640 | rtems_vector_number vector |
---|
| 641 | ) |
---|
| 642 | { |
---|
| 643 | int minor; |
---|
| 644 | unsigned32 ulCtrlPort; |
---|
| 645 | volatile unsigned8 ucIntPend; |
---|
| 646 | volatile unsigned8 ucIntPendPort; |
---|
[749c54e] | 647 | getRegister_f getReg; |
---|
[0737710] | 648 | |
---|
| 649 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
[991a1ab4] | 650 | if(Console_Port_Tbl[minor].ulIntVector == vector && |
---|
| 651 | Console_Port_Tbl[minor].deviceType == SERIAL_Z85C30 ) { |
---|
[0737710] | 652 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 653 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 654 | do { |
---|
[c14a619] | 655 | ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
[0737710] | 656 | |
---|
| 657 | /* |
---|
| 658 | * If this is channel A select channel A status |
---|
| 659 | */ |
---|
| 660 | |
---|
| 661 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
[973bf436] | 662 | ucIntPendPort = ucIntPend >> 3; |
---|
| 663 | ucIntPendPort &= 7; |
---|
[0737710] | 664 | } else { |
---|
| 665 | ucIntPendPort = ucIntPend &= 7; |
---|
| 666 | } |
---|
| 667 | |
---|
| 668 | if (ucIntPendPort) { |
---|
| 669 | z85c30_process(minor, ucIntPendPort); |
---|
| 670 | } |
---|
| 671 | } while (ucIntPendPort); |
---|
| 672 | } |
---|
| 673 | } |
---|
| 674 | } |
---|
| 675 | |
---|
| 676 | /* |
---|
[04c5ac7] | 677 | * z85c30_enable_interrupts |
---|
| 678 | * |
---|
| 679 | * This routine enables the specified interrupts for this minor. |
---|
[0737710] | 680 | */ |
---|
| 681 | |
---|
[04c5ac7] | 682 | Z85C30_STATIC void z85c30_enable_interrupts( |
---|
[0737710] | 683 | int minor, |
---|
[04c5ac7] | 684 | int interrupt_mask |
---|
[0737710] | 685 | ) |
---|
| 686 | { |
---|
[04c5ac7] | 687 | unsigned32 ulCtrlPort; |
---|
| 688 | setRegister_f setReg; |
---|
[0737710] | 689 | |
---|
[04c5ac7] | 690 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 691 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 692 | |
---|
[04c5ac7] | 693 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask); |
---|
[0737710] | 694 | } |
---|
| 695 | |
---|
| 696 | /* |
---|
| 697 | * z85c30_initialize_interrupts |
---|
| 698 | * |
---|
[04c5ac7] | 699 | * This routine initializes the port to use interrupts. |
---|
[0737710] | 700 | */ |
---|
| 701 | |
---|
[04c5ac7] | 702 | Z85C30_STATIC void z85c30_initialize_interrupts( |
---|
[0737710] | 703 | int minor |
---|
| 704 | ) |
---|
| 705 | { |
---|
[04c5ac7] | 706 | unsigned32 ulCtrlPort1; |
---|
| 707 | unsigned32 ulCtrlPort2; |
---|
[0737710] | 708 | setRegister_f setReg; |
---|
| 709 | |
---|
[04c5ac7] | 710 | ulCtrlPort1 = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 711 | ulCtrlPort2 = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 712 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 713 | |
---|
| 714 | |
---|
| 715 | z85c30_init(minor); |
---|
| 716 | |
---|
| 717 | Console_Port_Data[minor].bActive=FALSE; |
---|
[04c5ac7] | 718 | |
---|
| 719 | z85c30_initialize_port( minor ); |
---|
| 720 | |
---|
| 721 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 722 | z85c30_negate_RTS(minor); |
---|
| 723 | } |
---|
| 724 | |
---|
[04c5ac7] | 725 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
[0737710] | 726 | |
---|
[04c5ac7] | 727 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
| 728 | |
---|
| 729 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0); /* XXX vector */ |
---|
| 730 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
| 731 | |
---|
| 732 | /* |
---|
| 733 | * Reset interrupts |
---|
| 734 | */ |
---|
[0737710] | 735 | |
---|
[04c5ac7] | 736 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[0737710] | 737 | } |
---|
| 738 | |
---|
| 739 | /* |
---|
| 740 | * z85c30_write_support_int |
---|
| 741 | * |
---|
| 742 | * Console Termios output entry point. |
---|
| 743 | * |
---|
| 744 | */ |
---|
[e4acf68] | 745 | |
---|
[677a503] | 746 | Z85C30_STATIC int z85c30_write_support_int( |
---|
[0737710] | 747 | int minor, |
---|
| 748 | const char *buf, |
---|
| 749 | int len) |
---|
| 750 | { |
---|
[04c5ac7] | 751 | unsigned32 Irql; |
---|
| 752 | unsigned32 ulCtrlPort; |
---|
| 753 | setRegister_f setReg; |
---|
[0737710] | 754 | |
---|
[04c5ac7] | 755 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 756 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 757 | |
---|
| 758 | /* |
---|
[04c5ac7] | 759 | * We are using interrupt driven output and termios only sends us |
---|
| 760 | * one character at a time. |
---|
[0737710] | 761 | */ |
---|
[04c5ac7] | 762 | |
---|
| 763 | if ( !len ) |
---|
| 764 | return 0; |
---|
| 765 | |
---|
| 766 | /* |
---|
| 767 | * Put the character out and enable interrupts if necessary. |
---|
| 768 | */ |
---|
| 769 | |
---|
| 770 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
| 771 | z85c30_assert_RTS(minor); |
---|
[0737710] | 772 | } |
---|
[04c5ac7] | 773 | rtems_interrupt_disable(Irql); |
---|
| 774 | if ( Console_Port_Data[minor].bActive == FALSE) { |
---|
| 775 | Console_Port_Data[minor].bActive = TRUE; |
---|
| 776 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR); |
---|
| 777 | } |
---|
| 778 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf); |
---|
| 779 | rtems_interrupt_enable(Irql); |
---|
[0737710] | 780 | |
---|
[04c5ac7] | 781 | return 1; |
---|
[0737710] | 782 | } |
---|
| 783 | |
---|
| 784 | /* |
---|
| 785 | * z85c30_inbyte_nonblocking_polled |
---|
| 786 | * |
---|
| 787 | * This routine polls for a character. |
---|
| 788 | */ |
---|
[e4acf68] | 789 | |
---|
[677a503] | 790 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
---|
[0737710] | 791 | int minor |
---|
| 792 | ) |
---|
| 793 | { |
---|
| 794 | volatile unsigned8 z85c30_status; |
---|
| 795 | unsigned32 ulCtrlPort; |
---|
| 796 | getRegister_f getReg; |
---|
| 797 | |
---|
| 798 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 799 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 800 | |
---|
| 801 | /* |
---|
| 802 | * return -1 if a character is not available. |
---|
| 803 | */ |
---|
[c14a619] | 804 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 805 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 806 | return -1; |
---|
| 807 | } |
---|
| 808 | |
---|
| 809 | /* |
---|
| 810 | * Return the character read. |
---|
| 811 | */ |
---|
[c14a619] | 812 | |
---|
| 813 | return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 814 | } |
---|
| 815 | |
---|
| 816 | /* |
---|
| 817 | * z85c30_write_support_polled |
---|
| 818 | * |
---|
| 819 | * Console Termios output entry point. |
---|
| 820 | * |
---|
| 821 | */ |
---|
| 822 | |
---|
[677a503] | 823 | Z85C30_STATIC int z85c30_write_support_polled( |
---|
[0737710] | 824 | int minor, |
---|
| 825 | const char *buf, |
---|
| 826 | int len) |
---|
| 827 | { |
---|
| 828 | int nwrite=0; |
---|
| 829 | |
---|
| 830 | /* |
---|
| 831 | * poll each byte in the string out of the port. |
---|
| 832 | */ |
---|
| 833 | while (nwrite < len) { |
---|
| 834 | z85c30_write_polled(minor, *buf++); |
---|
| 835 | nwrite++; |
---|
| 836 | } |
---|
| 837 | |
---|
| 838 | /* |
---|
| 839 | * return the number of bytes written. |
---|
| 840 | */ |
---|
| 841 | return nwrite; |
---|
| 842 | } |
---|
[c14a619] | 843 | |
---|
| 844 | /* |
---|
| 845 | * z85c30_write_polled |
---|
| 846 | * |
---|
| 847 | * This routine transmits a character using polling. |
---|
| 848 | */ |
---|
| 849 | |
---|
| 850 | Z85C30_STATIC void z85c30_write_polled( |
---|
| 851 | int minor, |
---|
| 852 | char cChar |
---|
| 853 | ) |
---|
| 854 | { |
---|
| 855 | volatile unsigned8 z85c30_status; |
---|
| 856 | unsigned32 ulCtrlPort; |
---|
| 857 | getRegister_f getReg; |
---|
| 858 | setRegister_f setReg; |
---|
| 859 | |
---|
| 860 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 861 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 862 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 863 | |
---|
| 864 | /* |
---|
| 865 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
| 866 | */ |
---|
| 867 | |
---|
| 868 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
---|
| 869 | |
---|
| 870 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 871 | /* |
---|
| 872 | * Yield while we wait |
---|
| 873 | */ |
---|
[0eb85ae] | 874 | #if 0 |
---|
[c14a619] | 875 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 876 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 877 | } |
---|
[0eb85ae] | 878 | #endif |
---|
[c14a619] | 879 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 880 | } |
---|
| 881 | |
---|
| 882 | /* |
---|
| 883 | * Write the character. |
---|
| 884 | */ |
---|
| 885 | |
---|
| 886 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar ); |
---|
| 887 | } |
---|
| 888 | |
---|