[0737710] | 1 | /* |
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| 2 | * This file contains the console driver chip level routines for the |
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[e4acf68] | 3 | * Zilog z85c30 chip. |
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| 4 | * |
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| 5 | * The Zilog Z8530 is also available as: |
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| 6 | * |
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| 7 | * + Intel 82530 |
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| 8 | * + AMD ??? |
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[0737710] | 9 | * |
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| 10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 11 | * |
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| 12 | * |
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| 13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 17 | * |
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| 18 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 19 | * this file, provided that this notice, plus the above copyright notice |
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| 20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 21 | * no support for this code. |
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| 22 | * |
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| 23 | * COPYRIGHT (c) 1989-1997. |
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| 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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[94365d9] | 28 | * http://www.rtems.com/license/LICENSE. |
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[0737710] | 29 | * |
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| 30 | * $Id$ |
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| 31 | */ |
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| 32 | |
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| 33 | #include <rtems.h> |
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| 34 | #include <rtems/libio.h> |
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| 35 | #include <stdlib.h> |
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| 36 | |
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[ee3b242b] | 37 | #include <libchip/serial.h> |
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[7e05b53] | 38 | #include <libchip/sersupp.h> |
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[0737710] | 39 | #include "z85c30_p.h" |
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| 40 | |
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| 41 | /* |
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| 42 | * Flow control is only supported when using interrupts |
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| 43 | */ |
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[e4acf68] | 44 | |
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[749c54e] | 45 | console_flow z85c30_flow_RTSCTS = { |
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[0737710] | 46 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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| 47 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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| 48 | }; |
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| 49 | |
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[749c54e] | 50 | console_flow z85c30_flow_DTRCTS = { |
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[0737710] | 51 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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| 52 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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| 53 | }; |
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| 54 | |
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| 55 | /* |
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| 56 | * Exported driver function table |
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| 57 | */ |
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[e4acf68] | 58 | |
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[749c54e] | 59 | console_fns z85c30_fns = { |
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[fb32356b] | 60 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 61 | z85c30_open, /* deviceFirstOpen */ |
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[04c5ac7] | 62 | NULL, /* deviceLastClose */ |
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[0737710] | 63 | NULL, /* deviceRead */ |
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| 64 | z85c30_write_support_int, /* deviceWrite */ |
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| 65 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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| 66 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 67 | NULL, /* deviceSetAttributes */ |
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[6640459d] | 68 | true /* deviceOutputUsesInterrupts */ |
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[0737710] | 69 | }; |
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| 70 | |
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[749c54e] | 71 | console_fns z85c30_fns_polled = { |
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[fb32356b] | 72 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 73 | z85c30_open, /* deviceFirstOpen */ |
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| 74 | z85c30_close, /* deviceLastClose */ |
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| 75 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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| 76 | z85c30_write_support_polled, /* deviceWrite */ |
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| 77 | z85c30_init, /* deviceInitialize */ |
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| 78 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 79 | NULL, /* deviceSetAttributes */ |
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[6640459d] | 80 | false /* deviceOutputUsesInterrupts */ |
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[0737710] | 81 | }; |
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| 82 | |
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| 83 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 84 | |
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[a3d3d9a] | 85 | /* |
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[749c54e] | 86 | * z85c30_initialize_port |
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[0737710] | 87 | * |
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[749c54e] | 88 | * initialize a z85c30 Port |
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[0737710] | 89 | */ |
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| 90 | |
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[677a503] | 91 | Z85C30_STATIC void z85c30_initialize_port( |
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[0737710] | 92 | int minor |
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| 93 | ) |
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| 94 | { |
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[642c500] | 95 | uintptr_t ulCtrlPort; |
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| 96 | uintptr_t ulBaudDivisor; |
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[0737710] | 97 | setRegister_f setReg; |
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| 98 | |
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| 99 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 100 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 101 | |
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| 102 | /* |
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| 103 | * Using register 4 |
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| 104 | * Set up the clock rate is 16 times the data |
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| 105 | * rate, 8 bit sync char, 1 stop bit, no parity |
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| 106 | */ |
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| 107 | |
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| 108 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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| 109 | |
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| 110 | /* |
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| 111 | * Set up for 8 bits/character on receive with |
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| 112 | * receiver disable via register 3 |
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| 113 | */ |
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| 114 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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| 115 | |
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| 116 | /* |
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| 117 | * Set up for 8 bits/character on transmit |
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| 118 | * with transmitter disable via register 5 |
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| 119 | */ |
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| 120 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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| 121 | |
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| 122 | /* |
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| 123 | * Clear misc control bits |
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| 124 | */ |
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| 125 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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| 126 | |
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| 127 | /* |
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| 128 | * Setup the source of the receive and xmit |
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| 129 | * clock as BRG output and the transmit clock |
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| 130 | * as the output source for TRxC pin via register 11 |
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| 131 | */ |
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| 132 | (*setReg)( |
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| 133 | ulCtrlPort, |
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| 134 | SCC_WR0_SEL_WR11, |
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[a3d3d9a] | 135 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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[0737710] | 136 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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| 137 | ); |
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| 138 | |
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[a3d3d9a] | 139 | ulBaudDivisor = Z85C30_Baud( |
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[509fec9c] | 140 | (uint32_t) Console_Port_Tbl[minor].ulClock, |
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[642c500] | 141 | (uint32_t) ((uintptr_t)Console_Port_Tbl[minor].pDeviceParams) |
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[0737710] | 142 | ); |
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| 143 | |
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| 144 | /* |
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| 145 | * Setup the lower 8 bits time constants=1E. |
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| 146 | * If the time constans=1E, then the desire |
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| 147 | * baud rate will be equilvalent to 9600, via register 12. |
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| 148 | */ |
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| 149 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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| 150 | |
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| 151 | /* |
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| 152 | * using register 13 |
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| 153 | * Setup the upper 8 bits time constant |
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| 154 | */ |
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| 155 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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[a3d3d9a] | 156 | |
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[0737710] | 157 | /* |
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| 158 | * Enable the baud rate generator enable with clock from the |
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| 159 | * SCC's PCLK input via register 14. |
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| 160 | */ |
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| 161 | (*setReg)( |
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| 162 | ulCtrlPort, |
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| 163 | SCC_WR0_SEL_WR14, |
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| 164 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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| 165 | ); |
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| 166 | |
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| 167 | /* |
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| 168 | * We are only interested in CTS state changes |
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| 169 | */ |
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| 170 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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| 171 | |
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| 172 | /* |
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| 173 | * Reset errors |
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| 174 | */ |
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| 175 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 176 | |
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| 177 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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| 178 | |
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| 179 | /* |
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| 180 | * Enable the receiver via register 3 |
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| 181 | */ |
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| 182 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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| 183 | |
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| 184 | /* |
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| 185 | * Enable the transmitter pins set via register 5. |
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| 186 | */ |
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| 187 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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| 188 | |
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| 189 | /* |
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| 190 | * Disable interrupts |
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| 191 | */ |
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| 192 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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| 193 | |
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| 194 | /* |
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| 195 | * Reset TX CRC |
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| 196 | */ |
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| 197 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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| 198 | |
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| 199 | /* |
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| 200 | * Reset interrupts |
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| 201 | */ |
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| 202 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 203 | } |
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| 204 | |
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[749c54e] | 205 | /* |
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| 206 | * z85c30_open |
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| 207 | */ |
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| 208 | |
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[677a503] | 209 | Z85C30_STATIC int z85c30_open( |
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[0737710] | 210 | int major, |
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| 211 | int minor, |
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| 212 | void *arg |
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| 213 | ) |
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| 214 | { |
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[04c5ac7] | 215 | |
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| 216 | z85c30_initialize_port(minor); |
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| 217 | |
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[0737710] | 218 | /* |
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| 219 | * Assert DTR |
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| 220 | */ |
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| 221 | |
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| 222 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 223 | z85c30_assert_DTR(minor); |
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| 224 | } |
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| 225 | |
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| 226 | return(RTEMS_SUCCESSFUL); |
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| 227 | } |
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| 228 | |
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[749c54e] | 229 | /* |
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| 230 | * z85c30_close |
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| 231 | */ |
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| 232 | |
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[677a503] | 233 | Z85C30_STATIC int z85c30_close( |
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[0737710] | 234 | int major, |
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| 235 | int minor, |
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| 236 | void *arg |
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| 237 | ) |
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| 238 | { |
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| 239 | /* |
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| 240 | * Negate DTR |
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| 241 | */ |
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| 242 | |
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| 243 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 244 | z85c30_negate_DTR(minor); |
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| 245 | } |
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| 246 | |
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| 247 | return(RTEMS_SUCCESSFUL); |
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| 248 | } |
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| 249 | |
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| 250 | /* |
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[749c54e] | 251 | * z85c30_init |
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[0737710] | 252 | */ |
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| 253 | |
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[677a503] | 254 | Z85C30_STATIC void z85c30_init(int minor) |
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[0737710] | 255 | { |
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[642c500] | 256 | uintptr_t ulCtrlPort; |
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[0737710] | 257 | z85c30_context *pz85c30Context; |
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| 258 | setRegister_f setReg; |
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| 259 | getRegister_f getReg; |
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| 260 | |
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| 261 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 262 | getReg = Console_Port_Tbl[minor].getRegister; |
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| 263 | |
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| 264 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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| 265 | |
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[c14a619] | 266 | Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context; |
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[0737710] | 267 | |
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| 268 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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| 269 | |
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| 270 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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[c14a619] | 271 | if ( ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2 ) { |
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[0737710] | 272 | /* |
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| 273 | * This is channel A |
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| 274 | */ |
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| 275 | /* |
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| 276 | * Ensure port state machine is reset |
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| 277 | */ |
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[a399857] | 278 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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[0737710] | 279 | |
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| 280 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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| 281 | |
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| 282 | } else { |
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| 283 | /* |
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| 284 | * This is channel B |
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| 285 | */ |
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| 286 | /* |
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| 287 | * Ensure port state machine is reset |
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| 288 | */ |
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[a399857] | 289 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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[0737710] | 290 | |
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| 291 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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| 292 | } |
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| 293 | } |
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| 294 | |
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| 295 | /* |
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| 296 | * These routines provide control of the RTS and DTR lines |
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| 297 | */ |
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[e4acf68] | 298 | |
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[0737710] | 299 | /* |
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| 300 | * z85c30_assert_RTS |
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| 301 | */ |
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[e4acf68] | 302 | |
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[677a503] | 303 | Z85C30_STATIC int z85c30_assert_RTS(int minor) |
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[0737710] | 304 | { |
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| 305 | rtems_interrupt_level Irql; |
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| 306 | z85c30_context *pz85c30Context; |
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| 307 | setRegister_f setReg; |
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| 308 | |
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| 309 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 310 | |
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| 311 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 312 | |
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[0737710] | 313 | /* |
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| 314 | * Assert RTS |
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| 315 | */ |
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| 316 | |
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| 317 | rtems_interrupt_disable(Irql); |
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| 318 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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| 319 | (*setReg)( |
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| 320 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 321 | SCC_WR0_SEL_WR5, |
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| 322 | pz85c30Context->ucModemCtrl |
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| 323 | ); |
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| 324 | rtems_interrupt_enable(Irql); |
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| 325 | return 0; |
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| 326 | } |
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| 327 | |
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| 328 | /* |
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| 329 | * z85c30_negate_RTS |
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| 330 | */ |
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[e4acf68] | 331 | |
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[677a503] | 332 | Z85C30_STATIC int z85c30_negate_RTS(int minor) |
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[0737710] | 333 | { |
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| 334 | rtems_interrupt_level Irql; |
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| 335 | z85c30_context *pz85c30Context; |
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| 336 | setRegister_f setReg; |
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| 337 | |
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| 338 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 339 | |
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| 340 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 341 | |
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[0737710] | 342 | /* |
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| 343 | * Negate RTS |
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| 344 | */ |
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| 345 | |
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| 346 | rtems_interrupt_disable(Irql); |
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| 347 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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| 348 | (*setReg)( |
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| 349 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 350 | SCC_WR0_SEL_WR5, |
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| 351 | pz85c30Context->ucModemCtrl |
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| 352 | ); |
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| 353 | rtems_interrupt_enable(Irql); |
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| 354 | return 0; |
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| 355 | } |
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| 356 | |
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| 357 | /* |
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| 358 | * These flow control routines utilise a connection from the local DTR |
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| 359 | * line to the remote CTS line |
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| 360 | */ |
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[e4acf68] | 361 | |
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[0737710] | 362 | /* |
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| 363 | * z85c30_assert_DTR |
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| 364 | */ |
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[e4acf68] | 365 | |
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[677a503] | 366 | Z85C30_STATIC int z85c30_assert_DTR(int minor) |
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[0737710] | 367 | { |
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| 368 | rtems_interrupt_level Irql; |
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| 369 | z85c30_context *pz85c30Context; |
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| 370 | setRegister_f setReg; |
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| 371 | |
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| 372 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 373 | |
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| 374 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 375 | |
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[0737710] | 376 | /* |
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| 377 | * Assert DTR |
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| 378 | */ |
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| 379 | |
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| 380 | rtems_interrupt_disable(Irql); |
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| 381 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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| 382 | (*setReg)( |
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| 383 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 384 | SCC_WR0_SEL_WR5, |
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| 385 | pz85c30Context->ucModemCtrl |
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| 386 | ); |
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| 387 | rtems_interrupt_enable(Irql); |
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| 388 | return 0; |
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| 389 | } |
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| 390 | |
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| 391 | /* |
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| 392 | * z85c30_negate_DTR |
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| 393 | */ |
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[e4acf68] | 394 | |
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[677a503] | 395 | Z85C30_STATIC int z85c30_negate_DTR(int minor) |
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[0737710] | 396 | { |
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| 397 | rtems_interrupt_level Irql; |
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| 398 | z85c30_context *pz85c30Context; |
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| 399 | setRegister_f setReg; |
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| 400 | |
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| 401 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 402 | |
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| 403 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 404 | |
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[0737710] | 405 | /* |
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| 406 | * Negate DTR |
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| 407 | */ |
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| 408 | |
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| 409 | rtems_interrupt_disable(Irql); |
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| 410 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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| 411 | (*setReg)( |
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| 412 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 413 | SCC_WR0_SEL_WR5, |
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| 414 | pz85c30Context->ucModemCtrl |
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| 415 | ); |
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| 416 | rtems_interrupt_enable(Irql); |
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| 417 | return 0; |
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| 418 | } |
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| 419 | |
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[fb32356b] | 420 | /* |
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| 421 | * z85c30_set_attributes |
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| 422 | * |
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| 423 | * This function sets the SCC channel to reflect the requested termios |
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| 424 | * port settings. |
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| 425 | */ |
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| 426 | |
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| 427 | Z85C30_STATIC int z85c30_set_attributes( |
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| 428 | int minor, |
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| 429 | const struct termios *t |
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| 430 | ) |
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| 431 | { |
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[642c500] | 432 | uintptr_t ulCtrlPort; |
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[ee4f57d] | 433 | uint32_t ulBaudDivisor; |
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| 434 | uint32_t wr3; |
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| 435 | uint32_t wr4; |
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| 436 | uint32_t wr5; |
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[fb32356b] | 437 | int baud_requested; |
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| 438 | setRegister_f setReg; |
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| 439 | rtems_interrupt_level Irql; |
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| 440 | |
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| 441 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 442 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 443 | |
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| 444 | /* |
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| 445 | * Calculate the baud rate divisor |
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| 446 | */ |
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| 447 | |
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| 448 | baud_requested = t->c_cflag & CBAUD; |
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| 449 | if (!baud_requested) |
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| 450 | baud_requested = B9600; /* default to 9600 baud */ |
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| 451 | |
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[a3d3d9a] | 452 | ulBaudDivisor = Z85C30_Baud( |
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[509fec9c] | 453 | (uint32_t) Console_Port_Tbl[minor].ulClock, |
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[64a1529] | 454 | (uint32_t) rtems_termios_baud_to_number( baud_requested ) |
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[fb32356b] | 455 | ); |
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| 456 | |
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| 457 | wr3 = SCC_WR3_RX_EN; |
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| 458 | wr4 = SCC_WR4_16_CLOCK; |
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| 459 | wr5 = SCC_WR5_TX_EN; |
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| 460 | |
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| 461 | /* |
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| 462 | * Parity |
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| 463 | */ |
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| 464 | |
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| 465 | if (t->c_cflag & PARENB) { |
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| 466 | wr4 |= SCC_WR4_PAR_EN; |
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| 467 | if (!(t->c_cflag & PARODD)) |
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| 468 | wr4 |= SCC_WR4_PAR_EVEN; |
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[a3d3d9a] | 469 | } |
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[fb32356b] | 470 | |
---|
| 471 | /* |
---|
| 472 | * Character Size |
---|
| 473 | */ |
---|
| 474 | |
---|
| 475 | if (t->c_cflag & CSIZE) { |
---|
| 476 | switch (t->c_cflag & CSIZE) { |
---|
| 477 | case CS5: break; |
---|
| 478 | case CS6: wr3 |= SCC_WR3_RX_6_BITS; wr5 |= SCC_WR5_TX_6_BITS; break; |
---|
| 479 | case CS7: wr3 |= SCC_WR3_RX_7_BITS; wr5 |= SCC_WR5_TX_7_BITS; break; |
---|
| 480 | case CS8: wr3 |= SCC_WR3_RX_8_BITS; wr5 |= SCC_WR5_TX_8_BITS; break; |
---|
| 481 | } |
---|
| 482 | } else { |
---|
| 483 | wr3 |= SCC_WR3_RX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 484 | wr5 |= SCC_WR5_TX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 485 | } |
---|
| 486 | |
---|
| 487 | /* |
---|
| 488 | * Stop Bits |
---|
| 489 | */ |
---|
| 490 | |
---|
| 491 | if (t->c_cflag & CSTOPB) { |
---|
| 492 | wr4 |= SCC_WR4_2_STOP; /* 2 stop bits */ |
---|
| 493 | } else { |
---|
| 494 | wr4 |= SCC_WR4_1_STOP; /* 1 stop bits */ |
---|
| 495 | } |
---|
| 496 | |
---|
[b636d56] | 497 | /* |
---|
| 498 | * Now actually set the chip |
---|
| 499 | */ |
---|
| 500 | |
---|
[fb32356b] | 501 | rtems_interrupt_disable(Irql); |
---|
| 502 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 ); |
---|
| 503 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 ); |
---|
| 504 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 ); |
---|
| 505 | |
---|
| 506 | /* |
---|
| 507 | * Setup the lower 8 bits time constants=1E. |
---|
| 508 | * If the time constans=1E, then the desire |
---|
| 509 | * baud rate will be equilvalent to 9600, via register 12. |
---|
| 510 | */ |
---|
| 511 | |
---|
| 512 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
---|
| 513 | |
---|
| 514 | /* |
---|
| 515 | * using register 13 |
---|
| 516 | * Setup the upper 8 bits time constant |
---|
| 517 | */ |
---|
| 518 | |
---|
| 519 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
---|
| 520 | |
---|
| 521 | rtems_interrupt_enable(Irql); |
---|
| 522 | |
---|
| 523 | return 0; |
---|
| 524 | } |
---|
| 525 | |
---|
[0737710] | 526 | /* |
---|
[749c54e] | 527 | * z85c30_process |
---|
[0737710] | 528 | * |
---|
[749c54e] | 529 | * This is the per port ISR handler. |
---|
[0737710] | 530 | */ |
---|
| 531 | |
---|
[677a503] | 532 | Z85C30_STATIC void z85c30_process( |
---|
[0737710] | 533 | int minor, |
---|
[ee4f57d] | 534 | uint8_t ucIntPend |
---|
[0737710] | 535 | ) |
---|
| 536 | { |
---|
[ee4f57d] | 537 | uint32_t ulCtrlPort; |
---|
| 538 | volatile uint8_t z85c30_status; |
---|
[e11bf43] | 539 | char cChar; |
---|
[0737710] | 540 | setRegister_f setReg; |
---|
| 541 | getRegister_f getReg; |
---|
| 542 | |
---|
| 543 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 544 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 545 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 546 | |
---|
| 547 | /* |
---|
| 548 | * Deal with any received characters |
---|
| 549 | */ |
---|
[04c5ac7] | 550 | |
---|
[0737710] | 551 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
| 552 | { |
---|
[c14a619] | 553 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 554 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 555 | break; |
---|
| 556 | } |
---|
| 557 | |
---|
| 558 | /* |
---|
| 559 | * Return the character read. |
---|
| 560 | */ |
---|
| 561 | |
---|
[c14a619] | 562 | cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 563 | |
---|
| 564 | rtems_termios_enqueue_raw_characters( |
---|
| 565 | Console_Port_Data[minor].termios_data, |
---|
| 566 | &cChar, |
---|
| 567 | 1 |
---|
| 568 | ); |
---|
| 569 | } |
---|
| 570 | |
---|
[04c5ac7] | 571 | /* |
---|
| 572 | * There could be a race condition here if there is not yet a TX |
---|
| 573 | * interrupt pending but the buffer is empty. This condition has |
---|
| 574 | * been seen before on other z8530 drivers but has not been seen |
---|
| 575 | * with this one. The typical solution is to use "vector includes |
---|
| 576 | * status" or to only look at the interrupts actually pending |
---|
| 577 | * in RR3. |
---|
| 578 | */ |
---|
| 579 | |
---|
[6640459d] | 580 | while (true) { |
---|
[0737710] | 581 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 582 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 583 | /* |
---|
| 584 | * We'll get another interrupt when |
---|
| 585 | * the transmitter holding reg. becomes |
---|
| 586 | * free again and we are clear to send |
---|
| 587 | */ |
---|
| 588 | break; |
---|
| 589 | } |
---|
[a3d3d9a] | 590 | |
---|
[04c5ac7] | 591 | #if 0 |
---|
[0737710] | 592 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
| 593 | /* |
---|
| 594 | * We can't transmit yet |
---|
| 595 | */ |
---|
| 596 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 597 | /* |
---|
| 598 | * The next state change of CTS will wake us up |
---|
| 599 | */ |
---|
| 600 | break; |
---|
| 601 | } |
---|
[04c5ac7] | 602 | #endif |
---|
[a3d3d9a] | 603 | |
---|
[bfcf4cb3] | 604 | rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1); |
---|
[692b9f7] | 605 | if (rtems_termios_dequeue_characters( |
---|
| 606 | Console_Port_Data[minor].termios_data, 1)) { |
---|
[04c5ac7] | 607 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 608 | z85c30_negate_RTS(minor); |
---|
| 609 | } |
---|
[04c5ac7] | 610 | Console_Port_Data[minor].bActive = FALSE; |
---|
| 611 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
[0737710] | 612 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 613 | break; |
---|
| 614 | } |
---|
| 615 | |
---|
| 616 | } |
---|
| 617 | |
---|
[04c5ac7] | 618 | if (ucIntPend & SCC_RR3_B_EXT_IP) { |
---|
[0737710] | 619 | /* |
---|
| 620 | * Clear the external status interrupt |
---|
| 621 | */ |
---|
| 622 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[c14a619] | 623 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 624 | } |
---|
| 625 | |
---|
| 626 | /* |
---|
| 627 | * Reset interrupts |
---|
| 628 | */ |
---|
| 629 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
| 630 | } |
---|
| 631 | |
---|
[749c54e] | 632 | /* |
---|
| 633 | * z85c30_isr |
---|
| 634 | * |
---|
| 635 | * This is the ISR handler for each Z8530. |
---|
| 636 | */ |
---|
| 637 | |
---|
[677a503] | 638 | Z85C30_STATIC rtems_isr z85c30_isr( |
---|
[0737710] | 639 | rtems_vector_number vector |
---|
| 640 | ) |
---|
| 641 | { |
---|
| 642 | int minor; |
---|
[ee4f57d] | 643 | uint32_t ulCtrlPort; |
---|
| 644 | volatile uint8_t ucIntPend; |
---|
| 645 | volatile uint8_t ucIntPendPort; |
---|
[749c54e] | 646 | getRegister_f getReg; |
---|
[0737710] | 647 | |
---|
| 648 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
[a3d3d9a] | 649 | if(Console_Port_Tbl[minor].ulIntVector == vector && |
---|
[991a1ab4] | 650 | Console_Port_Tbl[minor].deviceType == SERIAL_Z85C30 ) { |
---|
[0737710] | 651 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 652 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 653 | do { |
---|
[c14a619] | 654 | ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
[0737710] | 655 | |
---|
| 656 | /* |
---|
| 657 | * If this is channel A select channel A status |
---|
| 658 | */ |
---|
| 659 | |
---|
| 660 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
[973bf436] | 661 | ucIntPendPort = ucIntPend >> 3; |
---|
| 662 | ucIntPendPort &= 7; |
---|
[0737710] | 663 | } else { |
---|
| 664 | ucIntPendPort = ucIntPend &= 7; |
---|
| 665 | } |
---|
| 666 | |
---|
| 667 | if (ucIntPendPort) { |
---|
| 668 | z85c30_process(minor, ucIntPendPort); |
---|
| 669 | } |
---|
| 670 | } while (ucIntPendPort); |
---|
| 671 | } |
---|
| 672 | } |
---|
| 673 | } |
---|
| 674 | |
---|
| 675 | /* |
---|
[04c5ac7] | 676 | * z85c30_enable_interrupts |
---|
| 677 | * |
---|
| 678 | * This routine enables the specified interrupts for this minor. |
---|
[0737710] | 679 | */ |
---|
| 680 | |
---|
[04c5ac7] | 681 | Z85C30_STATIC void z85c30_enable_interrupts( |
---|
[0737710] | 682 | int minor, |
---|
[04c5ac7] | 683 | int interrupt_mask |
---|
[0737710] | 684 | ) |
---|
| 685 | { |
---|
[ee4f57d] | 686 | uint32_t ulCtrlPort; |
---|
[04c5ac7] | 687 | setRegister_f setReg; |
---|
[0737710] | 688 | |
---|
[04c5ac7] | 689 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 690 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 691 | |
---|
[04c5ac7] | 692 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask); |
---|
[0737710] | 693 | } |
---|
| 694 | |
---|
| 695 | /* |
---|
| 696 | * z85c30_initialize_interrupts |
---|
| 697 | * |
---|
[04c5ac7] | 698 | * This routine initializes the port to use interrupts. |
---|
[0737710] | 699 | */ |
---|
| 700 | |
---|
[04c5ac7] | 701 | Z85C30_STATIC void z85c30_initialize_interrupts( |
---|
[0737710] | 702 | int minor |
---|
| 703 | ) |
---|
| 704 | { |
---|
[ee4f57d] | 705 | uint32_t ulCtrlPort1; |
---|
| 706 | uint32_t ulCtrlPort2; |
---|
[0737710] | 707 | setRegister_f setReg; |
---|
| 708 | |
---|
[04c5ac7] | 709 | ulCtrlPort1 = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 710 | ulCtrlPort2 = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 711 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 712 | |
---|
| 713 | |
---|
| 714 | z85c30_init(minor); |
---|
| 715 | |
---|
| 716 | Console_Port_Data[minor].bActive=FALSE; |
---|
[04c5ac7] | 717 | |
---|
| 718 | z85c30_initialize_port( minor ); |
---|
| 719 | |
---|
| 720 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 721 | z85c30_negate_RTS(minor); |
---|
| 722 | } |
---|
| 723 | |
---|
[04c5ac7] | 724 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
[0737710] | 725 | |
---|
[04c5ac7] | 726 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
| 727 | |
---|
| 728 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0); /* XXX vector */ |
---|
| 729 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
| 730 | |
---|
| 731 | /* |
---|
| 732 | * Reset interrupts |
---|
| 733 | */ |
---|
[0737710] | 734 | |
---|
[04c5ac7] | 735 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[0737710] | 736 | } |
---|
| 737 | |
---|
[a3d3d9a] | 738 | /* |
---|
[0737710] | 739 | * z85c30_write_support_int |
---|
| 740 | * |
---|
| 741 | * Console Termios output entry point. |
---|
| 742 | * |
---|
| 743 | */ |
---|
[e4acf68] | 744 | |
---|
[3ed964f9] | 745 | Z85C30_STATIC ssize_t z85c30_write_support_int( |
---|
[a3d3d9a] | 746 | int minor, |
---|
| 747 | const char *buf, |
---|
[3ed964f9] | 748 | size_t len) |
---|
[0737710] | 749 | { |
---|
[ee4f57d] | 750 | uint32_t Irql; |
---|
| 751 | uint32_t ulCtrlPort; |
---|
[04c5ac7] | 752 | setRegister_f setReg; |
---|
[0737710] | 753 | |
---|
[04c5ac7] | 754 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 755 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
[0737710] | 756 | |
---|
| 757 | /* |
---|
[04c5ac7] | 758 | * We are using interrupt driven output and termios only sends us |
---|
| 759 | * one character at a time. |
---|
[0737710] | 760 | */ |
---|
[04c5ac7] | 761 | |
---|
| 762 | if ( !len ) |
---|
| 763 | return 0; |
---|
| 764 | |
---|
| 765 | /* |
---|
| 766 | * Put the character out and enable interrupts if necessary. |
---|
| 767 | */ |
---|
| 768 | |
---|
| 769 | if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
| 770 | z85c30_assert_RTS(minor); |
---|
[0737710] | 771 | } |
---|
[04c5ac7] | 772 | rtems_interrupt_disable(Irql); |
---|
| 773 | if ( Console_Port_Data[minor].bActive == FALSE) { |
---|
| 774 | Console_Port_Data[minor].bActive = TRUE; |
---|
| 775 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR); |
---|
| 776 | } |
---|
| 777 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf); |
---|
| 778 | rtems_interrupt_enable(Irql); |
---|
[0737710] | 779 | |
---|
[3ed964f9] | 780 | return 0; |
---|
[0737710] | 781 | } |
---|
| 782 | |
---|
[a3d3d9a] | 783 | /* |
---|
[0737710] | 784 | * z85c30_inbyte_nonblocking_polled |
---|
| 785 | * |
---|
| 786 | * This routine polls for a character. |
---|
| 787 | */ |
---|
[e4acf68] | 788 | |
---|
[677a503] | 789 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
---|
[0737710] | 790 | int minor |
---|
| 791 | ) |
---|
| 792 | { |
---|
[ee4f57d] | 793 | volatile uint8_t z85c30_status; |
---|
| 794 | uint32_t ulCtrlPort; |
---|
[0737710] | 795 | getRegister_f getReg; |
---|
| 796 | |
---|
| 797 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 798 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 799 | |
---|
| 800 | /* |
---|
| 801 | * return -1 if a character is not available. |
---|
| 802 | */ |
---|
[c14a619] | 803 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 804 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 805 | return -1; |
---|
| 806 | } |
---|
| 807 | |
---|
| 808 | /* |
---|
| 809 | * Return the character read. |
---|
| 810 | */ |
---|
[c14a619] | 811 | |
---|
| 812 | return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 813 | } |
---|
| 814 | |
---|
[a3d3d9a] | 815 | /* |
---|
[0737710] | 816 | * z85c30_write_support_polled |
---|
| 817 | * |
---|
| 818 | * Console Termios output entry point. |
---|
| 819 | * |
---|
| 820 | */ |
---|
| 821 | |
---|
[3ed964f9] | 822 | Z85C30_STATIC ssize_t z85c30_write_support_polled( |
---|
[0737710] | 823 | int minor, |
---|
| 824 | const char *buf, |
---|
[3ed964f9] | 825 | size_t len) |
---|
[0737710] | 826 | { |
---|
| 827 | int nwrite=0; |
---|
| 828 | |
---|
| 829 | /* |
---|
| 830 | * poll each byte in the string out of the port. |
---|
| 831 | */ |
---|
| 832 | while (nwrite < len) { |
---|
| 833 | z85c30_write_polled(minor, *buf++); |
---|
| 834 | nwrite++; |
---|
| 835 | } |
---|
| 836 | |
---|
| 837 | /* |
---|
| 838 | * return the number of bytes written. |
---|
| 839 | */ |
---|
| 840 | return nwrite; |
---|
| 841 | } |
---|
[c14a619] | 842 | |
---|
[a3d3d9a] | 843 | /* |
---|
[c14a619] | 844 | * z85c30_write_polled |
---|
| 845 | * |
---|
| 846 | * This routine transmits a character using polling. |
---|
| 847 | */ |
---|
| 848 | |
---|
| 849 | Z85C30_STATIC void z85c30_write_polled( |
---|
| 850 | int minor, |
---|
| 851 | char cChar |
---|
| 852 | ) |
---|
| 853 | { |
---|
[ee4f57d] | 854 | volatile uint8_t z85c30_status; |
---|
| 855 | uint32_t ulCtrlPort; |
---|
[c14a619] | 856 | getRegister_f getReg; |
---|
| 857 | setRegister_f setReg; |
---|
| 858 | |
---|
| 859 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 860 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 861 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 862 | |
---|
| 863 | /* |
---|
| 864 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
| 865 | */ |
---|
| 866 | |
---|
| 867 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
---|
| 868 | |
---|
| 869 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 870 | /* |
---|
| 871 | * Yield while we wait |
---|
| 872 | */ |
---|
[0eb85ae] | 873 | #if 0 |
---|
[c14a619] | 874 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 875 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 876 | } |
---|
[0eb85ae] | 877 | #endif |
---|
[c14a619] | 878 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 879 | } |
---|
| 880 | |
---|
| 881 | /* |
---|
| 882 | * Write the character. |
---|
| 883 | */ |
---|
| 884 | |
---|
| 885 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar ); |
---|
| 886 | } |
---|