[0737710] | 1 | /* |
---|
| 2 | * This file contains the console driver chip level routines for the |
---|
[e4acf68] | 3 | * Zilog z85c30 chip. |
---|
| 4 | * |
---|
| 5 | * The Zilog Z8530 is also available as: |
---|
| 6 | * |
---|
| 7 | * + Intel 82530 |
---|
| 8 | * + AMD ??? |
---|
[0737710] | 9 | * |
---|
| 10 | * COPYRIGHT (c) 1998 by Radstone Technology |
---|
| 11 | * |
---|
| 12 | * |
---|
| 13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
---|
| 14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
---|
| 15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
---|
| 16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
---|
| 17 | * |
---|
| 18 | * You are hereby granted permission to use, copy, modify, and distribute |
---|
| 19 | * this file, provided that this notice, plus the above copyright notice |
---|
| 20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
---|
| 21 | * no support for this code. |
---|
| 22 | * |
---|
| 23 | * COPYRIGHT (c) 1989-1997. |
---|
| 24 | * On-Line Applications Research Corporation (OAR). |
---|
| 25 | * Copyright assigned to U.S. Government, 1994. |
---|
| 26 | * |
---|
| 27 | * The license and distribution terms for this file may be |
---|
| 28 | * found in the file LICENSE in this distribution or at |
---|
| 29 | * http://www.OARcorp.com/rtems/license.html. |
---|
| 30 | * |
---|
| 31 | * $Id$ |
---|
| 32 | */ |
---|
| 33 | |
---|
| 34 | #include <rtems.h> |
---|
| 35 | #include <rtems/libio.h> |
---|
| 36 | #include <stdlib.h> |
---|
| 37 | |
---|
[ee3b242b] | 38 | #include <libchip/serial.h> |
---|
[0737710] | 39 | #include "z85c30_p.h" |
---|
| 40 | |
---|
| 41 | /* |
---|
| 42 | * Flow control is only supported when using interrupts |
---|
| 43 | */ |
---|
[e4acf68] | 44 | |
---|
[0737710] | 45 | console_flow z85c30_flow_RTSCTS = |
---|
| 46 | { |
---|
| 47 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
---|
| 48 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
---|
| 49 | }; |
---|
| 50 | |
---|
| 51 | console_flow z85c30_flow_DTRCTS = |
---|
| 52 | { |
---|
| 53 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
---|
| 54 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
---|
| 55 | }; |
---|
| 56 | |
---|
| 57 | /* |
---|
| 58 | * Exported driver function table |
---|
| 59 | */ |
---|
[e4acf68] | 60 | |
---|
[0737710] | 61 | console_fns z85c30_fns = |
---|
| 62 | { |
---|
| 63 | z85c30_probe, /* deviceProbe */ |
---|
| 64 | z85c30_open, /* deviceFirstOpen */ |
---|
| 65 | z85c30_flush, /* deviceLastClose */ |
---|
| 66 | NULL, /* deviceRead */ |
---|
| 67 | z85c30_write_support_int, /* deviceWrite */ |
---|
| 68 | z85c30_initialize_interrupts, /* deviceInitialize */ |
---|
| 69 | z85c30_write_polled, /* deviceWritePolled */ |
---|
| 70 | FALSE, /* deviceOutputUsesInterrupts */ |
---|
| 71 | }; |
---|
| 72 | |
---|
| 73 | console_fns z85c30_fns_polled = |
---|
| 74 | { |
---|
| 75 | z85c30_probe, /* deviceProbe */ |
---|
| 76 | z85c30_open, /* deviceFirstOpen */ |
---|
| 77 | z85c30_close, /* deviceLastClose */ |
---|
| 78 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
---|
| 79 | z85c30_write_support_polled, /* deviceWrite */ |
---|
| 80 | z85c30_init, /* deviceInitialize */ |
---|
| 81 | z85c30_write_polled, /* deviceWritePolled */ |
---|
| 82 | FALSE, /* deviceOutputUsesInterrupts */ |
---|
| 83 | }; |
---|
| 84 | |
---|
| 85 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
---|
| 86 | |
---|
| 87 | |
---|
| 88 | |
---|
| 89 | /* |
---|
| 90 | * z85c30_initialize_port |
---|
| 91 | * |
---|
| 92 | * initialize a z85c30 Port |
---|
| 93 | */ |
---|
| 94 | |
---|
| 95 | static void z85c30_initialize_port( |
---|
| 96 | int minor |
---|
| 97 | ) |
---|
| 98 | { |
---|
| 99 | unsigned32 ulCtrlPort; |
---|
| 100 | unsigned32 ulBaudDivisor; |
---|
| 101 | setRegister_f setReg; |
---|
| 102 | |
---|
| 103 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 104 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 105 | |
---|
| 106 | /* |
---|
| 107 | * Using register 4 |
---|
| 108 | * Set up the clock rate is 16 times the data |
---|
| 109 | * rate, 8 bit sync char, 1 stop bit, no parity |
---|
| 110 | */ |
---|
| 111 | |
---|
| 112 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
---|
| 113 | |
---|
| 114 | /* |
---|
| 115 | * Set up for 8 bits/character on receive with |
---|
| 116 | * receiver disable via register 3 |
---|
| 117 | */ |
---|
| 118 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
---|
| 119 | |
---|
| 120 | /* |
---|
| 121 | * Set up for 8 bits/character on transmit |
---|
| 122 | * with transmitter disable via register 5 |
---|
| 123 | */ |
---|
| 124 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
---|
| 125 | |
---|
| 126 | /* |
---|
| 127 | * Clear misc control bits |
---|
| 128 | */ |
---|
| 129 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
---|
| 130 | |
---|
| 131 | /* |
---|
| 132 | * Setup the source of the receive and xmit |
---|
| 133 | * clock as BRG output and the transmit clock |
---|
| 134 | * as the output source for TRxC pin via register 11 |
---|
| 135 | */ |
---|
| 136 | (*setReg)( |
---|
| 137 | ulCtrlPort, |
---|
| 138 | SCC_WR0_SEL_WR11, |
---|
| 139 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
---|
| 140 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
---|
| 141 | ); |
---|
| 142 | |
---|
| 143 | ulBaudDivisor = Z85C30_Baud( |
---|
| 144 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
---|
| 145 | (unsigned32) Console_Port_Tbl[minor].pDeviceParams |
---|
| 146 | ); |
---|
| 147 | |
---|
| 148 | /* |
---|
| 149 | * Setup the lower 8 bits time constants=1E. |
---|
| 150 | * If the time constans=1E, then the desire |
---|
| 151 | * baud rate will be equilvalent to 9600, via register 12. |
---|
| 152 | */ |
---|
| 153 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
---|
| 154 | |
---|
| 155 | /* |
---|
| 156 | * using register 13 |
---|
| 157 | * Setup the upper 8 bits time constant |
---|
| 158 | */ |
---|
| 159 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
---|
| 160 | |
---|
| 161 | /* |
---|
| 162 | * Enable the baud rate generator enable with clock from the |
---|
| 163 | * SCC's PCLK input via register 14. |
---|
| 164 | */ |
---|
| 165 | (*setReg)( |
---|
| 166 | ulCtrlPort, |
---|
| 167 | SCC_WR0_SEL_WR14, |
---|
| 168 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
---|
| 169 | ); |
---|
| 170 | |
---|
| 171 | /* |
---|
| 172 | * We are only interested in CTS state changes |
---|
| 173 | */ |
---|
| 174 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
---|
| 175 | |
---|
| 176 | /* |
---|
| 177 | * Reset errors |
---|
| 178 | */ |
---|
| 179 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
---|
| 180 | |
---|
| 181 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
---|
| 182 | |
---|
| 183 | /* |
---|
| 184 | * Enable the receiver via register 3 |
---|
| 185 | */ |
---|
| 186 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
---|
| 187 | |
---|
| 188 | /* |
---|
| 189 | * Enable the transmitter pins set via register 5. |
---|
| 190 | */ |
---|
| 191 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
---|
| 192 | |
---|
| 193 | /* |
---|
| 194 | * Disable interrupts |
---|
| 195 | */ |
---|
| 196 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
---|
| 197 | |
---|
| 198 | /* |
---|
| 199 | * Reset TX CRC |
---|
| 200 | */ |
---|
| 201 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
---|
| 202 | |
---|
| 203 | /* |
---|
| 204 | * Reset interrupts |
---|
| 205 | */ |
---|
| 206 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
---|
| 207 | } |
---|
| 208 | |
---|
| 209 | static int z85c30_open( |
---|
| 210 | int major, |
---|
| 211 | int minor, |
---|
| 212 | void *arg |
---|
| 213 | ) |
---|
| 214 | { |
---|
| 215 | /* |
---|
| 216 | * Assert DTR |
---|
| 217 | */ |
---|
| 218 | |
---|
| 219 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
---|
| 220 | z85c30_assert_DTR(minor); |
---|
| 221 | } |
---|
| 222 | |
---|
| 223 | return(RTEMS_SUCCESSFUL); |
---|
| 224 | } |
---|
| 225 | |
---|
| 226 | static int z85c30_close( |
---|
| 227 | int major, |
---|
| 228 | int minor, |
---|
| 229 | void *arg |
---|
| 230 | ) |
---|
| 231 | { |
---|
| 232 | /* |
---|
| 233 | * Negate DTR |
---|
| 234 | */ |
---|
| 235 | |
---|
| 236 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
---|
| 237 | z85c30_negate_DTR(minor); |
---|
| 238 | } |
---|
| 239 | |
---|
| 240 | return(RTEMS_SUCCESSFUL); |
---|
| 241 | } |
---|
| 242 | |
---|
| 243 | /* |
---|
| 244 | * z85c30_write_polled |
---|
| 245 | * |
---|
| 246 | * This routine transmits a character using polling. |
---|
| 247 | */ |
---|
| 248 | |
---|
| 249 | static void z85c30_write_polled( |
---|
| 250 | int minor, |
---|
| 251 | char cChar |
---|
| 252 | ) |
---|
| 253 | { |
---|
| 254 | volatile unsigned8 z85c30_status; |
---|
| 255 | unsigned32 ulCtrlPort; |
---|
| 256 | getRegister_f getReg; |
---|
| 257 | setData_f setData; |
---|
| 258 | |
---|
| 259 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 260 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 261 | setData = Console_Port_Tbl[minor].setData; |
---|
| 262 | |
---|
| 263 | /* |
---|
| 264 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
| 265 | */ |
---|
| 266 | |
---|
| 267 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
---|
| 268 | |
---|
| 269 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 270 | /* |
---|
| 271 | * Yield while we wait |
---|
| 272 | */ |
---|
| 273 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 274 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 275 | } |
---|
| 276 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 277 | } |
---|
| 278 | |
---|
| 279 | /* |
---|
| 280 | * Write the character. |
---|
| 281 | */ |
---|
| 282 | |
---|
| 283 | (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); |
---|
| 284 | } |
---|
| 285 | |
---|
| 286 | /* |
---|
| 287 | * Console Device Driver Entry Points |
---|
| 288 | */ |
---|
| 289 | |
---|
| 290 | static boolean z85c30_probe(int minor) |
---|
| 291 | { |
---|
| 292 | /* |
---|
[4cd4c5a] | 293 | * If the configuration dependent probe has located the device then |
---|
[0737710] | 294 | * assume it is there |
---|
| 295 | */ |
---|
| 296 | |
---|
| 297 | return(TRUE); |
---|
| 298 | } |
---|
| 299 | |
---|
| 300 | static void z85c30_init(int minor) |
---|
| 301 | { |
---|
| 302 | unsigned32 ulCtrlPort; |
---|
| 303 | unsigned8 dummy; |
---|
| 304 | z85c30_context *pz85c30Context; |
---|
| 305 | setRegister_f setReg; |
---|
| 306 | getRegister_f getReg; |
---|
| 307 | |
---|
| 308 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 309 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 310 | |
---|
| 311 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
---|
| 312 | |
---|
| 313 | Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; |
---|
| 314 | |
---|
| 315 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
---|
| 316 | |
---|
| 317 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 318 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { |
---|
| 319 | /* |
---|
| 320 | * This is channel A |
---|
| 321 | */ |
---|
| 322 | /* |
---|
| 323 | * Ensure port state machine is reset |
---|
| 324 | */ |
---|
| 325 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 326 | |
---|
| 327 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
---|
| 328 | |
---|
| 329 | } else { |
---|
| 330 | /* |
---|
| 331 | * This is channel B |
---|
| 332 | */ |
---|
| 333 | /* |
---|
| 334 | * Ensure port state machine is reset |
---|
| 335 | */ |
---|
| 336 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 337 | |
---|
| 338 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
---|
| 339 | } |
---|
| 340 | |
---|
| 341 | z85c30_initialize_port(minor); |
---|
| 342 | } |
---|
| 343 | |
---|
| 344 | /* |
---|
| 345 | * These routines provide control of the RTS and DTR lines |
---|
| 346 | */ |
---|
[e4acf68] | 347 | |
---|
[0737710] | 348 | /* |
---|
| 349 | * z85c30_assert_RTS |
---|
| 350 | */ |
---|
[e4acf68] | 351 | |
---|
[0737710] | 352 | static int z85c30_assert_RTS(int minor) |
---|
| 353 | { |
---|
| 354 | rtems_interrupt_level Irql; |
---|
| 355 | z85c30_context *pz85c30Context; |
---|
| 356 | setRegister_f setReg; |
---|
| 357 | |
---|
| 358 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 359 | |
---|
| 360 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
---|
| 361 | |
---|
| 362 | /* |
---|
| 363 | * Assert RTS |
---|
| 364 | */ |
---|
| 365 | |
---|
| 366 | rtems_interrupt_disable(Irql); |
---|
| 367 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
---|
| 368 | (*setReg)( |
---|
| 369 | Console_Port_Tbl[minor].ulCtrlPort1, |
---|
| 370 | SCC_WR0_SEL_WR5, |
---|
| 371 | pz85c30Context->ucModemCtrl |
---|
| 372 | ); |
---|
| 373 | rtems_interrupt_enable(Irql); |
---|
| 374 | return 0; |
---|
| 375 | } |
---|
| 376 | |
---|
| 377 | /* |
---|
| 378 | * z85c30_negate_RTS |
---|
| 379 | */ |
---|
[e4acf68] | 380 | |
---|
[0737710] | 381 | static int z85c30_negate_RTS(int minor) |
---|
| 382 | { |
---|
| 383 | rtems_interrupt_level Irql; |
---|
| 384 | z85c30_context *pz85c30Context; |
---|
| 385 | setRegister_f setReg; |
---|
| 386 | |
---|
| 387 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 388 | |
---|
| 389 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
---|
| 390 | |
---|
| 391 | /* |
---|
| 392 | * Negate RTS |
---|
| 393 | */ |
---|
| 394 | |
---|
| 395 | rtems_interrupt_disable(Irql); |
---|
| 396 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
---|
| 397 | (*setReg)( |
---|
| 398 | Console_Port_Tbl[minor].ulCtrlPort1, |
---|
| 399 | SCC_WR0_SEL_WR5, |
---|
| 400 | pz85c30Context->ucModemCtrl |
---|
| 401 | ); |
---|
| 402 | rtems_interrupt_enable(Irql); |
---|
| 403 | return 0; |
---|
| 404 | } |
---|
| 405 | |
---|
| 406 | /* |
---|
| 407 | * These flow control routines utilise a connection from the local DTR |
---|
| 408 | * line to the remote CTS line |
---|
| 409 | */ |
---|
[e4acf68] | 410 | |
---|
[0737710] | 411 | /* |
---|
| 412 | * z85c30_assert_DTR |
---|
| 413 | */ |
---|
[e4acf68] | 414 | |
---|
[0737710] | 415 | static int z85c30_assert_DTR(int minor) |
---|
| 416 | { |
---|
| 417 | rtems_interrupt_level Irql; |
---|
| 418 | z85c30_context *pz85c30Context; |
---|
| 419 | setRegister_f setReg; |
---|
| 420 | |
---|
| 421 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 422 | |
---|
| 423 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
---|
| 424 | |
---|
| 425 | /* |
---|
| 426 | * Assert DTR |
---|
| 427 | */ |
---|
| 428 | |
---|
| 429 | rtems_interrupt_disable(Irql); |
---|
| 430 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
---|
| 431 | (*setReg)( |
---|
| 432 | Console_Port_Tbl[minor].ulCtrlPort1, |
---|
| 433 | SCC_WR0_SEL_WR5, |
---|
| 434 | pz85c30Context->ucModemCtrl |
---|
| 435 | ); |
---|
| 436 | rtems_interrupt_enable(Irql); |
---|
| 437 | return 0; |
---|
| 438 | } |
---|
| 439 | |
---|
| 440 | /* |
---|
| 441 | * z85c30_negate_DTR |
---|
| 442 | */ |
---|
[e4acf68] | 443 | |
---|
[0737710] | 444 | static int z85c30_negate_DTR(int minor) |
---|
| 445 | { |
---|
| 446 | rtems_interrupt_level Irql; |
---|
| 447 | z85c30_context *pz85c30Context; |
---|
| 448 | setRegister_f setReg; |
---|
| 449 | |
---|
| 450 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 451 | |
---|
| 452 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
---|
| 453 | |
---|
| 454 | /* |
---|
| 455 | * Negate DTR |
---|
| 456 | */ |
---|
| 457 | |
---|
| 458 | rtems_interrupt_disable(Irql); |
---|
| 459 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
---|
| 460 | (*setReg)( |
---|
| 461 | Console_Port_Tbl[minor].ulCtrlPort1, |
---|
| 462 | SCC_WR0_SEL_WR5, |
---|
| 463 | pz85c30Context->ucModemCtrl |
---|
| 464 | ); |
---|
| 465 | rtems_interrupt_enable(Irql); |
---|
| 466 | return 0; |
---|
| 467 | } |
---|
| 468 | |
---|
| 469 | /* |
---|
| 470 | * z85c30_isr |
---|
| 471 | * |
---|
| 472 | * This routine is the console interrupt handler for COM3 and COM4 |
---|
| 473 | * |
---|
| 474 | * Input parameters: |
---|
| 475 | * vector - vector number |
---|
| 476 | * |
---|
| 477 | * Output parameters: NONE |
---|
| 478 | * |
---|
| 479 | * Return values: NONE |
---|
| 480 | */ |
---|
| 481 | |
---|
| 482 | static void z85c30_process( |
---|
| 483 | int minor, |
---|
| 484 | unsigned8 ucIntPend |
---|
| 485 | ) |
---|
| 486 | { |
---|
| 487 | unsigned32 ulCtrlPort; |
---|
| 488 | unsigned32 ulDataPort; |
---|
| 489 | volatile unsigned8 z85c30_status; |
---|
| 490 | char cChar; |
---|
| 491 | setRegister_f setReg; |
---|
| 492 | getRegister_f getReg; |
---|
| 493 | getData_f getData; |
---|
| 494 | setData_f setData; |
---|
| 495 | |
---|
| 496 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 497 | ulDataPort = Console_Port_Tbl[minor].ulDataPort; |
---|
| 498 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 499 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 500 | getData = Console_Port_Tbl[minor].getData; |
---|
[4cd4c5a] | 501 | setData = Console_Port_Tbl[minor].setData; |
---|
[0737710] | 502 | |
---|
| 503 | /* |
---|
| 504 | * Deal with any received characters |
---|
| 505 | */ |
---|
| 506 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
| 507 | { |
---|
| 508 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 509 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 510 | break; |
---|
| 511 | } |
---|
| 512 | |
---|
| 513 | /* |
---|
| 514 | * Return the character read. |
---|
| 515 | */ |
---|
| 516 | |
---|
| 517 | cChar = (*getData)(ulDataPort); |
---|
| 518 | |
---|
| 519 | rtems_termios_enqueue_raw_characters( |
---|
| 520 | Console_Port_Data[minor].termios_data, |
---|
| 521 | &cChar, |
---|
| 522 | 1 |
---|
| 523 | ); |
---|
| 524 | } |
---|
| 525 | |
---|
| 526 | while (TRUE) |
---|
| 527 | { |
---|
| 528 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 529 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 530 | /* |
---|
| 531 | * We'll get another interrupt when |
---|
| 532 | * the transmitter holding reg. becomes |
---|
| 533 | * free again and we are clear to send |
---|
| 534 | */ |
---|
| 535 | break; |
---|
| 536 | } |
---|
| 537 | |
---|
| 538 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
| 539 | /* |
---|
| 540 | * We can't transmit yet |
---|
| 541 | */ |
---|
| 542 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 543 | /* |
---|
| 544 | * The next state change of CTS will wake us up |
---|
| 545 | */ |
---|
| 546 | break; |
---|
| 547 | } |
---|
| 548 | |
---|
| 549 | if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 550 | Console_Port_Data[minor].bActive=FALSE; |
---|
| 551 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 552 | z85c30_negate_RTS(minor); |
---|
| 553 | } |
---|
| 554 | /* |
---|
| 555 | * There is no data to transmit |
---|
| 556 | */ |
---|
| 557 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 558 | break; |
---|
| 559 | } |
---|
| 560 | |
---|
| 561 | Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); |
---|
| 562 | |
---|
| 563 | /* |
---|
| 564 | * transmit character |
---|
| 565 | */ |
---|
| 566 | (*setData)(ulDataPort, cChar); |
---|
| 567 | |
---|
| 568 | /* |
---|
| 569 | * Interrupt once FIFO has room |
---|
| 570 | */ |
---|
| 571 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 572 | break; |
---|
| 573 | } |
---|
| 574 | |
---|
| 575 | if (ucIntPend&SCC_RR3_B_EXT_IP) { |
---|
| 576 | /* |
---|
| 577 | * Clear the external status interrupt |
---|
| 578 | */ |
---|
| 579 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
| 580 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 581 | } |
---|
| 582 | |
---|
| 583 | /* |
---|
| 584 | * Reset interrupts |
---|
| 585 | */ |
---|
| 586 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
| 587 | } |
---|
| 588 | |
---|
| 589 | static rtems_isr z85c30_isr( |
---|
| 590 | rtems_vector_number vector |
---|
| 591 | ) |
---|
| 592 | { |
---|
| 593 | int minor; |
---|
| 594 | unsigned32 ulCtrlPort; |
---|
| 595 | volatile unsigned8 ucIntPend; |
---|
| 596 | volatile unsigned8 ucIntPendPort; |
---|
| 597 | getRegister_f getReg; |
---|
| 598 | |
---|
| 599 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
| 600 | if (vector==Console_Port_Tbl[minor].ulIntVector) { |
---|
| 601 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 602 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 603 | do { |
---|
| 604 | ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
| 605 | |
---|
| 606 | /* |
---|
| 607 | * If this is channel A select channel A status |
---|
| 608 | */ |
---|
| 609 | |
---|
| 610 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
| 611 | ucIntPendPort = ucIntPend>>3; |
---|
| 612 | ucIntPendPort = ucIntPendPort&=7; |
---|
| 613 | } else { |
---|
| 614 | ucIntPendPort = ucIntPend &= 7; |
---|
| 615 | } |
---|
| 616 | |
---|
| 617 | if (ucIntPendPort) { |
---|
| 618 | z85c30_process(minor, ucIntPendPort); |
---|
| 619 | } |
---|
| 620 | } while (ucIntPendPort); |
---|
| 621 | } |
---|
| 622 | } |
---|
| 623 | } |
---|
| 624 | |
---|
| 625 | /* |
---|
| 626 | * z85c30_flush |
---|
| 627 | */ |
---|
| 628 | |
---|
| 629 | static int z85c30_flush( |
---|
| 630 | int major, |
---|
| 631 | int minor, |
---|
| 632 | void *arg |
---|
| 633 | ) |
---|
| 634 | { |
---|
| 635 | while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 636 | /* |
---|
| 637 | * Yield while we wait |
---|
| 638 | */ |
---|
| 639 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 640 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 641 | } |
---|
| 642 | } |
---|
| 643 | |
---|
| 644 | z85c30_close(major, minor, arg); |
---|
| 645 | |
---|
| 646 | return(RTEMS_SUCCESSFUL); |
---|
| 647 | } |
---|
| 648 | |
---|
| 649 | /* |
---|
| 650 | * z85c30_initialize_interrupts |
---|
| 651 | * |
---|
| 652 | * This routine initializes the console's receive and transmit |
---|
| 653 | * ring buffers and loads the appropriate vectors to handle the interrupts. |
---|
| 654 | * |
---|
| 655 | * Input parameters: NONE |
---|
| 656 | * |
---|
| 657 | * Output parameters: NONE |
---|
| 658 | * |
---|
| 659 | * Return values: NONE |
---|
| 660 | */ |
---|
| 661 | |
---|
| 662 | static void z85c30_enable_interrupts( |
---|
| 663 | int minor |
---|
| 664 | ) |
---|
| 665 | { |
---|
| 666 | unsigned32 ulCtrlPort; |
---|
| 667 | setRegister_f setReg; |
---|
| 668 | |
---|
| 669 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 670 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 671 | |
---|
| 672 | /* |
---|
| 673 | * Enable interrupts |
---|
| 674 | */ |
---|
| 675 | (*setReg)( |
---|
| 676 | ulCtrlPort, |
---|
| 677 | SCC_WR0_SEL_WR1, |
---|
| 678 | SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX |
---|
| 679 | ); |
---|
| 680 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); |
---|
| 681 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
| 682 | |
---|
| 683 | /* |
---|
| 684 | * Reset interrupts |
---|
| 685 | */ |
---|
| 686 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
| 687 | } |
---|
| 688 | |
---|
| 689 | static void z85c30_initialize_interrupts( |
---|
| 690 | int minor |
---|
| 691 | ) |
---|
| 692 | { |
---|
| 693 | z85c30_init(minor); |
---|
| 694 | |
---|
| 695 | Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); |
---|
| 696 | |
---|
| 697 | Console_Port_Data[minor].bActive=FALSE; |
---|
| 698 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 699 | z85c30_negate_RTS(minor); |
---|
| 700 | } |
---|
| 701 | |
---|
| 702 | if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { |
---|
| 703 | /* |
---|
| 704 | * Only do this for Channel A |
---|
| 705 | */ |
---|
| 706 | |
---|
| 707 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
| 708 | } |
---|
| 709 | |
---|
| 710 | z85c30_enable_interrupts(minor); |
---|
| 711 | } |
---|
| 712 | |
---|
| 713 | /* |
---|
| 714 | * z85c30_write_support_int |
---|
| 715 | * |
---|
| 716 | * Console Termios output entry point. |
---|
| 717 | * |
---|
| 718 | */ |
---|
[e4acf68] | 719 | |
---|
[0737710] | 720 | static int z85c30_write_support_int( |
---|
| 721 | int minor, |
---|
| 722 | const char *buf, |
---|
| 723 | int len) |
---|
| 724 | { |
---|
| 725 | int i; |
---|
| 726 | unsigned32 Irql; |
---|
| 727 | |
---|
| 728 | for (i=0; i<len;) { |
---|
| 729 | if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 730 | if (!Console_Port_Data[minor].bActive) { |
---|
| 731 | /* |
---|
| 732 | * Wake up the device |
---|
| 733 | */ |
---|
| 734 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 735 | z85c30_assert_RTS(minor); |
---|
| 736 | } |
---|
| 737 | rtems_interrupt_disable(Irql); |
---|
| 738 | Console_Port_Data[minor].bActive=TRUE; |
---|
| 739 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
| 740 | rtems_interrupt_enable(Irql); |
---|
| 741 | } else { |
---|
| 742 | /* |
---|
| 743 | * Yield while we await an interrupt |
---|
| 744 | */ |
---|
| 745 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 746 | } |
---|
| 747 | |
---|
| 748 | /* |
---|
| 749 | * Wait for ring buffer to empty |
---|
| 750 | */ |
---|
| 751 | continue; |
---|
| 752 | } else { |
---|
| 753 | Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); |
---|
| 754 | i++; |
---|
| 755 | } |
---|
| 756 | } |
---|
| 757 | |
---|
| 758 | /* |
---|
| 759 | * Ensure that characters are on the way |
---|
| 760 | */ |
---|
| 761 | if (!Console_Port_Data[minor].bActive) { |
---|
| 762 | /* |
---|
| 763 | * Wake up the device |
---|
| 764 | */ |
---|
| 765 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 766 | z85c30_assert_RTS(minor); |
---|
| 767 | } |
---|
| 768 | rtems_interrupt_disable(Irql); |
---|
| 769 | Console_Port_Data[minor].bActive=TRUE; |
---|
| 770 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
| 771 | rtems_interrupt_enable(Irql); |
---|
| 772 | } |
---|
| 773 | |
---|
| 774 | return (len); |
---|
| 775 | } |
---|
| 776 | |
---|
| 777 | /* |
---|
| 778 | * z85c30_inbyte_nonblocking_polled |
---|
| 779 | * |
---|
| 780 | * This routine polls for a character. |
---|
| 781 | */ |
---|
[e4acf68] | 782 | |
---|
[0737710] | 783 | static int z85c30_inbyte_nonblocking_polled( |
---|
| 784 | int minor |
---|
| 785 | ) |
---|
| 786 | { |
---|
| 787 | volatile unsigned8 z85c30_status; |
---|
| 788 | unsigned32 ulCtrlPort; |
---|
| 789 | getRegister_f getReg; |
---|
| 790 | getData_f getData; |
---|
| 791 | |
---|
| 792 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 793 | getData = Console_Port_Tbl[minor].getData; |
---|
| 794 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 795 | |
---|
| 796 | /* |
---|
| 797 | * return -1 if a character is not available. |
---|
| 798 | */ |
---|
| 799 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 800 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 801 | return -1; |
---|
| 802 | } |
---|
| 803 | |
---|
| 804 | /* |
---|
| 805 | * Return the character read. |
---|
| 806 | */ |
---|
| 807 | return (*getData)(Console_Port_Tbl[minor].ulDataPort); |
---|
| 808 | } |
---|
| 809 | |
---|
| 810 | /* |
---|
| 811 | * z85c30_write_support_polled |
---|
| 812 | * |
---|
| 813 | * Console Termios output entry point. |
---|
| 814 | * |
---|
| 815 | */ |
---|
| 816 | |
---|
| 817 | static int z85c30_write_support_polled( |
---|
| 818 | int minor, |
---|
| 819 | const char *buf, |
---|
| 820 | int len) |
---|
| 821 | { |
---|
| 822 | int nwrite=0; |
---|
| 823 | |
---|
| 824 | /* |
---|
| 825 | * poll each byte in the string out of the port. |
---|
| 826 | */ |
---|
| 827 | while (nwrite < len) { |
---|
| 828 | z85c30_write_polled(minor, *buf++); |
---|
| 829 | nwrite++; |
---|
| 830 | } |
---|
| 831 | |
---|
| 832 | /* |
---|
| 833 | * return the number of bytes written. |
---|
| 834 | */ |
---|
| 835 | return nwrite; |
---|
| 836 | } |
---|