[0737710] | 1 | /* |
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| 2 | * This file contains the console driver chip level routines for the |
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| 3 | * z85c30 chip. |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 6 | * |
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| 7 | * |
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| 8 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 9 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 10 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 11 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 12 | * |
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| 13 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 14 | * this file, provided that this notice, plus the above copyright notice |
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| 15 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 16 | * no support for this code. |
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| 17 | * |
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| 18 | * COPYRIGHT (c) 1989-1997. |
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| 19 | * On-Line Applications Research Corporation (OAR). |
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| 20 | * Copyright assigned to U.S. Government, 1994. |
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| 21 | * |
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| 22 | * The license and distribution terms for this file may be |
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| 23 | * found in the file LICENSE in this distribution or at |
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| 24 | * http://www.OARcorp.com/rtems/license.html. |
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| 25 | * |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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| 29 | #include <rtems.h> |
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| 30 | #include <rtems/libio.h> |
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| 31 | #include <stdlib.h> |
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| 32 | |
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| 33 | #include "console.h" |
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| 34 | #include "z85c30_p.h" |
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| 35 | |
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| 36 | /* |
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| 37 | * Flow control is only supported when using interrupts |
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| 38 | */ |
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| 39 | console_flow z85c30_flow_RTSCTS = |
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| 40 | { |
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| 41 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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| 42 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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| 43 | }; |
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| 44 | |
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| 45 | console_flow z85c30_flow_DTRCTS = |
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| 46 | { |
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| 47 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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| 48 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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| 49 | }; |
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| 50 | |
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| 51 | /* |
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| 52 | * Exported driver function table |
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| 53 | */ |
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| 54 | console_fns z85c30_fns = |
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| 55 | { |
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| 56 | z85c30_probe, /* deviceProbe */ |
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| 57 | z85c30_open, /* deviceFirstOpen */ |
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| 58 | z85c30_flush, /* deviceLastClose */ |
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| 59 | NULL, /* deviceRead */ |
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| 60 | z85c30_write_support_int, /* deviceWrite */ |
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| 61 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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| 62 | z85c30_write_polled, /* deviceWritePolled */ |
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| 63 | FALSE, /* deviceOutputUsesInterrupts */ |
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| 64 | }; |
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| 65 | |
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| 66 | console_fns z85c30_fns_polled = |
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| 67 | { |
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| 68 | z85c30_probe, /* deviceProbe */ |
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| 69 | z85c30_open, /* deviceFirstOpen */ |
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| 70 | z85c30_close, /* deviceLastClose */ |
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| 71 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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| 72 | z85c30_write_support_polled, /* deviceWrite */ |
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| 73 | z85c30_init, /* deviceInitialize */ |
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| 74 | z85c30_write_polled, /* deviceWritePolled */ |
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| 75 | FALSE, /* deviceOutputUsesInterrupts */ |
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| 76 | }; |
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| 77 | |
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| 78 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 79 | |
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| 80 | /* |
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| 81 | * Types for get and set register routines |
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| 82 | */ |
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| 83 | |
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| 84 | typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register); |
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| 85 | typedef void (*setRegister_f)( |
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| 86 | unsigned32 port, unsigned8 reg, unsigned8 value); |
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| 87 | typedef unsigned8 (*getData_f)(unsigned32 port); |
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| 88 | typedef void (*setData_f)(unsigned32 port, unsigned8 value); |
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| 89 | |
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| 90 | |
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| 91 | /* |
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| 92 | * z85c30_initialize_port |
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| 93 | * |
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| 94 | * initialize a z85c30 Port |
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| 95 | */ |
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| 96 | |
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| 97 | static void z85c30_initialize_port( |
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| 98 | int minor |
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| 99 | ) |
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| 100 | { |
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| 101 | unsigned32 ulCtrlPort; |
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| 102 | unsigned32 ulBaudDivisor; |
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| 103 | setRegister_f setReg; |
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| 104 | |
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| 105 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 106 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 107 | |
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| 108 | /* |
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| 109 | * Using register 4 |
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| 110 | * Set up the clock rate is 16 times the data |
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| 111 | * rate, 8 bit sync char, 1 stop bit, no parity |
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| 112 | */ |
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| 113 | |
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| 114 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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| 115 | |
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| 116 | /* |
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| 117 | * Set up for 8 bits/character on receive with |
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| 118 | * receiver disable via register 3 |
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| 119 | */ |
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| 120 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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| 121 | |
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| 122 | /* |
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| 123 | * Set up for 8 bits/character on transmit |
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| 124 | * with transmitter disable via register 5 |
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| 125 | */ |
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| 126 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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| 127 | |
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| 128 | /* |
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| 129 | * Clear misc control bits |
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| 130 | */ |
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| 131 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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| 132 | |
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| 133 | /* |
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| 134 | * Setup the source of the receive and xmit |
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| 135 | * clock as BRG output and the transmit clock |
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| 136 | * as the output source for TRxC pin via register 11 |
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| 137 | */ |
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| 138 | (*setReg)( |
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| 139 | ulCtrlPort, |
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| 140 | SCC_WR0_SEL_WR11, |
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| 141 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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| 142 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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| 143 | ); |
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| 144 | |
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| 145 | ulBaudDivisor = Z85C30_Baud( |
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| 146 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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| 147 | (unsigned32) Console_Port_Tbl[minor].pDeviceParams |
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| 148 | ); |
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| 149 | |
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| 150 | /* |
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| 151 | * Setup the lower 8 bits time constants=1E. |
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| 152 | * If the time constans=1E, then the desire |
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| 153 | * baud rate will be equilvalent to 9600, via register 12. |
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| 154 | */ |
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| 155 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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| 156 | |
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| 157 | /* |
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| 158 | * using register 13 |
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| 159 | * Setup the upper 8 bits time constant |
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| 160 | */ |
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| 161 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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| 162 | |
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| 163 | /* |
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| 164 | * Enable the baud rate generator enable with clock from the |
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| 165 | * SCC's PCLK input via register 14. |
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| 166 | */ |
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| 167 | (*setReg)( |
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| 168 | ulCtrlPort, |
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| 169 | SCC_WR0_SEL_WR14, |
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| 170 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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| 171 | ); |
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| 172 | |
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| 173 | /* |
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| 174 | * We are only interested in CTS state changes |
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| 175 | */ |
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| 176 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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| 177 | |
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| 178 | /* |
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| 179 | * Reset errors |
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| 180 | */ |
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| 181 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 182 | |
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| 183 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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| 184 | |
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| 185 | /* |
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| 186 | * Enable the receiver via register 3 |
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| 187 | */ |
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| 188 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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| 189 | |
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| 190 | /* |
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| 191 | * Enable the transmitter pins set via register 5. |
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| 192 | */ |
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| 193 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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| 194 | |
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| 195 | /* |
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| 196 | * Disable interrupts |
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| 197 | */ |
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| 198 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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| 199 | |
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| 200 | /* |
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| 201 | * Reset TX CRC |
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| 202 | */ |
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| 203 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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| 204 | |
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| 205 | /* |
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| 206 | * Reset interrupts |
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| 207 | */ |
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| 208 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 209 | } |
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| 210 | |
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| 211 | static int z85c30_open( |
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| 212 | int major, |
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| 213 | int minor, |
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| 214 | void *arg |
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| 215 | ) |
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| 216 | { |
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| 217 | /* |
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| 218 | * Assert DTR |
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| 219 | */ |
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| 220 | |
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| 221 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 222 | z85c30_assert_DTR(minor); |
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| 223 | } |
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| 224 | |
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| 225 | return(RTEMS_SUCCESSFUL); |
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| 226 | } |
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| 227 | |
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| 228 | static int z85c30_close( |
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| 229 | int major, |
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| 230 | int minor, |
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| 231 | void *arg |
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| 232 | ) |
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| 233 | { |
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| 234 | /* |
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| 235 | * Negate DTR |
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| 236 | */ |
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| 237 | |
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| 238 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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| 239 | z85c30_negate_DTR(minor); |
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| 240 | } |
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| 241 | |
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| 242 | return(RTEMS_SUCCESSFUL); |
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| 243 | } |
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| 244 | |
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| 245 | /* |
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| 246 | * z85c30_write_polled |
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| 247 | * |
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| 248 | * This routine transmits a character using polling. |
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| 249 | */ |
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| 250 | |
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| 251 | static void z85c30_write_polled( |
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| 252 | int minor, |
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| 253 | char cChar |
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| 254 | ) |
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| 255 | { |
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| 256 | volatile unsigned8 z85c30_status; |
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| 257 | unsigned32 ulCtrlPort; |
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| 258 | getRegister_f getReg; |
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| 259 | setData_f setData; |
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| 260 | |
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| 261 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 262 | getReg = Console_Port_Tbl[minor].getRegister; |
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| 263 | setData = Console_Port_Tbl[minor].setData; |
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| 264 | |
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| 265 | /* |
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| 266 | * Wait for the Transmit buffer to indicate that it is empty. |
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| 267 | */ |
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| 268 | |
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| 269 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
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| 270 | |
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| 271 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
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| 272 | /* |
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| 273 | * Yield while we wait |
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| 274 | */ |
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| 275 | if (_System_state_Is_up(_System_state_Get())) { |
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| 276 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
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| 277 | } |
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| 278 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 279 | } |
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| 280 | |
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| 281 | /* |
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| 282 | * Write the character. |
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| 283 | */ |
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| 284 | |
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| 285 | (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); |
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| 286 | } |
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| 287 | |
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| 288 | /* |
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| 289 | * Console Device Driver Entry Points |
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| 290 | */ |
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| 291 | |
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| 292 | static boolean z85c30_probe(int minor) |
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| 293 | { |
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| 294 | /* |
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| 295 | * If the configuration dependant probe has located the device then |
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| 296 | * assume it is there |
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| 297 | */ |
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| 298 | |
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| 299 | return(TRUE); |
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| 300 | } |
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| 301 | |
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| 302 | static void z85c30_init(int minor) |
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| 303 | { |
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| 304 | unsigned32 ulCtrlPort; |
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| 305 | unsigned8 dummy; |
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| 306 | z85c30_context *pz85c30Context; |
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| 307 | setRegister_f setReg; |
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| 308 | getRegister_f getReg; |
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| 309 | |
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| 310 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 311 | getReg = Console_Port_Tbl[minor].getRegister; |
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| 312 | |
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| 313 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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| 314 | |
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| 315 | Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; |
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| 316 | |
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| 317 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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| 318 | |
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| 319 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 320 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { |
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| 321 | /* |
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| 322 | * This is channel A |
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| 323 | */ |
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| 324 | /* |
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| 325 | * Ensure port state machine is reset |
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| 326 | */ |
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| 327 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 328 | |
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| 329 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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| 330 | |
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| 331 | } else { |
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| 332 | /* |
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| 333 | * This is channel B |
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| 334 | */ |
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| 335 | /* |
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| 336 | * Ensure port state machine is reset |
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| 337 | */ |
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| 338 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 339 | |
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| 340 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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| 341 | } |
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| 342 | |
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| 343 | z85c30_initialize_port(minor); |
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| 344 | } |
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| 345 | |
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| 346 | /* |
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| 347 | * These routines provide control of the RTS and DTR lines |
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| 348 | */ |
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| 349 | /* |
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| 350 | * z85c30_assert_RTS |
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| 351 | */ |
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| 352 | static int z85c30_assert_RTS(int minor) |
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| 353 | { |
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| 354 | rtems_interrupt_level Irql; |
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| 355 | z85c30_context *pz85c30Context; |
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| 356 | setRegister_f setReg; |
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| 357 | |
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| 358 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 359 | |
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| 360 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 361 | |
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| 362 | /* |
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| 363 | * Assert RTS |
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| 364 | */ |
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| 365 | |
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| 366 | rtems_interrupt_disable(Irql); |
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| 367 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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| 368 | (*setReg)( |
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| 369 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 370 | SCC_WR0_SEL_WR5, |
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| 371 | pz85c30Context->ucModemCtrl |
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| 372 | ); |
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| 373 | rtems_interrupt_enable(Irql); |
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| 374 | return 0; |
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| 375 | } |
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| 376 | |
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| 377 | /* |
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| 378 | * z85c30_negate_RTS |
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| 379 | */ |
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| 380 | static int z85c30_negate_RTS(int minor) |
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| 381 | { |
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| 382 | rtems_interrupt_level Irql; |
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| 383 | z85c30_context *pz85c30Context; |
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| 384 | setRegister_f setReg; |
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| 385 | |
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| 386 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 387 | |
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| 388 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 389 | |
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| 390 | /* |
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| 391 | * Negate RTS |
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| 392 | */ |
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| 393 | |
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| 394 | rtems_interrupt_disable(Irql); |
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| 395 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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| 396 | (*setReg)( |
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| 397 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 398 | SCC_WR0_SEL_WR5, |
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| 399 | pz85c30Context->ucModemCtrl |
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| 400 | ); |
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| 401 | rtems_interrupt_enable(Irql); |
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| 402 | return 0; |
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| 403 | } |
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| 404 | |
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| 405 | /* |
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| 406 | * These flow control routines utilise a connection from the local DTR |
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| 407 | * line to the remote CTS line |
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| 408 | */ |
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| 409 | /* |
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| 410 | * z85c30_assert_DTR |
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| 411 | */ |
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| 412 | static int z85c30_assert_DTR(int minor) |
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| 413 | { |
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| 414 | rtems_interrupt_level Irql; |
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| 415 | z85c30_context *pz85c30Context; |
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| 416 | setRegister_f setReg; |
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| 417 | |
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| 418 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 419 | |
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| 420 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 421 | |
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| 422 | /* |
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| 423 | * Assert DTR |
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| 424 | */ |
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| 425 | |
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| 426 | rtems_interrupt_disable(Irql); |
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| 427 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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| 428 | (*setReg)( |
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| 429 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 430 | SCC_WR0_SEL_WR5, |
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| 431 | pz85c30Context->ucModemCtrl |
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| 432 | ); |
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| 433 | rtems_interrupt_enable(Irql); |
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| 434 | return 0; |
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| 435 | } |
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| 436 | |
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| 437 | /* |
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| 438 | * z85c30_negate_DTR |
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| 439 | */ |
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| 440 | static int z85c30_negate_DTR(int minor) |
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| 441 | { |
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| 442 | rtems_interrupt_level Irql; |
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| 443 | z85c30_context *pz85c30Context; |
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| 444 | setRegister_f setReg; |
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| 445 | |
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| 446 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 447 | |
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| 448 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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| 449 | |
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| 450 | /* |
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| 451 | * Negate DTR |
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| 452 | */ |
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| 453 | |
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| 454 | rtems_interrupt_disable(Irql); |
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| 455 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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| 456 | (*setReg)( |
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| 457 | Console_Port_Tbl[minor].ulCtrlPort1, |
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| 458 | SCC_WR0_SEL_WR5, |
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| 459 | pz85c30Context->ucModemCtrl |
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| 460 | ); |
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| 461 | rtems_interrupt_enable(Irql); |
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| 462 | return 0; |
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| 463 | } |
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| 464 | |
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| 465 | /* |
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| 466 | * z85c30_isr |
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| 467 | * |
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| 468 | * This routine is the console interrupt handler for COM3 and COM4 |
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| 469 | * |
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| 470 | * Input parameters: |
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| 471 | * vector - vector number |
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| 472 | * |
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| 473 | * Output parameters: NONE |
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| 474 | * |
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| 475 | * Return values: NONE |
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| 476 | */ |
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| 477 | |
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| 478 | static void z85c30_process( |
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| 479 | int minor, |
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| 480 | unsigned8 ucIntPend |
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| 481 | ) |
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| 482 | { |
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| 483 | unsigned32 ulCtrlPort; |
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| 484 | unsigned32 ulDataPort; |
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| 485 | volatile unsigned8 z85c30_status; |
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| 486 | char cChar; |
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| 487 | setRegister_f setReg; |
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| 488 | getRegister_f getReg; |
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| 489 | getData_f getData; |
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| 490 | setData_f setData; |
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| 491 | |
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| 492 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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| 493 | ulDataPort = Console_Port_Tbl[minor].ulDataPort; |
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| 494 | setReg = Console_Port_Tbl[minor].setRegister; |
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| 495 | getReg = Console_Port_Tbl[minor].getRegister; |
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| 496 | getData = Console_Port_Tbl[minor].getData; |
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| 497 | getData = Console_Port_Tbl[minor].getData; |
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| 498 | |
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| 499 | /* |
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| 500 | * Deal with any received characters |
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| 501 | */ |
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| 502 | while (ucIntPend&SCC_RR3_B_RX_IP) |
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| 503 | { |
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| 504 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 505 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
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| 506 | break; |
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| 507 | } |
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| 508 | |
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| 509 | /* |
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| 510 | * Return the character read. |
---|
| 511 | */ |
---|
| 512 | |
---|
| 513 | cChar = (*getData)(ulDataPort); |
---|
| 514 | |
---|
| 515 | rtems_termios_enqueue_raw_characters( |
---|
| 516 | Console_Port_Data[minor].termios_data, |
---|
| 517 | &cChar, |
---|
| 518 | 1 |
---|
| 519 | ); |
---|
| 520 | } |
---|
| 521 | |
---|
| 522 | while (TRUE) |
---|
| 523 | { |
---|
| 524 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 525 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 526 | /* |
---|
| 527 | * We'll get another interrupt when |
---|
| 528 | * the transmitter holding reg. becomes |
---|
| 529 | * free again and we are clear to send |
---|
| 530 | */ |
---|
| 531 | break; |
---|
| 532 | } |
---|
| 533 | |
---|
| 534 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
| 535 | /* |
---|
| 536 | * We can't transmit yet |
---|
| 537 | */ |
---|
| 538 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 539 | /* |
---|
| 540 | * The next state change of CTS will wake us up |
---|
| 541 | */ |
---|
| 542 | break; |
---|
| 543 | } |
---|
| 544 | |
---|
| 545 | if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 546 | Console_Port_Data[minor].bActive=FALSE; |
---|
| 547 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 548 | z85c30_negate_RTS(minor); |
---|
| 549 | } |
---|
| 550 | /* |
---|
| 551 | * There is no data to transmit |
---|
| 552 | */ |
---|
| 553 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 554 | break; |
---|
| 555 | } |
---|
| 556 | |
---|
| 557 | Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); |
---|
| 558 | |
---|
| 559 | /* |
---|
| 560 | * transmit character |
---|
| 561 | */ |
---|
| 562 | (*setData)(ulDataPort, cChar); |
---|
| 563 | |
---|
| 564 | /* |
---|
| 565 | * Interrupt once FIFO has room |
---|
| 566 | */ |
---|
| 567 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 568 | break; |
---|
| 569 | } |
---|
| 570 | |
---|
| 571 | if (ucIntPend&SCC_RR3_B_EXT_IP) { |
---|
| 572 | /* |
---|
| 573 | * Clear the external status interrupt |
---|
| 574 | */ |
---|
| 575 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
| 576 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 577 | } |
---|
| 578 | |
---|
| 579 | /* |
---|
| 580 | * Reset interrupts |
---|
| 581 | */ |
---|
| 582 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
| 583 | } |
---|
| 584 | |
---|
| 585 | static rtems_isr z85c30_isr( |
---|
| 586 | rtems_vector_number vector |
---|
| 587 | ) |
---|
| 588 | { |
---|
| 589 | int minor; |
---|
| 590 | unsigned32 ulCtrlPort; |
---|
| 591 | volatile unsigned8 ucIntPend; |
---|
| 592 | volatile unsigned8 ucIntPendPort; |
---|
| 593 | getRegister_f getReg; |
---|
| 594 | |
---|
| 595 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
| 596 | if (vector==Console_Port_Tbl[minor].ulIntVector) { |
---|
| 597 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
| 598 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 599 | do { |
---|
| 600 | ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
| 601 | |
---|
| 602 | /* |
---|
| 603 | * If this is channel A select channel A status |
---|
| 604 | */ |
---|
| 605 | |
---|
| 606 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
| 607 | ucIntPendPort = ucIntPend>>3; |
---|
| 608 | ucIntPendPort = ucIntPendPort&=7; |
---|
| 609 | } else { |
---|
| 610 | ucIntPendPort = ucIntPend &= 7; |
---|
| 611 | } |
---|
| 612 | |
---|
| 613 | if (ucIntPendPort) { |
---|
| 614 | z85c30_process(minor, ucIntPendPort); |
---|
| 615 | } |
---|
| 616 | } while (ucIntPendPort); |
---|
| 617 | } |
---|
| 618 | } |
---|
| 619 | } |
---|
| 620 | |
---|
| 621 | /* |
---|
| 622 | * z85c30_flush |
---|
| 623 | */ |
---|
| 624 | |
---|
| 625 | static int z85c30_flush( |
---|
| 626 | int major, |
---|
| 627 | int minor, |
---|
| 628 | void *arg |
---|
| 629 | ) |
---|
| 630 | { |
---|
| 631 | while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 632 | /* |
---|
| 633 | * Yield while we wait |
---|
| 634 | */ |
---|
| 635 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 636 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 637 | } |
---|
| 638 | } |
---|
| 639 | |
---|
| 640 | z85c30_close(major, minor, arg); |
---|
| 641 | |
---|
| 642 | return(RTEMS_SUCCESSFUL); |
---|
| 643 | } |
---|
| 644 | |
---|
| 645 | /* |
---|
| 646 | * z85c30_initialize_interrupts |
---|
| 647 | * |
---|
| 648 | * This routine initializes the console's receive and transmit |
---|
| 649 | * ring buffers and loads the appropriate vectors to handle the interrupts. |
---|
| 650 | * |
---|
| 651 | * Input parameters: NONE |
---|
| 652 | * |
---|
| 653 | * Output parameters: NONE |
---|
| 654 | * |
---|
| 655 | * Return values: NONE |
---|
| 656 | */ |
---|
| 657 | |
---|
| 658 | static void z85c30_enable_interrupts( |
---|
| 659 | int minor |
---|
| 660 | ) |
---|
| 661 | { |
---|
| 662 | unsigned32 ulCtrlPort; |
---|
| 663 | setRegister_f setReg; |
---|
| 664 | |
---|
| 665 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 666 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
| 667 | |
---|
| 668 | /* |
---|
| 669 | * Enable interrupts |
---|
| 670 | */ |
---|
| 671 | (*setReg)( |
---|
| 672 | ulCtrlPort, |
---|
| 673 | SCC_WR0_SEL_WR1, |
---|
| 674 | SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX |
---|
| 675 | ); |
---|
| 676 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); |
---|
| 677 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
| 678 | |
---|
| 679 | /* |
---|
| 680 | * Reset interrupts |
---|
| 681 | */ |
---|
| 682 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
| 683 | } |
---|
| 684 | |
---|
| 685 | static void z85c30_initialize_interrupts( |
---|
| 686 | int minor |
---|
| 687 | ) |
---|
| 688 | { |
---|
| 689 | z85c30_init(minor); |
---|
| 690 | |
---|
| 691 | Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); |
---|
| 692 | |
---|
| 693 | Console_Port_Data[minor].bActive=FALSE; |
---|
| 694 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 695 | z85c30_negate_RTS(minor); |
---|
| 696 | } |
---|
| 697 | |
---|
| 698 | if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { |
---|
| 699 | /* |
---|
| 700 | * Only do this for Channel A |
---|
| 701 | */ |
---|
| 702 | |
---|
| 703 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
| 704 | } |
---|
| 705 | |
---|
| 706 | z85c30_enable_interrupts(minor); |
---|
| 707 | } |
---|
| 708 | |
---|
| 709 | /* |
---|
| 710 | * z85c30_write_support_int |
---|
| 711 | * |
---|
| 712 | * Console Termios output entry point. |
---|
| 713 | * |
---|
| 714 | */ |
---|
| 715 | static int z85c30_write_support_int( |
---|
| 716 | int minor, |
---|
| 717 | const char *buf, |
---|
| 718 | int len) |
---|
| 719 | { |
---|
| 720 | int i; |
---|
| 721 | unsigned32 Irql; |
---|
| 722 | |
---|
| 723 | for (i=0; i<len;) { |
---|
| 724 | if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { |
---|
| 725 | if (!Console_Port_Data[minor].bActive) { |
---|
| 726 | /* |
---|
| 727 | * Wake up the device |
---|
| 728 | */ |
---|
| 729 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 730 | z85c30_assert_RTS(minor); |
---|
| 731 | } |
---|
| 732 | rtems_interrupt_disable(Irql); |
---|
| 733 | Console_Port_Data[minor].bActive=TRUE; |
---|
| 734 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
| 735 | rtems_interrupt_enable(Irql); |
---|
| 736 | } else { |
---|
| 737 | /* |
---|
| 738 | * Yield while we await an interrupt |
---|
| 739 | */ |
---|
| 740 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 741 | } |
---|
| 742 | |
---|
| 743 | /* |
---|
| 744 | * Wait for ring buffer to empty |
---|
| 745 | */ |
---|
| 746 | continue; |
---|
| 747 | } else { |
---|
| 748 | Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); |
---|
| 749 | i++; |
---|
| 750 | } |
---|
| 751 | } |
---|
| 752 | |
---|
| 753 | /* |
---|
| 754 | * Ensure that characters are on the way |
---|
| 755 | */ |
---|
| 756 | if (!Console_Port_Data[minor].bActive) { |
---|
| 757 | /* |
---|
| 758 | * Wake up the device |
---|
| 759 | */ |
---|
| 760 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
| 761 | z85c30_assert_RTS(minor); |
---|
| 762 | } |
---|
| 763 | rtems_interrupt_disable(Irql); |
---|
| 764 | Console_Port_Data[minor].bActive=TRUE; |
---|
| 765 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
| 766 | rtems_interrupt_enable(Irql); |
---|
| 767 | } |
---|
| 768 | |
---|
| 769 | return (len); |
---|
| 770 | } |
---|
| 771 | |
---|
| 772 | /* |
---|
| 773 | * z85c30_inbyte_nonblocking_polled |
---|
| 774 | * |
---|
| 775 | * This routine polls for a character. |
---|
| 776 | */ |
---|
| 777 | static int z85c30_inbyte_nonblocking_polled( |
---|
| 778 | int minor |
---|
| 779 | ) |
---|
| 780 | { |
---|
| 781 | volatile unsigned8 z85c30_status; |
---|
| 782 | unsigned32 ulCtrlPort; |
---|
| 783 | getRegister_f getReg; |
---|
| 784 | getData_f getData; |
---|
| 785 | |
---|
| 786 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
| 787 | getData = Console_Port_Tbl[minor].getData; |
---|
| 788 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
| 789 | |
---|
| 790 | /* |
---|
| 791 | * return -1 if a character is not available. |
---|
| 792 | */ |
---|
| 793 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 794 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 795 | return -1; |
---|
| 796 | } |
---|
| 797 | |
---|
| 798 | /* |
---|
| 799 | * Return the character read. |
---|
| 800 | */ |
---|
| 801 | return (*getData)(Console_Port_Tbl[minor].ulDataPort); |
---|
| 802 | } |
---|
| 803 | |
---|
| 804 | /* |
---|
| 805 | * z85c30_write_support_polled |
---|
| 806 | * |
---|
| 807 | * Console Termios output entry point. |
---|
| 808 | * |
---|
| 809 | */ |
---|
| 810 | |
---|
| 811 | static int z85c30_write_support_polled( |
---|
| 812 | int minor, |
---|
| 813 | const char *buf, |
---|
| 814 | int len) |
---|
| 815 | { |
---|
| 816 | int nwrite=0; |
---|
| 817 | |
---|
| 818 | /* |
---|
| 819 | * poll each byte in the string out of the port. |
---|
| 820 | */ |
---|
| 821 | while (nwrite < len) { |
---|
| 822 | z85c30_write_polled(minor, *buf++); |
---|
| 823 | nwrite++; |
---|
| 824 | } |
---|
| 825 | |
---|
| 826 | /* |
---|
| 827 | * return the number of bytes written. |
---|
| 828 | */ |
---|
| 829 | return nwrite; |
---|
| 830 | } |
---|