[4f1173bc] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | */ |
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| 5 | |
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[0737710] | 6 | /* |
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| 7 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 8 | * |
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| 9 | * |
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[4f1173bc] | 10 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 11 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 12 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 13 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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[0737710] | 14 | * |
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[4f1173bc] | 15 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 16 | * this file, provided that this notice, plus the above copyright notice |
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| 17 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 18 | * no support for this code. |
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[0737710] | 19 | * |
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[4f1173bc] | 20 | * COPYRIGHT (c) 1989-2012. |
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| 21 | * On-Line Applications Research Corporation (OAR). |
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| 22 | * |
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| 23 | * The license and distribution terms for this file may be |
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| 24 | * found in the file LICENSE in this distribution or at |
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[c499856] | 25 | * http://www.rtems.org/license/LICENSE. |
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[0737710] | 26 | */ |
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| 27 | |
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| 28 | #ifndef _NS16550_P_H_ |
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| 29 | #define _NS16550_P_H_ |
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| 30 | |
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[5455f23a] | 31 | #include <libchip/serial.h> |
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| 32 | |
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[0737710] | 33 | #ifdef __cplusplus |
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| 34 | extern "C" { |
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| 35 | #endif |
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[aa0da6b] | 36 | |
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[27045a82] | 37 | /* |
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| 38 | * Define NS16550_STATIC to nothing while debugging so the entry points |
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| 39 | * will show up in the symbol table. |
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| 40 | */ |
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| 41 | |
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[65cd5e9] | 42 | #define NS16550_STATIC static |
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[27045a82] | 43 | |
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[0737710] | 44 | #define NS16550_RECEIVE_BUFFER 0 |
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[ec5d4505] | 45 | #define NS16550_TRANSMIT_BUFFER 0 |
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[0737710] | 46 | #define NS16550_INTERRUPT_ENABLE 1 |
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| 47 | #define NS16550_INTERRUPT_ID 2 |
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[ec5d4505] | 48 | #define NS16550_FIFO_CONTROL 2 |
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[0737710] | 49 | #define NS16550_LINE_CONTROL 3 |
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| 50 | #define NS16550_MODEM_CONTROL 4 |
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| 51 | #define NS16550_LINE_STATUS 5 |
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| 52 | #define NS16550_MODEM_STATUS 6 |
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| 53 | #define NS16550_SCRATCH_PAD 7 |
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[c39148d6] | 54 | #define NS16550_FRACTIONAL_DIVIDER 10 |
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[aa0da6b] | 55 | |
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[0737710] | 56 | /* |
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| 57 | * Define serial port interrupt enable register structure. |
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| 58 | */ |
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| 59 | |
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[aa0da6b] | 60 | #define SP_INT_RX_ENABLE 0x01 |
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| 61 | #define SP_INT_TX_ENABLE 0x02 |
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| 62 | #define SP_INT_LS_ENABLE 0x04 |
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| 63 | #define SP_INT_MS_ENABLE 0x08 |
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[0737710] | 64 | |
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[70a9451] | 65 | #define NS16550_ENABLE_ALL_INTR (SP_INT_RX_ENABLE | SP_INT_TX_ENABLE) |
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| 66 | #define NS16550_DISABLE_ALL_INTR 0x00 |
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| 67 | #define NS16550_ENABLE_ALL_INTR_EXCEPT_TX (SP_INT_RX_ENABLE) |
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| 68 | |
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[0737710] | 69 | /* |
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[ec5d4505] | 70 | * Define serial port interrupt ID register structure. |
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[0737710] | 71 | */ |
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| 72 | |
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[ec5d4505] | 73 | #define SP_IID_0 0x01 |
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| 74 | #define SP_IID_1 0x02 |
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| 75 | #define SP_IID_2 0x04 |
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| 76 | #define SP_IID_3 0x08 |
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[0737710] | 77 | |
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| 78 | /* |
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| 79 | * Define serial port fifo control register structure. |
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| 80 | */ |
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[aa0da6b] | 81 | |
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| 82 | #define SP_FIFO_ENABLE 0x01 |
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| 83 | #define SP_FIFO_RXRST 0x02 |
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| 84 | #define SP_FIFO_TXRST 0x04 |
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| 85 | #define SP_FIFO_DMA 0x08 |
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| 86 | #define SP_FIFO_RXLEVEL 0xc0 |
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[0737710] | 87 | |
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[ec5d4505] | 88 | #define SP_FIFO_SIZE 16 |
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| 89 | |
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[0737710] | 90 | /* |
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| 91 | * Define serial port line control register structure. |
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| 92 | */ |
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[aa0da6b] | 93 | |
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| 94 | #define SP_LINE_SIZE 0x03 |
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| 95 | #define SP_LINE_STOP 0x04 |
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| 96 | #define SP_LINE_PAR 0x08 |
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| 97 | #define SP_LINE_ODD 0x10 |
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| 98 | #define SP_LINE_STICK 0x20 |
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| 99 | #define SP_LINE_BREAK 0x40 |
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| 100 | #define SP_LINE_DLAB 0x80 |
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[0737710] | 101 | |
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| 102 | /* |
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| 103 | * Line status register character size definitions. |
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| 104 | */ |
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[aa0da6b] | 105 | |
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[0737710] | 106 | #define FIVE_BITS 0x0 /* five bits per character */ |
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| 107 | #define SIX_BITS 0x1 /* six bits per character */ |
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| 108 | #define SEVEN_BITS 0x2 /* seven bits per character */ |
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| 109 | #define EIGHT_BITS 0x3 /* eight bits per character */ |
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| 110 | |
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| 111 | /* |
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| 112 | * Define serial port modem control register structure. |
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| 113 | */ |
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[aa0da6b] | 114 | |
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| 115 | #define SP_MODEM_DTR 0x01 |
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| 116 | #define SP_MODEM_RTS 0x02 |
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| 117 | #define SP_MODEM_IRQ 0x08 |
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| 118 | #define SP_MODEM_LOOP 0x10 |
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| 119 | #define SP_MODEM_DIV4 0x80 |
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[0737710] | 120 | |
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| 121 | /* |
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| 122 | * Define serial port line status register structure. |
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| 123 | */ |
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[aa0da6b] | 124 | |
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| 125 | #define SP_LSR_RDY 0x01 |
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| 126 | #define SP_LSR_EOVRUN 0x02 |
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| 127 | #define SP_LSR_EPAR 0x04 |
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| 128 | #define SP_LSR_EFRAME 0x08 |
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| 129 | #define SP_LSR_BREAK 0x10 |
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| 130 | #define SP_LSR_THOLD 0x20 |
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| 131 | #define SP_LSR_TX 0x40 |
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| 132 | #define SP_LSR_EFIFO 0x80 |
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[0737710] | 133 | |
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| 134 | #ifdef __cplusplus |
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| 135 | } |
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| 136 | #endif |
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| 137 | |
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| 138 | #endif /* _NS16550_P_H_ */ |
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