[cd58d82] | 1 | /* |
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| 2 | * |
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[08311cc3] | 3 | * COPYRIGHT (c) 1989-1999. |
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[cd58d82] | 4 | * On-Line Applications Research Corporation (OAR). |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[94365d9] | 8 | * http://www.rtems.com/license/LICENSE. |
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[cd58d82] | 9 | * |
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| 10 | * $Id$ |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef _MC68681_P_H_ |
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| 14 | #define _MC68681_P_H_ |
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| 15 | |
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| 16 | #ifdef __cplusplus |
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| 17 | extern "C" { |
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| 18 | #endif |
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[424e23ee] | 19 | |
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[37e8259] | 20 | /* |
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| 21 | * Define MC68681_STATIC to nothing while debugging so the entry points |
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| 22 | * will show up in the symbol table. |
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| 23 | */ |
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| 24 | |
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| 25 | #define MC68681_STATIC |
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| 26 | |
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| 27 | /* #define MC68681_STATIC static */ |
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| 28 | |
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[ab2dbd7] | 29 | /* |
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| 30 | * mc68681 register offsets Read/Write Addresses |
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| 31 | */ |
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| 32 | |
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| 33 | #define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */ |
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| 34 | #define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */ |
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| 35 | |
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| 36 | #define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */ |
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| 37 | #define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */ |
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| 38 | #define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */ |
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| 39 | #define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */ |
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| 40 | #define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */ |
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| 41 | |
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| 42 | #define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */ |
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| 43 | #define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */ |
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| 44 | |
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| 45 | /* |
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| 46 | * mc68681 register offsets Read Only Addresses |
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| 47 | */ |
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| 48 | |
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| 49 | #define MC68681_STATUS_REG_A 1 /* SRA */ |
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| 50 | #define MC68681_MASK_ISR_REG 2 /* MISR */ |
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| 51 | #define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */ |
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| 52 | #define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */ |
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| 53 | #define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */ |
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| 54 | #define MC68681_STATUS_REG_B 9 /* SRB */ |
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| 55 | #define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */ |
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| 56 | #define MC68681_INPUT_PORT 13 /* IP */ |
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| 57 | #define MC68681_START_COUNT_CMD 14 /* SCC */ |
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| 58 | #define MC68681_STOP_COUNT_CMD 15 /* STC */ |
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| 59 | |
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| 60 | /* |
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| 61 | * mc68681 register offsets Write Only Addresses |
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| 62 | */ |
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| 63 | |
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| 64 | #define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */ |
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| 65 | #define MC68681_COMMAND_REG_A 2 /* CRA */ |
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| 66 | #define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */ |
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| 67 | #define MC68681_AUX_CTRL_REG 4 /* ACR */ |
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| 68 | #define MC68681_INTERRUPT_MASK_REG 5 /* IMR */ |
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| 69 | #define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */ |
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| 70 | #define MC68681_COMMAND_REG_B 10 /* CRB */ |
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| 71 | #define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */ |
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| 72 | #define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */ |
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| 73 | #define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */ |
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| 74 | #define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */ |
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| 75 | |
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| 76 | /* |
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| 77 | * DUART Command Register Definitions: |
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| 78 | * |
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| 79 | * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B |
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| 80 | */ |
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| 81 | |
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| 82 | #define MC68681_MODE_REG_ENABLE_RX 0x01 |
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| 83 | #define MC68681_MODE_REG_DISABLE_RX 0x02 |
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| 84 | #define MC68681_MODE_REG_ENABLE_TX 0x04 |
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| 85 | #define MC68681_MODE_REG_DISABLE_TX 0x08 |
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| 86 | #define MC68681_MODE_REG_RESET_MR_PTR 0x10 |
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| 87 | #define MC68681_MODE_REG_RESET_RX 0x20 |
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| 88 | #define MC68681_MODE_REG_RESET_TX 0x30 |
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| 89 | #define MC68681_MODE_REG_RESET_ERROR 0x40 |
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| 90 | #define MC68681_MODE_REG_RESET_BREAK 0x50 |
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| 91 | #define MC68681_MODE_REG_START_BREAK 0x60 |
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| 92 | #define MC68681_MODE_REG_STOP_BREAK 0x70 |
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| 93 | #define MC68681_MODE_REG_SET_RX_BRG 0x80 |
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| 94 | #define MC68681_MODE_REG_CLEAR_RX_BRG 0x90 |
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| 95 | #define MC68681_MODE_REG_SET_TX_BRG 0xa0 |
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| 96 | #define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0 |
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| 97 | #define MC68681_MODE_REG_SET_STANDBY 0xc0 |
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| 98 | #define MC68681_MODE_REG_SET_ACTIVE 0xd0 |
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| 99 | |
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| 100 | /* |
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| 101 | * Mode Register Definitions |
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| 102 | * |
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| 103 | * MC68681_MODE_REG_1A |
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| 104 | * MC68681_MODE_REG_1B |
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| 105 | */ |
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| 106 | |
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| 107 | #define MC68681_5BIT_CHARS 0x00 |
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| 108 | #define MC68681_6BIT_CHARS 0x01 |
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| 109 | #define MC68681_7BIT_CHARS 0x02 |
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| 110 | #define MC68681_8BIT_CHARS 0x03 |
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| 111 | |
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| 112 | #define MC68681_ODD_PARITY 0x00 |
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| 113 | #define MC68681_EVEN_PARITY 0x04 |
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| 114 | |
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| 115 | #define MC68681_WITH_PARITY 0x00 |
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| 116 | #define MC68681_FORCE_PARITY 0x08 |
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| 117 | #define MC68681_NO_PARITY 0x10 |
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| 118 | #define MC68681_MULTI_DROP 0x18 |
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| 119 | |
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| 120 | #define MC68681_ERR_MODE_CHAR 0x00 |
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| 121 | #define MC68681_ERR_MODE_BLOCK 0x20 |
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| 122 | |
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| 123 | #define MC68681_RX_INTR_RX_READY 0x00 |
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| 124 | #define MC68681_RX_INTR_FFULL 0x40 |
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| 125 | |
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| 126 | #define MC68681_NO_RX_RTS_CTL 0x00 |
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| 127 | #define MC68681_RX_RTS_CTRL 0x80 |
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| 128 | |
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| 129 | /* |
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| 130 | * Mode Register Definitions |
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| 131 | * |
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| 132 | * MC68681_MODE_REG_2A |
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| 133 | * MC68681_MODE_REG_2B |
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| 134 | */ |
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| 135 | |
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| 136 | #define MC68681_STOP_BIT_LENGTH__563 0x00 |
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| 137 | #define MC68681_STOP_BIT_LENGTH__625 0x01 |
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| 138 | #define MC68681_STOP_BIT_LENGTH__688 0x02 |
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| 139 | #define MC68681_STOP_BIT_LENGTH__75 0x03 |
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| 140 | #define MC68681_STOP_BIT_LENGTH__813 0x04 |
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| 141 | #define MC68681_STOP_BIT_LENGTH__875 0x05 |
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| 142 | #define MC68681_STOP_BIT_LENGTH__938 0x06 |
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| 143 | #define MC68681_STOP_BIT_LENGTH_1 0x07 |
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| 144 | #define MC68681_STOP_BIT_LENGTH_1_563 0x08 |
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| 145 | #define MC68681_STOP_BIT_LENGTH_1_625 0x09 |
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| 146 | #define MC68681_STOP_BIT_LENGTH_1_688 0x0a |
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| 147 | #define MC68681_STOP_BIT_LENGTH_1_75 0x0b |
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| 148 | #define MC68681_STOP_BIT_LENGTH_1_813 0x0c |
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| 149 | #define MC68681_STOP_BIT_LENGTH_1_875 0x0d |
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| 150 | #define MC68681_STOP_BIT_LENGTH_1_938 0x0e |
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| 151 | #define MC68681_STOP_BIT_LENGTH_2 0x0f |
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| 152 | |
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| 153 | #define MC68681_CTS_ENABLE_TX 0x10 |
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| 154 | #define MC68681_TX_RTS_CTRL 0x20 |
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| 155 | |
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| 156 | #define MC68681_CHANNEL_MODE_NORMAL 0x00 |
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| 157 | #define MC68681_CHANNEL_MODE_ECHO 0x40 |
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| 158 | #define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80 |
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| 159 | #define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0 |
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| 160 | |
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| 161 | /* |
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| 162 | * Status Register Definitions |
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| 163 | * |
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| 164 | * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B |
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| 165 | */ |
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| 166 | |
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| 167 | #define MC68681_RX_READY 0x01 |
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| 168 | #define MC68681_FFULL 0x02 |
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| 169 | #define MC68681_TX_READY 0x04 |
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| 170 | #define MC68681_TX_EMPTY 0x08 |
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| 171 | #define MC68681_OVERRUN_ERROR 0x10 |
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| 172 | #define MC68681_PARITY_ERROR 0x20 |
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| 173 | #define MC68681_FRAMING_ERROR 0x40 |
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| 174 | #define MC68681_RECEIVED_BREAK 0x80 |
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| 175 | |
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[4f0ffa57] | 176 | #define MC68681_RX_ERRORS \ |
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| 177 | (MC68681_OVERRUN_ERROR|MC68681_PARITY_ERROR| \ |
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| 178 | MC68681_FRAMING_ERROR|MC68681_RECEIVED_BREAK) |
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| 179 | |
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[ab2dbd7] | 180 | /* |
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| 181 | * Interupt Status Register Definitions. |
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| 182 | * |
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| 183 | * MC68681_INTERRUPT_STATUS_REG |
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| 184 | */ |
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| 185 | |
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| 186 | /* |
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| 187 | * Interupt Mask Register Definitions |
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| 188 | * |
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| 189 | * MC68681_INTERRUPT_MASK_REG |
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| 190 | */ |
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| 191 | |
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[efaf85fa] | 192 | /* These are passed to mc68681_build_imr */ |
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| 193 | #define MC68681_IR_TX_READY 0x01 |
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| 194 | #define MC68681_IR_RX_READY 0x02 |
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| 195 | #define MC68681_IR_BREAK 0x04 |
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| 196 | #define MC68681_IMR_ENABLE_ALL 0x07 |
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| 197 | #define MC68681_IMR_DISABLE_ALL 0x00 |
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| 198 | #define MC68681_IMR_ENABLE_ALL_EXCEPT_TX 0x06 |
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| 199 | |
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[ab2dbd7] | 200 | #define MC68681_IR_TX_READY_A 0x01 |
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| 201 | #define MC68681_IR_RX_READY_A 0x02 |
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| 202 | #define MC68681_IR_BREAK_A 0x04 |
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| 203 | #define MC68681_IR_COUNTER_READY 0x08 |
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| 204 | #define MC68681_IR_TX_READY_B 0x10 |
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| 205 | #define MC68681_IR_RX_READY_B 0x20 |
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| 206 | #define MC68681_IR_BREAK_B 0x40 |
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| 207 | #define MC68681_IR_INPUT_PORT_CHANGE 0x80 |
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| 208 | |
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| 209 | /* |
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| 210 | * Status Register Definitions. |
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| 211 | * |
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| 212 | * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B |
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| 213 | */ |
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| 214 | |
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| 215 | #define MC68681_STATUS_RXRDY 0x01 |
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| 216 | #define MC68681_STATUS_FFULL 0x02 |
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| 217 | #define MC68681_STATUS_TXRDY 0x04 |
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| 218 | #define MC68681_STATUS_TXEMT 0x08 |
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| 219 | #define MC68681_STATUS_OVERRUN_ERROR 0x10 |
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| 220 | #define MC68681_STATUS_PARITY_ERROR 0x20 |
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| 221 | #define MC68681_STATUS_FRAMING_ERROR 0x40 |
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| 222 | #define MC68681_STATUS_RECEIVED_BREAK 0x80 |
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| 223 | |
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| 224 | /* |
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| 225 | * Definitions for the Interrupt Vector Register: |
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| 226 | * |
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| 227 | * MC68681_INTERRUPT_VECTOR_REG |
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| 228 | */ |
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| 229 | |
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| 230 | #define MC68681_INTERRUPT_VECTOR_INIT 0x0f |
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| 231 | |
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| 232 | /* |
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| 233 | * Definitions for the Auxiliary Control Register |
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| 234 | * |
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| 235 | * MC68681_AUX_CTRL_REG |
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| 236 | */ |
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| 237 | |
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| 238 | #define MC68681_AUX_BRG_SET1 0x00 |
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| 239 | #define MC68681_AUX_BRG_SET2 0x80 |
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| 240 | |
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| 241 | /* |
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| 242 | * Per chip context control |
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| 243 | */ |
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[424e23ee] | 244 | |
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[cd58d82] | 245 | typedef struct _mc68681_context |
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| 246 | { |
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[efaf85fa] | 247 | int mate; |
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| 248 | unsigned char imr; |
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[cd58d82] | 249 | } mc68681_context; |
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| 250 | |
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| 251 | /* |
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| 252 | * Driver functions |
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| 253 | */ |
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[6640459d] | 254 | MC68681_STATIC bool mc68681_probe(int minor); |
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[cd58d82] | 255 | |
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[a3d3d9a] | 256 | MC68681_STATIC int mc68681_set_attributes( |
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[9eef52b] | 257 | int minor, |
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| 258 | const struct termios *t |
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| 259 | ); |
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| 260 | |
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[37e8259] | 261 | MC68681_STATIC void mc68681_init(int minor); |
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[cd58d82] | 262 | |
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[37e8259] | 263 | MC68681_STATIC int mc68681_open( |
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[ab2dbd7] | 264 | int major, |
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| 265 | int minor, |
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| 266 | void * arg |
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[cd58d82] | 267 | ); |
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| 268 | |
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[37e8259] | 269 | MC68681_STATIC int mc68681_close( |
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[ab2dbd7] | 270 | int major, |
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| 271 | int minor, |
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| 272 | void * arg |
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[cd58d82] | 273 | ); |
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| 274 | |
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[37e8259] | 275 | MC68681_STATIC void mc68681_write_polled( |
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[a3d3d9a] | 276 | int minor, |
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[ab2dbd7] | 277 | char cChar |
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[cd58d82] | 278 | ); |
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| 279 | |
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[37e8259] | 280 | MC68681_STATIC void mc68681_initialize_interrupts(int minor); |
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[cd58d82] | 281 | |
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[3ed964f9] | 282 | MC68681_STATIC ssize_t mc68681_write_support_int( |
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[ab2dbd7] | 283 | int minor, |
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| 284 | const char *buf, |
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[3ed964f9] | 285 | size_t len |
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[cd58d82] | 286 | ); |
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| 287 | |
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[3ed964f9] | 288 | MC68681_STATIC ssize_t mc68681_write_support_polled( |
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[ab2dbd7] | 289 | int minor, |
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| 290 | const char *buf, |
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[3ed964f9] | 291 | size_t len |
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[ab2dbd7] | 292 | ); |
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[cd58d82] | 293 | |
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[37e8259] | 294 | MC68681_STATIC int mc68681_inbyte_nonblocking_polled( |
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[ab2dbd7] | 295 | int minor |
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[cd58d82] | 296 | ); |
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| 297 | |
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[efaf85fa] | 298 | MC68681_STATIC unsigned int mc68681_build_imr( |
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| 299 | int minor, |
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| 300 | int enable_flag |
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| 301 | ); |
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| 302 | |
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| 303 | MC68681_STATIC void mc68681_process( |
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| 304 | int minor |
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| 305 | ); |
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| 306 | |
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| 307 | MC68681_STATIC void mc68681_enable_interrupts( |
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| 308 | int minor, |
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| 309 | int imr_mask |
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| 310 | ); |
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| 311 | |
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[cd58d82] | 312 | #ifdef __cplusplus |
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| 313 | } |
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| 314 | #endif |
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| 315 | |
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| 316 | #endif /* _MC68681_P_H_ */ |
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