source: rtems/c/src/libchip/network/sonic.h @ f619250

4.115
Last change on this file since f619250 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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1/*
2 *       RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC'
3 *         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER
4 *
5 *                REUSABLE CHIP DRIVER CONFIGURATION
6 *
7 * References:
8 *
9 *  1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
10 *     Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
11 *     1995.
12 *
13 *  2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
14 *     Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
15 *     RRD-B30M75, National Semiconductor, March, 1991.
16 *
17 *  COPYRIGHT (c) 1989-1997.
18 *  On-Line Applications Research Corporation (OAR).
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.rtems.com/license/LICENSE.
23 */
24
25#ifndef _SONIC_DP83932_
26#define _SONIC_DP83932_
27
28
29 /*
30  * Debug levels
31  *
32  */
33
34#define SONIC_DEBUG_NONE                0x0000
35#define SONIC_DEBUG_ALL                 0xFFFF
36#define SONIC_DEBUG_PRINT_REGISTERS     0x0001
37#define SONIC_DEBUG_MEMORY              0x0002
38#define SONIC_DEBUG_MEMORY_ALLOCATE     0x0004
39#define SONIC_DEBUG_MEMORY_DESCRIPTORS  0x0008
40#define SONIC_DEBUG_FRAGMENTS           0x0008
41#define SONIC_DEBUG_CAM                 0x0010
42#define SONIC_DEBUG_DESCRIPTORS         0x0020
43#define SONIC_DEBUG_ERRORS              0x0040
44#define SONIC_DEBUG_DUMP_TX_MBUFS       0x0080
45#define SONIC_DEBUG_DUMP_RX_MBUFS       0x0100
46
47#define SONIC_DEBUG_DUMP_MBUFS \
48      (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS)
49
50#define SONIC_DEBUG  (SONIC_DEBUG_NONE)
51/*
52#define SONIC_DEBUG  (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\
53      SONIC_DEBUG_DESCRIPTORS)
54*/
55
56/*
57  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS))
58  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS))
59*/
60
61#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
62extern char SONIC_Reg_name[64][6];
63#endif
64
65
66/*
67 *  Configuration Information
68 */
69
70typedef void (*sonic_write_register_t)(
71  void       *base,
72  uint32_t    regno,
73  uint32_t    value
74);
75
76typedef uint32_t   (*sonic_read_register_t)(
77  void       *base,
78  uint32_t    regno
79);
80
81typedef struct {
82  void                   *base_address;
83  uint32_t                vector;
84  uint32_t                dcr_value;
85  uint32_t                dc2_value;
86  uint32_t                tda_count;
87  uint32_t                rda_count;
88  sonic_write_register_t  write_register;
89  sonic_read_register_t   read_register;
90} sonic_configuration_t;
91
92/*
93 ******************************************************************
94 *                                                                *
95 *                        Device Registers                        *
96 *                                                                *
97 ******************************************************************
98 */
99#define SONIC_REG_CR      0x00 /* Command */
100#define SONIC_REG_DCR     0x01 /* Data configuration */
101#define SONIC_REG_RCR     0x02 /* Receive control */
102#define SONIC_REG_TCR     0x03 /* Transmit control */
103#define SONIC_REG_IMR     0x04 /* Interrupt mask */
104#define SONIC_REG_ISR     0x05 /* Interrupt status */
105#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
106#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
107#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
108#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
109#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
110#define SONIC_REG_URRA    0x14 /* Upper receive resource */
111#define SONIC_REG_RSA     0x15 /* Resource start address */
112#define SONIC_REG_REA     0x16 /* Resource end address */
113#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
114#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
115#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
116#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
117#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
118#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
119#define SONIC_REG_CE      0x25 /* CAM enable */
120#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
121#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
122#define SONIC_REG_SR      0x28 /* Silicon revision */
123#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
124#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
125#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
126#define SONIC_REG_CRCT    0x2C /* CRC error tally */
127#define SONIC_REG_FAET    0x2D /* FAE tally */
128#define SONIC_REG_MPT     0x2E /* Missed packet tally */
129#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
130#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
131
132/*
133 * Command register
134 */
135#define CR_LCAM         0x0200
136#define CR_RRRA         0x0100
137#define CR_RST          0x0080
138#define CR_ST           0x0020
139#define CR_STP          0x0010
140#define CR_RXEN         0x0008
141#define CR_RXDIS        0x0004
142#define CR_TXP          0x0002
143#define CR_HTX          0x0001
144
145/*
146 * Data configuration register
147 */
148#define DCR_EXBUS       0x8000
149#define DCR_LBR         0x2000
150#define DCR_PO1         0x1000
151#define DCR_PO0         0x0800
152#define DCR_SBUS        0x0400
153#define DCR_USR1        0x0200
154#define DCR_USR0        0x0100
155#define DCR_WC1         0x0080
156#define DCR_WC0         0x0040
157#define DCR_DW          0x0020
158#define DCR_BMS         0x0010
159#define DCR_RFT1        0x0008
160#define DCR_RFT0        0x0004
161#define DCR_TFT1        0x0002
162#define DCR_TFT0        0x0001
163
164/* data configuration register aliases */
165#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
166#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
167
168#define DCR_WAIT0       0                 /* 0 wait states added */
169#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
170#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
171#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
172
173#define DCR_DW16        0       /* use 16-bit DMA accesses */
174#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
175
176#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
177#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
178
179#define DCR_RFT4        0               /* receive threshold 4 bytes */
180#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
181#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
182#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
183
184#define DCR_TFT8        0               /* transmit threshold 8 bytes */
185#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
186#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
187#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
188
189/*
190 * Receive control register
191 */
192#define RCR_ERR         0x8000
193#define RCR_RNT         0x4000
194#define RCR_BRD         0x2000
195#define RCR_PRO         0x1000
196#define RCR_AMC         0x0800
197#define RCR_LB1         0x0400
198#define RCR_LB0         0x0200
199#define RCR_MC          0x0100
200#define RCR_BC          0x0080
201#define RCR_LPKT        0x0040
202#define RCR_CRS         0x0020
203#define RCR_COL         0x0010
204#define RCR_CRCR        0x0008
205#define RCR_FAER        0x0004
206#define RCR_LBK         0x0002
207#define RCR_PRX         0x0001
208
209/*
210 * Transmit control register
211 */
212#define TCR_PINT        0x8000
213#define TCR_POWC        0x4000
214#define TCR_CRCI        0x2000
215#define TCR_EXDIS       0x1000
216#define TCR_EXD         0x0400
217#define TCR_DEF         0x0200
218#define TCR_NCRS        0x0100
219#define TCR_CRSL        0x0080
220#define TCR_EXC         0x0040
221#define TCR_OWC         0x0020
222#define TCR_PMB         0x0008
223#define TCR_FU          0x0004
224#define TCR_BCM         0x0002
225#define TCR_PTX         0x0001
226
227/*
228 * Interrupt mask register
229 */
230#define IMR_BREN        0x4000
231#define IMR_HBLEN       0x2000
232#define IMR_LCDEN       0x1000
233#define IMR_PINTEN      0x0800
234#define IMR_PRXEN       0x0400
235#define IMR_PTXEN       0x0200
236#define IMR_TXEREN      0x0100
237#define IMR_TCEN        0x0080
238#define IMR_RDEEN       0x0040
239#define IMR_RBEEN       0x0020
240#define IMR_RBAEEN      0x0010
241#define IMR_CRCEN       0x0008
242#define IMR_FAEEN       0x0004
243#define IMR_MPEN        0x0002
244#define IMR_RFOEN       0x0001
245
246/*
247 * Interrupt status register
248 */
249#define ISR_BR          0x4000
250#define ISR_HBL         0x2000
251#define ISR_LCD         0x1000
252#define ISR_PINT        0x0800
253#define ISR_PKTRX       0x0400
254#define ISR_TXDN        0x0200
255#define ISR_TXER        0x0100
256#define ISR_TC          0x0080
257#define ISR_RDE         0x0040
258#define ISR_RBE         0x0020
259#define ISR_RBAE        0x0010
260#define ISR_CRC         0x0008
261#define ISR_FAE         0x0004
262#define ISR_MP          0x0002
263#define ISR_RFO         0x0001
264
265/*
266 * Data configuration register 2
267 */
268#define DCR2_EXPO3      0x8000
269#define DCR2_EXPO2      0x4000
270#define DCR2_EXPO1      0x2000
271#define DCR2_EXPO0      0x1000
272#define DCR2_HBDIS      0x0800
273#define DCR2_PH         0x0010
274#define DCR2_PCM        0x0004
275#define DCR2_PCNM       0x0002
276#define DCR2_RJCM       0x0001
277
278/*
279 *  Known values for the Silicon Revision Register.
280 *  Note that DP83934 has revision 5 and seems to work.
281 */
282
283#define SONIC_REVISION_B   4
284#define SONIC_REVISION_DP83934   5
285#define SONIC_REVISION_C   6
286
287/*
288 ******************************************************************
289 *                                                                *
290 *                   Transmit Buffer Management                   *
291 *                                                                *
292 ******************************************************************
293 */
294
295/*
296 * Transmit descriptor area entry.
297 * There is one transmit descriptor for each packet to be transmitted.
298 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
299 * per descriptor.
300 */
301#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
302struct TransmitDescriptor {
303  uint32_t          status;
304  uint32_t          pkt_config;
305  uint32_t          pkt_size;
306  uint32_t          frag_count;
307
308  /*
309   * Packet fragment pointers
310   */
311  struct TransmitDescriptorFragLink {
312      uint32_t   frag_lsw;  /* LSW of fragment address */
313#define                      frag_link frag_lsw
314      uint32_t   frag_msw;  /* MSW of fragment address */
315      uint32_t   frag_size;
316  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
317
318  /*
319   * Space for link if all fragment pointers are used.
320   */
321  uint32_t          link_pad;
322
323  /*
324   * Extra RTEMS stuff
325   */
326  struct TransmitDescriptor       *next;  /* Circularly-linked list */
327  struct mbuf                     *mbufp; /* First mbuf in packet */
328  volatile uint32_t         *linkp; /* Pointer to un[xxx].link */
329};
330typedef struct TransmitDescriptor TransmitDescriptor_t;
331typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
332
333/*
334 * Transmit Configuration.
335 * For standard Ethernet transmission, all bits in the transmit
336 * configuration field are set to 0.
337 */
338#define TDA_CONFIG_PINT 0x8000
339#define TDA_CONFIG_POWC 0x4000
340#define TDA_CONFIG_CRCI 0x2000
341#define TDA_CONFIG_EXDIS        0x1000
342
343/*
344 * Transmit status
345 */
346#define TDA_STATUS_COLLISION_MASK       0xF800
347#define TDA_STATUS_COLLISION_SHIFT      11
348#define TDA_STATUS_EXD          0x0400
349#define TDA_STATUS_DEF          0x0200
350#define TDA_STATUS_NCRS         0x0100
351#define TDA_STATUS_CRSL         0x0080
352#define TDA_STATUS_EXC          0x0040
353#define TDA_STATUS_OWC          0x0020
354#define TDA_STATUS_PMB          0x0008
355#define TDA_STATUS_FU           0x0004
356#define TDA_STATUS_BCM          0x0002
357#define TDA_STATUS_PTX          0x0001
358
359#define TDA_LINK_EOL      0x0001
360#define TDA_LINK_EOL_MASK 0xFFFE
361
362
363
364/*
365 ******************************************************************
366 *                                                                *
367 *                    Receive Buffer Management                   *
368 *                                                                *
369 ******************************************************************
370 */
371
372/*
373 * Receive resource area entry.
374 * There is one receive resource entry for each receive buffer area (RBA).
375 * This driver allows only one packet per receive buffer area, so one
376 * receive resource entry corresponds to one correctly-received packet.
377 */
378struct ReceiveResource {
379  uint32_t          buff_ptr_lsw;   /* LSW of RBA address */
380  uint32_t          buff_ptr_msw;   /* MSW of RBA address */
381  uint32_t          buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
382  uint32_t          buff_wc_msw;    /* MSW of RBA size (16-bit words) */
383};
384typedef struct ReceiveResource ReceiveResource_t;
385typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
386
387/*
388 * Receive descriptor area entry.
389 * There is one receive descriptor for each packet received.
390 */
391struct ReceiveDescriptor {
392  uint32_t          status;
393  uint32_t          byte_count;
394  uint32_t          pkt_lsw;        /* LSW of packet address */
395  uint32_t          pkt_msw;        /* MSW of packet address */
396  uint32_t          seq_no;
397  uint32_t          link;
398  uint32_t          in_use;
399
400  /*
401   * Extra RTEMS stuff
402   */
403  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
404  struct mbuf                        *mbufp; /* First mbuf in packet */
405};
406typedef struct ReceiveDescriptor ReceiveDescriptor_t;
407typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
408
409typedef struct {
410  uint32_t    cep;  /* CAM Entry Pointer */
411  uint32_t    cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
412  uint32_t    cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
413  uint32_t    cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
414  uint32_t    ce;
415} CamDescriptor_t;
416
417typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
418
419/*
420 * Receive status
421 */
422#define RDA_STATUS_ERR          0x8800
423#define RDA_STATUS_RNT          0x4000
424#define RDA_STATUS_BRD          0x2000
425#define RDA_STATUS_PRO          0x1000
426#define RDA_STATUS_AMC          0x0800
427#define RDA_STATUS_LB1          0x0400
428#define RDA_STATUS_LB0          0x0200
429#define RDA_STATUS_MC           0x0100
430#define RDA_STATUS_BC           0x0080
431#define RDA_STATUS_LPKT         0x0040
432#define RDA_STATUS_CRS          0x0020
433#define RDA_STATUS_COL          0x0010
434#define RDA_STATUS_CRCR         0x0008
435#define RDA_STATUS_FAER         0x0004
436#define RDA_STATUS_LBK          0x0002
437#define RDA_STATUS_PRX          0x0001
438
439#define RDA_LINK_EOL        0x0001
440#define RDA_LINK_EOL_MASK   0xFFFE
441#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
442                                    /*   and the driver can process it */
443#define RDA_FREE            0xFFFF  /* SONIC can use it */
444
445/*
446 *  Attach routine
447 */
448
449int rtems_sonic_driver_attach (
450  struct rtems_bsdnet_ifconfig *config,
451  sonic_configuration_t *chip
452);
453
454#ifdef CPU_U32_FIX
455void ipalign(struct mbuf *m);
456#endif
457
458#endif /* _SONIC_DP83932_ */
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