source: rtems/c/src/libchip/network/sonic.h @ d0d73ec

4.104.114.84.95
Last change on this file since d0d73ec was c752ff2d, checked in by Joel Sherrill <joel.sherrill@…>, on 11/26/01 at 14:34:19

2001-11-26 Ralf Corsepius <corsepiu@…>

  • network/sonic.h: Fix typo.
  • Property mode set to 100644
File size: 14.8 KB
Line 
1/*
2 *       RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC'
3 *         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER
4 *
5 *                REUSABLE CHIP DRIVER CONFIGURATION
6 *
7 * References:
8 *
9 *  1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
10 *     Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
11 *     1995.
12 *
13 *  2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
14 *     Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
15 *     RRD-B30M75, National Semiconductor, March, 1991.
16 *
17 *  COPYRIGHT (c) 1989-1997.
18 *  On-Line Applications Research Corporation (OAR).
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.OARcorp.com/rtems/license.html.
23 *
24 *  $Id$
25 */
26
27#ifndef _SONIC_DP83932_
28#define _SONIC_DP83932_
29
30
31 /*
32  * Debug levels
33  *
34  */
35
36#define SONIC_DEBUG_NONE                0x0000
37#define SONIC_DEBUG_ALL                 0xFFFF
38#define SONIC_DEBUG_PRINT_REGISTERS     0x0001
39#define SONIC_DEBUG_MEMORY              0x0002
40#define SONIC_DEBUG_MEMORY_ALLOCATE     0x0004
41#define SONIC_DEBUG_MEMORY_DESCRIPTORS  0x0008
42#define SONIC_DEBUG_FRAGMENTS           0x0008
43#define SONIC_DEBUG_CAM                 0x0010
44#define SONIC_DEBUG_DESCRIPTORS         0x0020
45#define SONIC_DEBUG_ERRORS              0x0040
46#define SONIC_DEBUG_DUMP_TX_MBUFS       0x0080
47#define SONIC_DEBUG_DUMP_RX_MBUFS       0x0100
48
49#define SONIC_DEBUG_DUMP_MBUFS \
50      (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS)
51
52#define SONIC_DEBUG  (SONIC_DEBUG_NONE)
53/*
54#define SONIC_DEBUG  (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\
55      SONIC_DEBUG_DESCRIPTORS)
56*/
57
58/*
59  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS))
60  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS))
61*/
62
63#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
64extern char SONIC_Reg_name[64][6];
65#endif
66
67
68/*
69 *  Configuration Information
70 */
71
72typedef void (*sonic_write_register_t)(
73  void       *base,
74  unsigned32  regno,
75  unsigned32  value
76);
77
78typedef unsigned32 (*sonic_read_register_t)(
79  void       *base,
80  unsigned32  regno
81);
82
83typedef struct {
84  unsigned32              base_address;
85  unsigned32              vector;
86  unsigned32              dcr_value;
87  unsigned32              dc2_value;
88  unsigned32              tda_count;
89  unsigned32              rda_count;
90  sonic_write_register_t  write_register;
91  sonic_read_register_t   read_register;
92} sonic_configuration_t;
93
94/*
95 ******************************************************************
96 *                                                                *
97 *                        Device Registers                        *
98 *                                                                *
99 ******************************************************************
100 */
101#define SONIC_REG_CR      0x00 /* Command */
102#define SONIC_REG_DCR     0x01 /* Data configuration */
103#define SONIC_REG_RCR     0x02 /* Receive control */
104#define SONIC_REG_TCR     0x03 /* Transmit control */
105#define SONIC_REG_IMR     0x04 /* Interrupt mask */
106#define SONIC_REG_ISR     0x05 /* Interrupt status */
107#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
108#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
109#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
110#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
111#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
112#define SONIC_REG_URRA    0x14 /* Upper receive resource */
113#define SONIC_REG_RSA     0x15 /* Resource start address */
114#define SONIC_REG_REA     0x16 /* Resource end address */
115#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
116#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
117#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
118#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
119#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
120#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
121#define SONIC_REG_CE      0x25 /* CAM enable */
122#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
123#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
124#define SONIC_REG_SR      0x28 /* Silicon revision */
125#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
126#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
127#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
128#define SONIC_REG_CRCT    0x2C /* CRC error tally */
129#define SONIC_REG_FAET    0x2D /* FAE tally */
130#define SONIC_REG_MPT     0x2E /* Missed packet tally */
131#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
132#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
133
134/*
135 * Command register
136 */
137#define CR_LCAM         0x0200
138#define CR_RRRA         0x0100
139#define CR_RST          0x0080
140#define CR_ST           0x0020
141#define CR_STP          0x0010
142#define CR_RXEN         0x0008
143#define CR_RXDIS        0x0004
144#define CR_TXP          0x0002
145#define CR_HTX          0x0001
146
147/*
148 * Data configuration register
149 */
150#define DCR_EXBUS       0x8000
151#define DCR_LBR         0x2000
152#define DCR_PO1         0x1000
153#define DCR_PO0         0x0800
154#define DCR_SBUS        0x0400
155#define DCR_USR1        0x0200
156#define DCR_USR0        0x0100
157#define DCR_WC1         0x0080
158#define DCR_WC0         0x0040
159#define DCR_DW          0x0020
160#define DCR_BMS         0x0010
161#define DCR_RFT1        0x0008
162#define DCR_RFT0        0x0004
163#define DCR_TFT1        0x0002
164#define DCR_TFT0        0x0001
165
166/* data configuration register aliases */
167#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
168#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
169
170#define DCR_WAIT0       0                 /* 0 wait states added */
171#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
172#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
173#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
174
175#define DCR_DW16        0       /* use 16-bit DMA accesses */
176#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
177
178#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
179#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
180
181#define DCR_RFT4        0               /* receive threshold 4 bytes */
182#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
183#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
184#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
185
186#define DCR_TFT8        0               /* transmit threshold 8 bytes */
187#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
188#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
189#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
190
191/*
192 * Receive control register
193 */
194#define RCR_ERR         0x8000
195#define RCR_RNT         0x4000
196#define RCR_BRD         0x2000
197#define RCR_PRO         0x1000
198#define RCR_AMC         0x0800
199#define RCR_LB1         0x0400
200#define RCR_LB0         0x0200
201#define RCR_MC          0x0100
202#define RCR_BC          0x0080
203#define RCR_LPKT        0x0040
204#define RCR_CRS         0x0020
205#define RCR_COL         0x0010
206#define RCR_CRCR        0x0008
207#define RCR_FAER        0x0004
208#define RCR_LBK         0x0002
209#define RCR_PRX         0x0001
210
211/*
212 * Transmit control register
213 */
214#define TCR_PINT        0x8000
215#define TCR_POWC        0x4000
216#define TCR_CRCI        0x2000
217#define TCR_EXDIS       0x1000
218#define TCR_EXD         0x0400
219#define TCR_DEF         0x0200
220#define TCR_NCRS        0x0100
221#define TCR_CRSL        0x0080
222#define TCR_EXC         0x0040
223#define TCR_OWC         0x0020
224#define TCR_PMB         0x0008
225#define TCR_FU          0x0004
226#define TCR_BCM         0x0002
227#define TCR_PTX         0x0001
228
229/*
230 * Interrupt mask register
231 */
232#define IMR_BREN        0x4000
233#define IMR_HBLEN       0x2000
234#define IMR_LCDEN       0x1000
235#define IMR_PINTEN      0x0800
236#define IMR_PRXEN       0x0400
237#define IMR_PTXEN       0x0200
238#define IMR_TXEREN      0x0100
239#define IMR_TCEN        0x0080
240#define IMR_RDEEN       0x0040
241#define IMR_RBEEN       0x0020
242#define IMR_RBAEEN      0x0010
243#define IMR_CRCEN       0x0008
244#define IMR_FAEEN       0x0004
245#define IMR_MPEN        0x0002
246#define IMR_RFOEN       0x0001
247
248/*
249 * Interrupt status register
250 */
251#define ISR_BR          0x4000
252#define ISR_HBL         0x2000
253#define ISR_LCD         0x1000
254#define ISR_PINT        0x0800
255#define ISR_PKTRX       0x0400
256#define ISR_TXDN        0x0200
257#define ISR_TXER        0x0100
258#define ISR_TC          0x0080
259#define ISR_RDE         0x0040
260#define ISR_RBE         0x0020
261#define ISR_RBAE        0x0010
262#define ISR_CRC         0x0008
263#define ISR_FAE         0x0004
264#define ISR_MP          0x0002
265#define ISR_RFO         0x0001
266
267/*
268 * Data configuration register 2
269 */
270#define DCR2_EXPO3      0x8000
271#define DCR2_EXPO2      0x4000
272#define DCR2_EXPO1      0x2000
273#define DCR2_EXPO0      0x1000
274#define DCR2_HBDIS      0x0800
275#define DCR2_PH         0x0010
276#define DCR2_PCM        0x0004
277#define DCR2_PCNM       0x0002
278#define DCR2_RJCM       0x0001
279
280/*
281 *  Known values for the Silicon Revision Register.
282 *  Note that DP83934 has revision 5 and seems to work.
283 */
284
285#define SONIC_REVISION_B   4
286#define SONIC_REVISION_DP83934   5
287#define SONIC_REVISION_C   6
288
289/*
290 ******************************************************************
291 *                                                                *
292 *                   Transmit Buffer Management                   *
293 *                                                                *
294 ******************************************************************
295 */
296
297/*
298 * Transmit descriptor area entry.
299 * There is one transmit descriptor for each packet to be transmitted.
300 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
301 * per descriptor.
302 */
303#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
304struct TransmitDescriptor {
305  rtems_unsigned32        status;
306  rtems_unsigned32        pkt_config;
307  rtems_unsigned32        pkt_size;
308  rtems_unsigned32        frag_count;
309
310  /*
311   * Packet fragment pointers
312   */
313  struct TransmitDescriptorFragLink {
314      rtems_unsigned32 frag_lsw;  /* LSW of fragment address */
315#define                      frag_link frag_lsw
316      rtems_unsigned32 frag_msw;  /* MSW of fragment address */
317      rtems_unsigned32 frag_size;
318  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
319
320  /*
321   * Space for link if all fragment pointers are used.
322   */
323  rtems_unsigned32        link_pad;
324
325  /*
326   * Extra RTEMS stuff
327   */
328  struct TransmitDescriptor       *next;  /* Circularly-linked list */
329  struct mbuf                     *mbufp; /* First mbuf in packet */
330  volatile rtems_unsigned32       *linkp; /* Pointer to un[xxx].link */
331};
332typedef struct TransmitDescriptor TransmitDescriptor_t;
333typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
334
335/*
336 * Transmit Configuration.
337 * For standard Ethernet transmission, all bits in the transmit
338 * configuration field are set to 0.
339 */
340#define TDA_CONFIG_PINT 0x8000
341#define TDA_CONFIG_POWC 0x4000
342#define TDA_CONFIG_CRCI 0x2000
343#define TDA_CONFIG_EXDIS        0x1000
344
345/*
346 * Transmit status
347 */
348#define TDA_STATUS_COLLISION_MASK       0xF800
349#define TDA_STATUS_COLLISION_SHIFT      11
350#define TDA_STATUS_EXD          0x0400
351#define TDA_STATUS_DEF          0x0200
352#define TDA_STATUS_NCRS         0x0100
353#define TDA_STATUS_CRSL         0x0080
354#define TDA_STATUS_EXC          0x0040
355#define TDA_STATUS_OWC          0x0020
356#define TDA_STATUS_PMB          0x0008
357#define TDA_STATUS_FU           0x0004
358#define TDA_STATUS_BCM          0x0002
359#define TDA_STATUS_PTX          0x0001
360
361#define TDA_LINK_EOL      0x0001
362#define TDA_LINK_EOL_MASK 0xFFFE
363
364
365
366/*
367 ******************************************************************
368 *                                                                *
369 *                    Receive Buffer Management                   *
370 *                                                                *
371 ******************************************************************
372 */
373
374/*
375 * Receive resource area entry.
376 * There is one receive resource entry for each receive buffer area (RBA).
377 * This driver allows only one packet per receive buffer area, so one
378 * receive resource entry corresponds to one correctly-received packet.
379 */
380struct ReceiveResource {
381  rtems_unsigned32        buff_ptr_lsw;   /* LSW of RBA address */
382  rtems_unsigned32        buff_ptr_msw;   /* MSW of RBA address */
383  rtems_unsigned32        buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
384  rtems_unsigned32        buff_wc_msw;    /* MSW of RBA size (16-bit words) */
385};
386typedef struct ReceiveResource ReceiveResource_t;
387typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
388
389/*
390 * Receive descriptor area entry.
391 * There is one receive descriptor for each packet received.
392 */
393struct ReceiveDescriptor {
394  rtems_unsigned32        status;
395  rtems_unsigned32        byte_count;
396  rtems_unsigned32        pkt_lsw;        /* LSW of packet address */
397  rtems_unsigned32        pkt_msw;        /* MSW of packet address */
398  rtems_unsigned32        seq_no;
399  rtems_unsigned32        link;
400  rtems_unsigned32        in_use;
401
402  /*
403   * Extra RTEMS stuff
404   */
405  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
406  struct mbuf                        *mbufp; /* First mbuf in packet */
407};
408typedef struct ReceiveDescriptor ReceiveDescriptor_t;
409typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
410
411typedef struct {
412  rtems_unsigned32  cep;  /* CAM Entry Pointer */
413  rtems_unsigned32  cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
414  rtems_unsigned32  cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
415  rtems_unsigned32  cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
416  rtems_unsigned32  ce;
417} CamDescriptor_t;
418
419typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
420
421/*
422 * Receive status
423 */
424#define RDA_STATUS_ERR          0x8800
425#define RDA_STATUS_RNT          0x4000
426#define RDA_STATUS_BRD          0x2000
427#define RDA_STATUS_PRO          0x1000
428#define RDA_STATUS_AMC          0x0800
429#define RDA_STATUS_LB1          0x0400
430#define RDA_STATUS_LB0          0x0200
431#define RDA_STATUS_MC           0x0100
432#define RDA_STATUS_BC           0x0080
433#define RDA_STATUS_LPKT         0x0040
434#define RDA_STATUS_CRS          0x0020
435#define RDA_STATUS_COL          0x0010
436#define RDA_STATUS_CRCR         0x0008
437#define RDA_STATUS_FAER         0x0004
438#define RDA_STATUS_LBK          0x0002
439#define RDA_STATUS_PRX          0x0001
440
441#define RDA_LINK_EOL        0x0001
442#define RDA_LINK_EOL_MASK   0xFFFE
443#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
444                                    /*   and the driver can process it */
445#define RDA_FREE            0xFFFF  /* SONIC can use it */
446 
447/*
448 *  Attach routine
449 */
450
451int rtems_sonic_driver_attach (
452  struct rtems_bsdnet_ifconfig *config,
453  sonic_configuration_t *chip
454);
455
456#ifdef CPU_U32_FIX
457void ipalign(struct mbuf *m);
458#endif
459
460#endif /* _SONIC_DP83932_ */
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